Note: Descriptions are shown in the official language in which they were submitted.
~2~3~79
This is a divisional application of Ser-ial Number 308,202
filed July 26, 1978.
B~CKGROUND OF THE INVENTION
Field of the Invention
This invention concerns weight measuring apparatus. ~ore
particularly, the invention is concernea with a ~ighing scale
system having an improved analog-to-digita~ conversion means
including a microcomputer which forms an integral part thereof,
,~
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Description of the Prior Art
~_
~eighing and computing scales must meet several stringent
requirements for performance and cost. The scales must be accurate
!0 enough to satisfy public weights and measures authorities, yet
be available at a reasonabl~ affordablè price and perform their ~.
operations within a period of time which is convenient for sales
transactions.
One of the important factors in digital scal~s upon
.5 which cost, accuracy and operation time depends, is the convexsion
o~ the unXnown ~nalog weigh~ signal corresponding to an article
we`ight to digita.l~data repr~sentative of the ar~.icle weight.
In the past, digital ~eighing and computing scales hav~
typically performed the anaIog-to-dic3ital conversion ~ith a
0 ~eparate distinct and indep~ndently controlled analog-to-digital
converter circuit whi.ch may provide its digital output to a data
processincJ means. Typ.ical e~amples are Williams, Jr. et al, U.S.
Patent ~Jo. 3,709,309 and L~shbough et al , U.S~ Patent No.
3,~62,569. This prior art ircuitry conventionally uses the
.j dual slope m2thod of analo~-to-digital conversion, which method
is.illustrated in Gilber~, U,S. Patent No~ 3,051,939 and ~mann,
IJ.~. Patent No. 3,31G,5~7. Triple slope analog-to-digital
convertcrs are shown in U.S patents 3,577,1~0 ~asnacs;
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.
3,582,9~7 Harrison; 3,678,506 Wheable; an-l ~e 28706 Dorey.
Reference is also made to U.S. Patent 3,937,287 granted to
.G. Pryor and R.C. Loshbough on February 10, 1976 relating
to data filtering~ The exemplary embodiment of the invention
described herein describes features shown in U.S. patents
3,962,569, Loshbough et al; 3,962,570, Loshbough et al;
3,9~6,012, Loshbouyh et al; and 4,004,139, Hall; and Canadian
application Serial ~o. 286,550, Hall et al.
Prior art weight measuring apparatus has generally
required circuitry separate from the data processing means for
performing the integrating, counting, and control functions
normally associated with an integrating type analog-to-digital
conversion. Attendant with the requirement for separate
circuitry is its cost and the relative inflexibility due to the
limited number oE functions performed by hardwired circuitry.
SUMMARY OF THE INVENTION
There is, therefore, a need for a weighing scale having
a relatively simple design which is capable of more effectively
utilitizing the data processing mecl~s to reduce the number of
components required to implement the analog-to-digital conversion
and thereby reduce the cost of the weighing scale and allow
the analog-to-digital conv2rsion to avail itself of the flexi-
bility afforded by the datia processing means.
The present invention achieves the foregoing needs by
providing a weighing scale system which employs a microcomputer
data processlng means which is integral to an analog-to-digital
conversion and which is used for controlling the sequence of
operations and computing tlhe required data for the scale
system. The requirement f~r separate control and counting
79
circuitry associated solely with the analog-to-digital
conversion is thereby eliminated, with the additional
advantage of allowing the analog-to-digital conversion to be
modified via a modification of the instructions of the
microcomputer.
In a conventional triple slope analog-to-digital
conversion, an analog signal is applied through a switching
circuit to an integrator circuit for a first fixed time
interval in order to drive its output from an initial level to
a level which is proportional to the amplitude of the analog
signal. Then a second integrating interval is begun in which
a clock-driv2n digital timing counter begins counting time
intervals and simultaneously a first reference DC source is
applied through the switching circuit to the integrator to
drive its output past a reference level. This level is
detected by a threshold detector circuit. The second time
interval may be extended an additional time interval beyond
the crossover of the reference level. Then during the third
integrating interval, the elapse of time is counted. The
slower rate permits the crossover to be more precisel~
detected. Upon detection of such crossover by the threshold
detector, the counting of the elapsed time is halted.
In the prior art a separate single digital counter
is used to count the clock pulses to accumulate a count oE
elapsed time for both the second and third integrating intervals.
Its most significant digits are used,to accumulate the
elapsed time count during the second intervals and its least
significant digits are used to accumula-te the elapsed time
count during the third interval,
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The control of the switching circuit is perfo~med by a micro-
computer and the output of the threshold detector is applied
directly to the microcomputer so that all counting and
arithmetic operations are per~ormed by the microcomputer~
The analog to digital conversion system also affects
other characteristics of a weighing and computing scale.
For example, an improved digital input weight filtering
~rrangement is provided which permits the improved accuracy
0 to be obtained by reducing the filter delay and at the same
time reducing the effects of vibration or jitter.
In order for a weighing scale to be able to provide
a choice of full scale capacities, it is necessary that
the weight signal or data be modified in either its analog
form or its digital form in a manner which is dependent
upon the particular scale capacity and units of weight which
are selected.
The weight can be ~etected according to a single one
of several possible scale capacities and weight units and
O then multiplied by an appropriate. conversion ~actor when
another scale capacity is sel~cted. This, however, requires
that a computer of such a weighing scale have a more complex
sequence of op~rations because for each selected scal~
capacity it rnust dea.l witl- substantially different numbers
in performin~ all of its ~arious checks and control functions.
Alternatively, the analog weight signal may be
amplified by an amplifica~iorl actor ~7hicll is unique for
each scale capacity~ This selective modification of the
analog gain has the disad~antage that it requires the use of
o either adjustahle or multiple circuit elements, such as
resistors, in the analo~ circuitry, one of which must be
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~ ~28~79
-- manually switched into the circuit for each selected
amplification factor corresponding to each selected scale
capacity. The use of such alternatively selectable circuit
elements requires a substantial additional expense and
creates problems in calibration.
These problems can be reduced by causing the full
capacity analog weight signal ~or each scale capacity to
produce the same digital number at the output of the analog-to-
digital converter. This also permits a single span control
to set the full capacity output for all selectable scale
capacities. For example, in the exemplary embodiment of the
present invention, a full scale weight for each scale capacity
will produce a digital output of 30,000 net effective weight
increments which are termined raw weight increments. The
number of raw weight increments is then multiplied by a
factor, depending upon the scale capacity to obtain the
proper weight units. ``
The present invention provides substantially the same
digital data with a full capacity weight for all selected
~0 scale capacities without requiring multiple circuit elements
and without requiring modification of the analog circuit gain.
This aspect oE the present invention is provided by the
microcomputer implementation oE the analog-to-digital
conversion.
~nother feature oE the present in~rention relates
to the computing and displaying of a net weight. The prior art
includes weighing and computing scales upon which a food
container or other tare weight may be placed, weighed and
havc the tare weight entered into memory. This stored tare
weight is available for later subtraction from the gross
weight of the filled container to compute and display the
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llZ8~79
net weight of the conten-ts.
Whenever such a tare weight container is placed on
the platter of a scale operating in such a net mode, the
digital display should indicate a zero weight. I~owever,
drift and hysteresis effects may cause the digital data
representing the subsequent ~.easurement of the weight of
the container to be different ~rom the prevIously measured
weight data which was stored as the tare wei~ht. Consequently,
a subtractîon of the earlier stored tare weight from the
currently measured wei~ht may cause an erroneous non-zero
number to be displayed.
It is a feature of the present invention that
such drift or wandering in the digital tare wei~ht data is
automatically tracked and the stored tare weight is
automatically updated so that an accurate net zero indication
is maintained.
The objects and features oE the invention will be
apparent ~rom the speci~ication and claims when considering
in connection with the accompanying drawings illustratinq
tlle exemplary embodiment o the invention,
The means, apparatus, and structure, by which the
above novel improve~ents, in accordance with the present
invention, are achieved in the exemplary embodiment described
herein, comprlses various registers~ counters timers~ ~lags,
storage spaces, together with specific routines and routine
loops for the control o~ the respective apparatus or means by
the central controlled unit. In addition, numerous switches,
lamps and display devices cooperate with the central control
unit and the various storage spaces, counters, timers~ etc.,
which apparatus comprises input and output means for the
system.
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1iL28~79
According to one aspect o~ the present invention
there is proived in a weight measuring system computing means
of the type having circuit means for generating digital gross
weight data, a tare memory means for storing data representing
a tare weight, and means for periodically generating a net
weight signal from the difference between the generated
gross weight data and the tare weigh-t data stored in the tare
memory means, the improvement comprising means for modifying'
the tare weight data stored in the tare memory means by a
predetermined amount to decrease the absolute value of the
net weight in response to the generation of net weight data
within a preselected range.
According to a second aspect there is provided a
method for tracking and correcting the net zero indication
of a weighing scale, the scale having means for generatiny
a weight signal, means for storing a tare weight and means
for subtracting the tare weight from the generated weight,
the method comprising:
a) subtracting tare weight data from a generated
gross weiyht data to generate net weight data;
b) comparing the net we.ight data with a
preselected weight range to determine whether the net weight
data is within the range; and
c) modifying the tare weight data by a
predetermined amount to decrease the absolute value of the net
weight data in response to the net weiyht data being within
the range.
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DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram illustrating the apparatus
of the exemplary embodiment of the invention.
Fig. 2 is a diagram illustrating the layout and relative
interrelationship of the circuit diagrams of Figs. 3 through
8 and is shown on the same sheet as Fig. 10.
Figs. 3 through 8 show the detailed circuitry of an
exemplary embodiment of the invention.
Figs. 9 through 11 are block diagrams of the integrated
circuits forming the central processor, memory and general
purpose keyboard and display lnterface devices used in
combination with the circuitry of the exemplary embodiment
of the invention.
Fig. 12 is a diagram illustrating the operation o the
exemplary embodiment of the invention.
lS Fig. 13 is a random access memory assignment table
illustrating the assignments for the memory o~ the exemplary
embodiment o~ the invention.
Fiys. 14A through 14Z are 10w diagrams illustrating the
operation o the preferred embodiment o the invention (Fig.
numbers 14Q and 14U are not used for clarity).
In describing the preferred embodiment of the invention
illustrated in the drawings, specific terminology will be
resorted to for the sake o clarity. Ho~Jever, it is not
intended to be limited to the specific terms so selected,
~5 and it is to be understood that each specific term includes
all technical equivalents which operate in a similar manner
to accomplish a similar purpose. For example, the term
connection is not necessarily limited to direct connec-tion but
also includes connection through other circuit elements.
. ~ ~128~79
GENER~L DESCRIPTION
. _ _
The exemplary embodiment of the invention is illustrated
in the block diagram of Figl 1. A load cell 40 mechanically
supports a platter 12 and is supplied with electrical energy
by a power source 42. The load cell applies an analog weight
signal through a preamplifier 44 and filter 46 to a switching
circuit 50. The analog ~eight signal has an amplitude which
is dependent upon the weight supported by the load cell 40.
The switching circuit 50 is also connected to the power
supply so that not only the anaiog signal but also two refer-
ence DC sources can be sequentially applied to the integrator
51 during the performance of a triple slope A/D conversion.
The output of the integrator is amplified by an amplifier 52
and applied to a threshold detector so that the crossover of
the integrator output with its reference output level is
detected by the threshold detector 53. The output of the amplifier
is also connected to the switching means 50 for use in resettlng
the integrator 51. The output of the threshold detector 53
: is applied to a mlcrocomputer 54 which is also connected to
the switching circuit 50 for controlling its switching functions.
The microcomputer 54 is connected to a printer 28 and
through latch decoder and driver circuitry 56 to indicator
lamp displays 26. Operational mode selector switches 22 are
also connected to data input terminals of the microcomputer
54.
The microcomputer is further connected to a general
purpose keyboard and display interface 58 for receiving data
from a keyboard 20 and transmitting data through a decoder/
driver 60 to digit displays 24. The "PREPACK ON/OFF" switch
16 and the "Z" key 17 are individually connected to discrete
inputs to the microcomputer 54.
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In this exeml)].ary ~ml)odiment, the analog-to-di~ital
convers ion i s pc~rrorrned by the combination of the s~Jitching
circuit 5(), the refel-ence DC sources deri~ed Erom the power
source 42, the i.ntegrator 51, the threshold detector 53 c~nd
the mi.crocomputer 54. The am~ cier 52 is provided to
ampliI'y the integrator output so that the threshold detector
wi,ll n~ore accura.t.ely deterrnine when the integrator output
crosses the threshol~ volt:a~e.
The microcomputer 54 includes stora~e registers in which
the elapsed time counts, whieh are derived froltl a micro-
eomputer program or instruetion loop, are aceumulated. It also
ineludes stored clata for eaeh scale eapacity. The mieroeomputer
54 i.ncludes a cent,ral proees~or, assoeiated memory and stored
data f-or control lin~, the s~7itehing eireui t 50 to appropriately
apply the inputs to the integrator 51 i.n the proper sequenee
an~l at the proper time, ,~or interrogating the output of the
tl~resho].d det(eetor 53, and for arithmetieally processing the
nccumu] al:e~l elapsed time i.ntervals or eo~mts .
Fi~. ].2 illusl:rate~s, in simplifie(l form, the si,~naL
relationcr,hi p~s wh:ich are mos t si"nifieant in de.seribing the
inventiol. T~le vertieal axes repre~ent atnplitudes wslieh arc!
not draw~ o sc..l'lc~ in order t:h.lt t:hc prineiples o operation
rrl~y be more elearl.y i.'llustratcd. The l~orizont~l axis
r epreC;ellts time.
'l`he top mos t ~rap~ 12A clcp iets thc, eomputer interro-
~,al:io~ at-~l coc~nt inl~ eyeles and in tlle exempl.~ry embodirncnt
ilave ~-; 6~ mi erosecond period. '~`hese are not: clrclwtl to scale
because sevel^a]. tnol.lsclnd such cyeles would be neecled. Each
c~rcle rcpresent:s the length oE time required fc!r the miero-
3~J corn,nllter to loop through its intcrrogatiol and indexing
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112~79
sequence of operations.
Below that is a graph 12B illustrating in a solid line
the output of the integrator 51 and also illustrating, with
broken lines, portions of alternative outputs from the
integrator 51.
Finally, the lowest graph 12C illustrates the output
state of the thresho~d detector 53. Its ~hreshold level is
set to correspond to the initial level VO at the output of
the integrator 51 and its output is high when the output of
the integrator is negative and is low when the output of the
integrator is positive.
Referring to Figs. 1 and 12, at time To to microcomputer
54 switches the switching circuit 50 to apply the analog
; signal, which was derived from the load cell, to the input of
the integrator 51. Thiæ analog signal continues to be applied
and is integrated for the entire time interval Tl. This input
causes the output of the integrator to be driven from its
initial level VO along slope Sl to level Vl. The magnitude
o Vl-VO is a directly proportional function of the amplitude
of the analog signal and is also a function of its integration
time Tl.
The time interval Tl is a different but fixed and,constant
time for each different scale capacity and is controlled by the
microcomputer 54 and is obtained by reading permanently stored
,?5 timing data from the computer memory, loading it into suitable
registers and sequentially setting the registers in accordance
with selected timing loop instructions.
One un.ique feature of,the present invention is that
this first integrating interval Tl, during which the analog
signal is integrated, is different f~r each scale capacity
11~8~79
.
and therefore different data is stored i~ memory and loaded
into the time delay registers for each scale capacity.
A particular Tl time is chosen for each scale capacity
so that whatever scale capacity is selected, a full scale
weight on the platter for that scale capacity will always
drive the integrator output to substantially the same level.
Assume for example that the above described integration along
integrator output slope Sl represents a 20 pound weight on the
platter 12 with a 30 pound scale capacity selected, then a
30 pound weight on the platter 12 would integrate along slope
SB to arrive at VMAx at the time TlA after time interval Tl.
If, for example, a 15 kg scale capacity were then selected, a
shorter analog signal integrating the time would be provided
by the microcomputer 54 so that a 15kg weight on the scale
platter would drive the integrator output along the slope Sc
to reach VMAx at a time TlB. In the exemplary embodiment,
the following analog signal time intervals are used:
6 kg x 2g - 239.660 milliseconds
15 kg x 5g - 95.790 milliseconds
30 lb x .01 lb - 105.625 milliseconds
At time TlA which is the end o~ the irst integrating
time interval Tl, the microcomputer 54 switches the switching
circuit 50 to begin the second integrating time interval T2
by applying a first reference DC source Il to the input of the
integrator Sl. This first reference DC souxce Il is then
integrated to drive the integrator output level, which repre-
sents the sum of the integral obtained during Tl and the
integral being performed during T2, along slope S2 back towards
and past the initial integrator output level VO
After initiating this second integrating interval T2,
the microcomputer begins periodically interrogating the output
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oI the threshold detector J3 look.ing for the tr~nsition
whicl~ inc~icates the crossover of the integrator oukput level
wi.th its initial level VO.
~ ach time the microcomputer interroc~ates ~he output of
the threshold detector 53 and finds that crossover has not
occurred, it increments a m~mory re~ister referred to as the
T2 register or T2 counter which is assigned to accumulate such
intexrogation counts. Each such interrogation and countin~
cycle or instruction loop requires the identical time to
perform which in the exemplary embodiment, is 65m sec.
Even~ually, at a time labelled T2A in Fig. 12B, the output
oE the integrato.r 51 crosses over its initial level VO causing
th~ oul-put of tll~ threshold detector to switch ~rorn a hi~h
state to a low state. This transition may occur anywhere
withi.n an inte.rrogation and indexing cycle or the end or
be~inning of such a cycle. However, because of the digital
alIlb.iguity t:he Microcomputer 54 will not detect this transition
until it in~er.rogates the output of the threshold detector 53
~l: ti.me T2B~
~hen the switch.ing o~ the output o~ the threshold
d~.tector 53 is detected at T2B by the microcomputer 54, no
moxe .inl:errogation and inclexing cycle counts are accumulated
in the memory r~Jist~.r. The.reforc, the digit~1 count clccumu-
lcited i.n t}le first m~mory register at tirne T2B represents
tIle ;um o:E the c~mplitude (Vl-VO) plus ~Iny oversIloot V2-VO
0~ 910p-` S2, b~yond level VO.
On occas:;on, the coinci.dc!nce oE the i.ntegrat:or ou-tput
with the tllresllold level VO will occur re:l.ati.vely near the
end o.~ a countin~ cycle. l'he possibility then e~ists that
c.i.rcui.t swi.tchi.n~, which occur~ a-t the enI o~ the com~uter
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. . .
interrogating cycles, may cause transients which might cause
erroneous operation. For example, if the crossover occurs
just before an interrogation of the output of the threshold
detector 53 by the microcomputer 54 so that very little over-
shoot occurs, then the output level of the integrator will be
close to the level VO. If the next integrating interval T3
were then begun, a computer clock pulse may cause the threshold
detector 53 to switch states prematurely.
A unique feature of the present invention is that these
crosstalk problems can be eliminated by providing an extra
delay at the end of the T2 interval after the microcomputer 54
has detected the VO crossover. Conveniently, this delay
interval, labelled T2C, can be made equal to one interrogation
cycle and will cause the integrator output to be driven further
along S2 from V2 and V3, However, the count accumulating memory
is not incremented so that no count is added to the memory
register for that extra cycle.
After delay time T2C, the computer 54 switches the
switching circuit 50 to apply a second reference DC source
I2 to the integrator 51. This second reference DC source
I~ is substantially less than the first reference DC source
Il which was întegrated during interval T2 because it is
desired to integrate at a reduced slope S2 in order to obtain
more precisely the time of the coincidence of the integrator
output with its initial level VO' II1 the exemplary embodiment
of the invention, the reference source which is integrated
during the T2 interval is 32 times greater than the reference
source which is integrated during the T3 interval. Therefore,
the magnitude of the slope S2 o~ the integrator output during
interval T2 is 32 times greater than the magnitude of the slope
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1~28~79
during interval T3.
Upon the bec3inn ing of interval T3, the microcomputer 54
again goes t'hrou~h interrogating and counting cyclcs just as
.it did clur.i.ng interval T2. Ilowever, dur.ing interval T3, the
interrogati.ng and countin~ cycles are counted b~ incrementing
a memory rec3ister referred to as the T3 counter or T3 register.
T'hen, 7 as ~ring interval T2, counts continue to be accumulated
in the second memory register until the first interrogation
of the threshold detector 53 by the computer 54 which occurs
after coincidence of the integrator output with the threshold
level Vc~. When the computer detects the resultant output
level c11anye of the threshold deteckor 53 at time T4, and T3
i.ntec3rating inte3-va.l and the cou~t accumulation is stopped by
the mi~..rocomputer 54.
~ t tim~ T~, the count accumulated in the second register
during inkerval T3~ is directly proportional to and represents
the differencc betw~e.n the integrator output l~vel V3 at ~2C
which i.s ;lt the 'be-.~inning of i.nterval T3 and the integrator
output level ~t T~ at the end of int~rval T3r For computational
purposc:(3~ the i.ntegrcltor output level at the cnd of T3 is
assumed to be V0. Si.nc~ this is a dic3i.tal al~:;gUity within
o~le of the countinc3 c~c.1.(~..s fnr ~e inte(3ral:i.on along the
].~.sser slope S3, it will b~ appar~l1t from th~ ollowing dis~
cus~i.c.~n that the errc)r i5 less than one part i.n 30,000 at full
~c.~ale capac.ity in tlle exemplary erl~odimellt.
~ronet,lleless the ti.me T~, w~len the m;.crocomputer detects
-the crc~;~o~e3~ here wi.ll a~3ain ~e ~ome ovcrshoot past the
illiti.al level V0 i:E t'ne crossover occurs between pe3~i.0dic
interrogal,ion~; c>:E the output of the threshold detector 53.
In order to remove the a:EEect oE this o~el-shoot and
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.. .. ..
accurately reset the integrator precisely to the identical
VO prior to each integration, the microcomputer 54 switches
the switching circuit 50 to effectively connect the integrator
output to its input. .This negative feedback drives the
integrator output to VO follc,wing T4 by effectively discharging
the capacitor of the integrator 51. This is desirable because
the current may drift prior to the next integrating cycle and
because the overshoot and the end of the interval T3 may
produce an error in the time of crossover during the T2
interval in which the integration is done along the steeper
slope S2.
The integration functions of the triple slope A/D
conversion are completed with the accumulation in each of two
memory registers of the digital count data taken along slopes
S2 and S3. The microcomputer must now take this data and
derive a digital number which is proportional to vl-vo and
which therefore is proportional to the amplitude of the analog
input signal which was integrated during time interval Tl.
The counts in the T2 register are proportional to Vl-V2~
The counts accumulated in the T3 register are proportional to
V3-Vo. However, these counts were derived from the integration
of two different reference DC sources of substantially
different amplitudes. Therefore each T2 count represents a
di~erent and greater quantity of integrator output amplitude
and thus a greater weight increment than is represented by
- each T3 count. In the exemplary embodiment, the first
reference DC source Il is 32 times greater than the second
reference DC source I2 and therefore each T2 count represents
32 times as much amplitude ( 32 raw weight increments)
as does each T3 count.
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.,
In order to equaliYe the value of each count in the T2
and T3 counters, the microcomputer 54 first multiplies the T2
count by the ratio of 11/I2 which in the exemplary embodiment
is 32. ~here upon the result represents the raw weight
increments.
By way of example, 600 interrogating and counting cycle
counts may have been accumulated in the T2 register in driving
the integrator output from Vl to V2 and 45 interrogating and
counting cycle counts may have been accumulated in the T3
counter in driving the integrator output from V3 to VO during
interval T3. Consequently, in accordance with the invention,
the microcomputer will multiply 600 by 32 to obtain a product
of 19,200 raw weight increments represented by V1-V2.
The microcomputer then processes the T3 count to convert
li it from a number representing V3-Vo to a number representing
V2-VO. This is done by subtracting from the T3 count a number
of counts representing V3-V2. Since the integration along
slope S2 from V2 to V3 required ~ne interrogating and counting
cycle during time T2~ that interval T2C represents the same
amplitude as is represented by a number of T3 counts which is
equal to the r~tio of the first reference DC source Il to the
second constant DC source I2. Consequently, the microcomputer
i subtracts that ratio Il/I2 from the accumulated T3 count.
In the above example for the exemplary embodiment, the
2 nuMber 32 is the ratio which is subtracted from the T3 count
of 45 yield a difference of 13 counts. These 13 counts
represent 13 raw weight increments represented by V2-VO.
Therefore, the microcomputer can now arithmetically
derive the number of raw weight increments represented by
Vl-VO by subtracting this difference oE T3 counts which represents
V2-VO from 32 times the number of T2 counts. In the ex2mple,
I~Z8~79
the microcomputer subtracts 13 frorn 19,200 to yield 19,187
raw weight increments.
This digital number is proportional to the amplitude
- of the analog weight signal which was integrated during Tl.
In the exemplary embodiment this digital represents weight
increments which are referred to as raw weight increments
herein.
Each weight indication is then filtered by an improved
`~igital filter. Each weight, when obtained, is subtracted
from the filtered weight and the difference divided by two.
A one is then added or subtracted from the result to make
the result approach the last weight and the last weight
corrected by the final result.
This digital number of raw weight units is multiplied
by the computer at a later time by the computer by a factor,
depending upon the scale capacity to obtain the weight in
the proper units for display.
The present invention maintains an accurate zero indicati.on
when the scale is not operating in the net mode and also
maintains an accurate net zero indication in addition by
updating the data stored in a tar~ weight register.
Tare weight data may be entered into a tare memory
register by either of two methods. The digits of a tare
weight may be keyed in through the keyboard 20 and this is
referred to as a keyboard tare. The tare weight data may
also be entered into memory by placing an empty container or
other tare weight on the platter and depressing the "T'~
key. This is referred to as manual tare and causes the scale
to read the tare weight and store it in the tare memory.
After a tare weight i5 properly entered hy either of
these operations, the computing and weishing scale displays
-18-
~Z8~79
the net weight, which is the difference between the weight
of an object on the platter and the weight data stored in
the tare register. Consequently, an objec~ weighing the same
as the tare weight, for example, the same empty container,
S should cause a zero net weight to be displayed. A lessor
weight on the platter will generate the display of a negative
weight.
Unfortunately, creep, hysteresis effects and drift may
cause an object on the platter to generate slightly different
tare weight data at different times. Similar difficulties
have been observed in the maintenance of a gross zero
indication as described in Loshbough et al, U.S. Patent No.
3,986,012. In that situation, a separate ~uto zero register
is used to store a correction factor for automatically
correcting the gross zero indication. However, it has been
discovered that the same auto zero register cannot be used
for net zero tracking because whenever the scale reverts from
a net mode of operation back to its gross mode, the auto
i~ zero register would still contain net zero tracking data and
be erroneous for gross auto zero correction purposes.
The invention involves the periodic updating of the
tare weight data to track such wander in order to maintain
the display of a zero net weight under the conditions for
which a zero net weight should be displayed and in order to
~5 ~se the most recently detected and most accurate tare weight
data as a reference which is subtracted from total gross
wei~ht to compute net weight.
Each time the microcomputer 54 computes a net weight, it
examines that weight data to determine whether the tare
we~ght data should be modified. If the net weight is found
to be exactly zero, then no drift has occurred and no trac~ing
-19-
1128~7~
.
is necessary. Since a zero indication already exists, the
microcomputer skips the remaining net zero tracking sequence
of operations.
However, if the computed net weight is not exactly zero,
it is then examined to determine whether it is close enough to
a net weight of zero that its departure from zero can be
attributed to creep, drift or hysteresis effects rather than
to a change in the weight placed on the platter.
This decision, whether the net zero tracking should
actually be performed, is made by determining whether the
net weight is within a preselected, narrow, weight range or
band centered about a net weight indication of zero. There-
~ore if the computed but non-zero net weight is outside this
range, the remainder of the net zero tracking sequence of
operations is skipped. However, if it is within the range,
! net zero tracking is performed by modifying the previously
stored tare w~ight data to compensate for the shift or wander
of the net zero.
Data representing the preselectèd range within which
` net zero tracking is performed is permanently stored in the
memory of the microcomputer 54. ~n the exemplary embodiment
of the invention this range is a predetermined number of
increments which represent different weights for each scale
capacity so the net zero tracking sequence of operations is
done with data which has already been multiplied by a scale
conversion factor to represent output increments of weight
rather than units of raw weight increments.
For example, in the exemplary embodiment, for the
followiny scale capacities, the net weight must be within
the following ranges in order for the tare weight data to be
modified ~o trac~ the net zero:
-20-
1128~79
Scale Capacity Ranqe
6kg x 0.0021<9 + O.OOO~kg
15kg x 0.005Kg +00.0002kg
301b x 0.01 Ib +00.004 lb
If the net weight is within the preselected
range for the selected scale capacity, then the micro-
computer modifies the tare weight register in a direction
which will reduce the next computed net weight by one
increment of its least significant digit.
This is done by algebraically adding to the
tare weight data a one having the same sign as the pre-
vlously compu-ted net weight.
For exampleJ for the 30 lb x .01 Ib capacity,
a compul-ed ne-t weight of +00.002 pounds will cause a +1
to be added to the least significant digit of the tare
weight da-ta, any carry being appropriately propaga-ted.
If the s-lored -tare weight was 00.192 pounds it will
become 00.193 pountls. Therefore, the next timt-) a net
weight is computcd for the idcntical gross wt3ighl data,
the net weight wtll be -~00.001 pounds.
If lht-~ gross weight dala tlot-)s not chanle,
con-lTnued repelition of the above st-~qut)nce o~ opt-)ratiorls
wtll contlnllt3 lo incromcnl the slored tare weighl data
ulllmately lo cause a nel weTghl indication o~ OO.ooo
pounds. Thus, in the exemplary embodimenl 00.00 will be
displayed when only the 4 most significan-l digi-ls are
clisplayed. Tht-~ repelition of 1-hese net weigh-l tracking
opera-l-ions occur approxima-iely five times per sccond in
the exemplary embodiment.
:.:
21
jb/
,; :'
1128~79
-
The exemplary embodiment of the invention ineorporates
and cooperates with many features shown in U.S. patents
3,962,569; 3,962,570; 3,986,012; and 4,004,139; and in
Canadian applieation Serial No. 286,550, as well as parent
applieation Serial Number 308,202.
However, these features are briefly described to
the eY.tent whieh is helpful to enable those skilled in the
art to construet an embodiment of the invention and to
practice the invention.
The exemplary embodiment eomprises a digital weighing
and eomputing seale to determine the weic3ht of merehandise,
to compute the total price or value of t:he merchandise and
to display, and optionally to print, the price per unit
weight, the weiqht oE the merehandise and the total value
or total price of the merehandise.
Fig. 1 is a bloek diagram of the exemplary embodiment
of the invention and was broadly deseribed above. The
exemplary embodiment has input and output struetures whieh'
may be explained in more detail.
The first input deviee is thc load eell ~0 linked
to a pla-tter 12 upon which mereh~lndise is support~d. The
load eell 40 provides the c~nalog output sign~l W]liC`21 :i.S
related to th~ wc?iclh~ of thc- merehandi3e.
The seeoncl group of inputs eompriseC. operator
aceessible swlt:ches 20 :including a "PREPACI~ on/oEE" switch
16 for seleetincJ a preE)c~ck modc oE opercltion an(l a keyboard
20 havillcJ keys labelled and pllysiccllly arrallcJed as il:lustrat-ed
in r~ti9. 1. The "PREPACK on/ofE" sw.itch i5 not provided ~or
UK modes of operation when IIalf Pence prieing is used.
~hile -th~ "PREPACK on/oEf" switch 16 is not ~lectrically a
part oE
.
" - 22 -
csm/~
.
1~283t79
.
.. ~ .
the keyboard, it is conveniently positioned adjacent the
keyboard for ease of access by the operator.
The third group of inputs comprises a plurality o~
programmable mode selector switches 22 which are selectively
switched at the factory or by a service technician in the
field and are inaccessible to the operator. These mode
selector switch~s 22 are labelled as indicated in Fig. 1
and are switched to those operational modes which are appropriats
for the weight and currency units, legal standards and require-
ments and to the merchandisiny and pricing methods of the
particular store in which the weighing and computing scale
will be used.
The weighing and computing scale embodying the present
invention also has three groups of output devices. The
first group consists of two identical sets of three numerical
display devices 24. One set is ~.ounted so that it is visible
to the scale operator and a duplicate set is mounted to be
visible to the customer or purchaser of the merchandise.
Each display device contains five, cold cathode, gas
discharge display di~its with three lower commas, each digit
having seven segments to display any number from zero through
nine. The three displays of each duplicate set ordinarily
display price per unit, net or gross weight and total value.
The second output group comprises a pair of duplicate
front and back indicator lamp displays, one facing the
operator and one facing the purchasing customer. Each
indicator lamp display has six translucent windows upon which
labels are printed and which are at ti~es backlighted by
suitable lamps for making the labels visible. As illustrated
in Fig. 1, the labeIs include "ZERO", "NET", "P~.EPAC~", "1~4",
"1/2" and a sixth legend which is alternati~ely labelled at
-23-
.
112~3~79
the factory either "LB" or "KG".
The third output is a printer 28 which is optional.
The "Z" key 17 is operated to zero or null the scale.
After power is first applied to the weighing and computing
scale embodying the present invention or after a power
interruption, no unit price data or tare weiyht data w~
be accepted and no total price or value will be displayed
until the exemplary embodiment has been so zeroed. The
scale may also be zeroed at other times using the "2" key.
The scale is zeroed in response to depression of the
"Z" key 17 when no substantial weight is on the scale by
loading the presently detected weight into a memory register
for subsequent use as a correction factor. In subsequent
weight measurements this correction factor is subtracted
; 15 from the detected weight to provide a corrected weight.
Consequently a zero weight indication will be displayed when
; there is no weight on the scale.
In order for the exemplary embodiment to perform the
zero operation in response to depression of the "Z" push-
button l7, all of the following four conditions must exist.
These interlocks prevent the customer from being defrauded
by intentional or accidental creation of an erroneous zero.
First, the "Z" pushbutton 17 must be depressed continuously
for at least 1.5 seconds. Second, the platform of the scale
must have been motionless for a predetermined interval of
time. Third, there must be no tare weiyht data stored in
the memory registers of the exemplary embodiment. Fourth,
there must be no significant weight on the platter.
Shortly aEter the exemplary embodiment has been zeroed
3~ in this manner the lamp behind the "ZERO" legend of the
,
~2~-
,
l~Z8~79
.. .
indicator lamp display 26 will be illuminated.
The keyboard 20 is a 4 x 5 matrix in which 15 of its
key positions are used. The 10 keys labelled "0" through
"9" are used to key in price per unit information and, under
conditions subsequently described, may ~e used to key in a
tare weight.
Tare weight data may be entered into memory registers
in one of two ways. First, a known tare weight may be keyed
in by using the keys labelled "0" through "9" of the keyboard
20 and then subsequently depressing the "T" key within two
seconds after entry of the last tare weight digit. Such a
keyboard entry of tare weight data is accepted only if the
corresponding mode of operation is selected by the appropriate
mode selector switches 22. Second, a~ empty container or
other object of unknown tare weight may be positioned on the
platter 12 and the "T" key then depressed to cause the
exemplary embodiment of the invention to automatically store
in memory the weight of that object as the tare weight. This
is termed a manual tare operation. A tare wei~ht will be
accepted and entered into memory only when certain conditions
exist which are described in connection with Figs. 14~-14Z
in the detailed d~scription of the operation of the exemplary
embodiment.
I an operator discovers that erxoneous tare wei~ht data
has been entered, the tare data may be cleared ~y pressing
the key with the numeral "0" and then pressing the "T" key
~ within 2 seconds of the operation of the "0" key. ~lowever,
; such a clearing of the tare data will only be accepted and
the tare data will be cleared only if the net weigh~ on the --
scale is less than 10 scale increments. This prevents the
,: ,
-25-
i~28! 79
. . j .
defrauding of a customer by the erroneous clearing or
changing of the tare data while an object is on the platter.
After the entry and acceptance of tare weight data,
the "NET" legends of the indicator lamp displays will be
backlighted to signify that the exemplary embodiment is in
a net mode of operation and therefore that its displayed
data is a net weight.
If tare weight data has been entered by a manual tare,
then the removal of the container will cause the exemplary
embodiment to display the tare weight preceaed by a negative
sign.
The ten ~igit keys 0 through 9 are used to enter the
price per unit weight either after tare data has been entered
into memory or, under no tare conditions, by keying in the
price per unit and failing to depress the "T" key.
The fr~ction keys 21 and 23 bear, respectively, the
legends "1/2" and "1/4". These fraction keys are depressed
to input the inormation that the pricing i5 per 1/2 unit
or 1/4 unit of weight. Depression of a fraction key 21 or
23 at the appropriate time will cause the corresponding
fractional legend on the indicator lamp displays 26 to be
illuminated .
The "CLEAR" key of the keyboard 20 may per~orm two
different functions. First, any price data which has been
entered may be cleared by depressing the "CLEAR" key. Second,
when the "CLEAR" key is pressed and held in a depressed
position, all output displays will be blanked or held off.
If the pushbutton is released and subse~uently agaîn held
in a depressed state, all display segments and all display
indicating lamps wiil be turned on.
-26-
`` l~Z~3~79
.
These two modes permit the displays to be checked to
make certain that there are no short circuits which are
exroneously turning on display`segments and no open circuits
which are preventing display sigements from being turned on.
When the weighing and computing scale embodying the
present invention is used with a printer 28, the operator may
depress the "PRINT" key to initiate the printing of an
appropriate label beari,ig the price per unit, the total weight
and the total value.
The manually programmable mode selector switches 22
comprise a plurality of individually operable, single pole,
single throw switches. Their functions are enabled, that is
their labelled conditions exist, when the switches are on or
made.
The exemplary embodiment of the present invention has
three selectable scale capacities, these are: 15.000 kg x
0.005 kg., 30.00 lbs. x 0.01 lbs. and 6.000 kg x 0~002 ~g.
For selecting the particular scale capacity which is desired,
two capacity-enabled mod~ selector switches are provided, a
~0 first s~itch 1 fox selecting the 6 kg scale and a second
switch 2 for selecting the 30 lb capacity. If both of these
mode selector switches are off, then 15 kg scale capacity is
chosen.
Under most conditions, the price pex unit and the total
price will be four digit numbers fxom 0 to 99.99. However,
mode selector switches are provided to permit either or both
of the price per unit and the total price to be displayed as
a five digit number. Selection of these modes is accomplished
; by switching to the on position the mode selector switch 3
labelled "5 digit unit price" and/or the mode sel~ctor switch
.,.
.,
, -27-
~., ,, : ~ .. .
l~Z8$?79
4 labelled "5 digit total price."
A mode selector switch 5 labelled "x10 EXPAND" provides
a mode which increases displayed resolution by causing the
display of the raw weight increment data. This mode may be
used when calibrating, servicing or testing the exemplary
embodiment.
A mode selector switch 6 labelled "PRINT INHIBIT", when
switched to its on position, will cause printing to be inhibited
for weights less than 20 scale increments. A mode selector
10 , switch 7 labelled "KEYBOARD TARE ENABLE" is switched on to
permit tare weights to be entered on the keyboard as describ2d
above.
The mode selector switch 8 labelled "AUTO-CLEAR PRICE
AND TARE" may be switched to its on position so that whenevex
the scale weight goes above ten scale increments and remains
above ten increments for one second or longer and then returns
below ten scale increments, the price per unit data and the
tare weight data will be automatically cleared. This avoids
the necessity of requiring the operator to manually clear
the price per unit data and tare weight data each time
merchandise is wei~hed.
"TARE ~NDATORY" mode selector switch 9 may be switched
to its on position to require the input of a tare weight before
the exemplary embodiment will compute and display the total
price~
The mode selector switch 10, labelled "300 PRINTER
ENABLE" is provided for use with the model Toledo/300 Auto-
matic label printer manufactured by the Toledo Scale Division
of Reliance Electric Company. When switched to its on
position, it limits the printing of price per unit, weight
,,
-28-
28~79
., ,
and total value to four digits each.
Mode selector switch 12 labelled "UK" enables half penny
pricing for the United Kingdom.
- The mode selector switch 13, labelled "PRICE PER UNIT",
is switched to its on position whenever it is desired to
permit iactor pricing (e.g., price per 1/4 and 1/~ pound), to
be entered on the keyboard and yet have the price per pound
displayed.
In some areas a "price by count" mode of operation is
desired. To allow this mode to be elected, the "PREPACK on/
off" switch 16 may be provided in an alternate embodiment
with a third position labelled "price by count".
When the "PREPACK" switch 16 is switched to its on
position, the previously entered price per unit data and tare
weight data will not be automatically cleared regardless of
the position of the mode selector switch 8. The "P~EPACK"
switch 16 causes the "PREPACK" legend to be backlighted and
overrides the mode selector switch 8 so that re-entry of the
identical price per unit and tare weight after each weighing
; 20 operation will not be necessary.
In addition to the operational modes and ~unctions
already described above, the exemplary embodiment of the
present invention automatically performs several other
operations regardless of the selected mode.
2.S Automatic gross zero compensation or auto zero tracking
compensates the scale for minor off-sets from a zexo weig}lt
; ater correction. Whenever the presently detected and
corrected weight is within 4 raw weight increments of zero,
the correction factor is modified to automatically bring t}le
corrected weight to within one raw weight increment or zero.
~29-
1~213Q79
This automatic yross zero compensation will occur for
variations in zero which occur at a rate of 5 raw weight incre-
ments per second or slower so long as the total compensation,
that is the total correction factor, is within 1 400 raw
weight increments. The exemplary embodiment of the invention
also provides net zero tracking as previously described.
It might be noted by way of further explanation, that
the "Z" key 17 causes the capture range of the automatic
gross zero tracking system to be extended from + 4 raw weight
increments as described above to i 400 raw weight increments.
The exemplary embodiment of the invention is also
provided with a motion detection system which detects weight
changes greater than i 0.5 displayed increment per 1/5 second.
The detection of such platter motion causes the display lamps
behind the legend "LB" or "KG" to be turned off and signals
to the remainder of the circuitry o~ the exemplary embodiment
that a motion condition exists.
; A gross weight exceeding the scale capacity by more than
S scale increments causes the weight display and the total
value or total price display to be blanked.
A total price calculation in excess of the digit nine
in all foux character positions of the total price register
(ox alternatively all five if the five digit total price
mode is selected) will cause the total price display to be
; 25 blanked.
The circuitry of the weighing and computing scale
illustrated in Fig. 1 is shown in detail in the schematic
diagrams of Figs~ 3 through 11. Fig. 2 shows how Figs. 3
through 8 are associated to iIlustrate the complete circuit.
The ramdom access memory assignments are illustrated in
_30_
~.~.2~3~79
. . .
in Fig. 13 and are discussed in connection.with the subsequent
description.of the detailed operation of the exemplary
embodiment.
Fig. 3 illustrates a load cell 40 which is mechanically
linked to the platter 12 and includes four resistive strain
. gage elements which are connected in a Wheatstone bridge
arrangement 70. Typical scale mechanisms suitable for
cooperating in the. embodiment of the invention described
herein are shown in U.S. Patent 3,847,238 granted to D.L. Hall,
et al., on November 12, 1974 and in U.S. Patent No. 3,074,496
granted to L.S. Williams on January 22, 1963.
Electrical power from the regulated power supply 42 is
applied across one pair of opposite terminals of the bridge 70.
The other pair of opposite terminals of the strain gage bridge
70 forms the output of the strain gage bridge and is connected
to the input o the preamplifier 4~. With no strain, the
bridge 70 would be balanced and the output would be zero volts.
In this state each output terminal of the strain gage brid~e
is at the same potential intermediate the potentials of the
terminals of the regulated power source 42. ~Iowever, in
practical application the strain gage bridge 70 will be under
the stress of the platter and other mechanical linkages.
Any weight positioned on the platter 12 will further
deform the resistive element of the bridge 70 causing a
variat.ion .in their resistance and unbalancing of the bridge.
In this manner an output analog voltage is obtained fxom the
strain gage bridge 70 which is related to the wei~ht of the
object on the platter 12 and is applied and ampli~ied by the
. preampliier 44~
; 30 The preamplifier 44 has two differential operational
amplifiers 72 and 74 which are connected to form a differential
. .
- -31~
,
~28~79
. ,
amplifier presenting a very high input impedence to the
output o~ the strain gage bridge 70 so that there is
. substantially no current drain from the bridge 70 while
: still providing a preamplifier which is a true differential
S amplifier rejecting all common mode voltages such as drift
or changes in the bridge exc1tatlon voltage.
The non-inverting input of the OP-AMP 72 is connected
to one of the output terminals of the strain gage bridge 70.
lhe other output terminal of the bridge 70 is connected to
the non-inverting input of OP-AMP 74. The OP-AMP 74 provides
a substantially unity gain amplifier with its output fed across
to the inverting input of the OP-AMP 72. In addition, the
inverting input of the OP-AMP 74 is connected to the wiper
: of a potentiometer 76 which i5 used to shift the output level
ofOP-AMP 72. The potentiometer 76 is manually adjusted to
compensate for small differences in the mechanical and electrical
parameters of production parts and circuits to provide a total
effective analog signal component resulting primarily from
loading of the strain gages 70 when.the platter has no object
placed thereon. This known analog signal component or analog
o~fset is subsequently removed by a subtraction in the digital
data processing circuitry.
Referring now to Fig. 4, the output 30 of the preampli-
fier 44 provides a voltage having an amplitude proportional .
to the sum of the analog offset and the signal change resulting
: from an object being placed on the platter 12 and is applied
to an active filter circuit 46. This active filter circuit 46
is a low pass filter designed to filter out scale platform or
platter vibration. The output circuit of the active filter 46
includes a span adjustment potentiometer 92 which is connected
as a simple voltage divider for adjustably selecting the
; .
-32-
11Z~3~79
desired proportion of the filtered analog weight voltage to
he applied through the switching,circuit 50 to .the integrator
52 at xhe appropriate time. This potentiometer adjusts the
, analog circuit gain to a value suitable for the various
scale capacities.
The switching circuit 50 under the control of the micro-
computer 54 (see Fig. 1) may be used to selectively gate one
of four possible inputs through four field effect transistors
to the input 98 of the integrator 51. The four alternatively
1~ selectable inputs are: ~lj the analog weight signal from the
' wipex of the potentiometer 92 which is applied through a
resistor 85 and FET 94; (2) a reference DC source applied
through resistor 87 and FET 95; (3) a second reference DC
source which is applied through resistor 91 and FET 96; and
~15 ~4) a reset signal applied ~hrough resistor 93 and FET-97.
' In the exemplary embodiment, resistors 85, 87, and 91 are all 500K
ohms.
Th~ gates o~,~oux FETS 94, ~5, 96, and 97 a're cannected
to four discrete inpu~/output terminals, 1, 42, 41, and 40 of
~20 the CP~ as illustrated in Figs. 5 and 9 so that the CPU can
control these gates.
As previously described in the exemplary embodimentj the
ampl;.tude of the irst re~erence DC souxce, which is integrated
during the second integration interval T2 of the triple slope
; 25 ~/D conversion, is 32 times greater than the second reference
DC source which is integrated during the third inte~ration
~ime interval T3,
This is accomplished in the e~emplary embodiment by
referencing the' input to the integrator 51 to a particu.lar
; 30 non-zero potential rather than to ground, In particular,
series resistors R and R/32 shown in Fig, 4 form a voltage diviaer
-33-
,
~128~79
between the power supply potential of -15 volts and ground.
Resistor R is 32K ohms and resistor R/32 is lK ohm. There-
fore, the reference potential which is always applied to the
noninverting input of OP-AMP 99 of the integrator 51 has an
amplitude equal to 1/33 of the power supply potential and
has the same polarity. In the exemplary embodiment this
reference potential fixed is at -33 volts relative to ground
potential by resistors R and ~/32.
- During the first integrating interval Tl of the triple
slope conversion, a positive analog weight signal i~ normally
applied to the integrator 51. Then, during the second interval
T2, the -15 volt power supply provides the first reference
DC source having a polarity opposite to the polar ty of the
analog weight signal and having an amplitude of -~ x 15 volts
relative to the reference potential at the noninverting input
;~ of the OP-AMP 99.
During the third integrating interval ~3, FET 96 is
switched on to apply a 4econd reference DC source to the
integrator which is derived through resistor 91 from ground
potential. Since.ground potential is positive with respect
to the reference voltage at the noninverting input of OP-~MP
99 and has an amplitude of 15/33 volts, the connection Qf the
integrator input 98 to ground through resistor 91 effectively
. provides a second reference DC source during interval T3 which
is both opposite in polarity to and 1/32 the amplitude o~ the
reference DC source applied during interval T2
Except for this manner of referencing the integrator 51,
; it is a conventional integrator circ~it including an integrating
capacitor 100.
The output of the integrator 51 is applied to the amplifier
52 and through it to the threshold detector 53. The amplifler
-34-
` ` ` l~Z8~79
52 comprises an OP-PMP 104 and is provided to amplify the
output of the inteyrator 51 to make the slope of the output
of integrator 51 steeper so that the time of its crossover
with its initial level can be more accurately determined.
' The threshold detector circuit 53 includes an OP-AMP 106.
It is simply a high gain amplifier which is driven from one
saturation to the other when its input voltage crosses zero.
Figs. 5-8 show the details of the input and output devices
and circuitry and the digital data processing and control
circuitry.
In accordance with the present invention the microcomputer
54 of Fig. 1 may be any of several suitable types of commer-
cially available microcomputers or other similar control
; circuitry including wired components of types well known in
lS the computer and electronics arts.
In the exemplary embodiment of the`invention, the micro-
' computer $4 is essentially a PPS-4 parallel processing, micro-
i~ computer system developed,by and using devices manufactured by
Rockwell International Corpor~tion. ~he microcomputer 54 is
comprised essentially o~'a central processing unit or CPU
which in the exemplary embodiment described herein is a Rockwell
PPS-4/2 unit and a memory unit having both read only memory or
~OM for storage of program and fixed constants and al~o random
~ access memory or R~M for storage of data for use in processing.
2~ The preferred memory used with the exemplary embodiment of the
invention i5 a Rockwell P/N A17XX device.
In addition to its connection to the OUtpllt o~ the
Threshold detector 53, the microcomputer 54 is also directly ~,
connec~ed to the mode selector switches 22, the printer 28,
the "Z" key 17, and the "PREPACK ~N/OFF" switch 16. Tne micro-
-35-
` ~L21~79
.
computer 54-is also connected to the frorlt and back indicator
lamp displays 26 through suitable interfacing latching, decoding
and driving circuitry 56.
Finally, the microcomputer 54 is also connected to a
; general purpose keyboard and display interfacing device 58
îor interfacing the keyboard 20 and the front and back digit
displays 24 with the microcomputer 54. A general purpcse
keyboard and display interface or GPKD interface 58 is employed
' which is the exemplary embodiment described herein comprises a
device manufactured by Rockwell International Corpora-tion '
and designated P/N 10788. This unit, under the control of the
microcomputer 54,'receives and temporarily holds data keyed in
on the keyboard 20 fox subsequent transmission to the micro-
computer 54. The GPKD interface unit 58 also receives data
from the microcomputer 54 which it applied through decoderjdrive
lo~ic 60 the front and back digit displays 24 under control o~
the mi'crocomputer 54. The Rockwell PPS 4 microcomputer system
uses fo~r bit data words, eight bit instruction words and in
' the exemplary embodiment of the present invention twelve bit
address words all of which are parallel transferred within the
' system.
Referring now to Figs. 5-8, at the top of Fig. 5 is shown
' the bus system 201 interconnecting the CPU 210 of Fig. 5, the
' ~ memory 310 o'f Fig. 6 and the GPKD 410 of Fig. 7. The bus
system 201 inc'l'udes a twelve line address bus 203 which is ~
connected ~only to the memor~ 310 for addressing the RAM and
ROM memory. The bus 201 further includes an eight line
instruction/data bus 205'~hich transfers, at different times,
either eight bit instruction words or two four bit data words
bidirectionally. The bus 201 further includes two clock lines,
-36-
; ~ llZB~79
CLKA and CL~B, a write command ~ine and an input/output enable
line W/I0 for use during one clock phase time for instructing
the RAM memory to write and for use during another clock phase
time for disabling the RAM memory and enabling the input/output
devices for the performance of an input~output instruction.
The bus system also includes a "synchronized power on" CPU
output line labelled SPO for use in initializing other devices
in the circuit.
The CPU 210, which is shown as a single block in Fig. 5,
is illustrated in greater detail in Fig. 9. Fig. 9 is a block
diagram available with technical'information from Rockwell
International, Inc.
The CPU 210 as shown in Fig. 9 has an accumulator 810
j which is the basic work register of the CPU. It also has an
,15 arithmetic logic unit 811 with a carry register 812 and an X
~j register 813 all connected to the accumulator 810. The CPU
, .
' 210 further has a data address register 814 and a proyram
address register 815 which may be selectively interconnected
` with the address bus 203 output pins 27 through 38 through the
;~20 multiplex driver'c'ircuits 816. The CPU 210 has two program
address save registers 817 and 818 to provide two lev~ls o
~ubroutine stacking. 'rhe Rockwell CPU PPS 4/2 is provided with
internal'clock 819 when a suitable crystal 820 is connected to
its pills 18 and 19. The instruction/data bus 205 is connected
to pins 6 through 13 which in turn are'connected to multiplex
receivers 821 and 822 and the multiplex driver 823. Incoming
instructions are decoded by the CPU in its instruction d~code
logic 824 and two separate flip-flops 825 and 826 are provided
for program use.
' 30 In addition to the bus input~output capabilities, ~he
CPU 210 is provided with 12 discrete input/output pins, fou~
'
-37-
` ` 1128~79
from each of the three registers 827, 828, and 829. These are
connected as illustrated to pins 1-5, 23-26, and 40-42.
Referring back to Fig. 5, the discrete input/output
register 828 of the CPU a~ shown in Fiy. 9 is connected as
shown in ~ig. 5 to the four control lines labelled Tl, T2, T3,
and "Reset" which extend to the switching circuit 50 in order
to control the integrations of the triple slope A~D conversion.
The crystal 820, shown in Fig. 5, controls the frequency of
~ts internal clock generator which is preferably 0.20 MHZ~
A time delay circuit 222 Fig. 5 is provided for delaying
the CPU 210 and in particular its prograrn counter (which must
be returned to 0000) after power is first applied or after a
brief power interruption or momentary power failure.
The "PREPACK ON/OFF" switch 16, the "Z" pushbutton 17
and the "xlO EXPAND" mode selector switch 5 are connected to
the discrete input 827 (see Fig. 9) at pins 2, 3, 4, and 5 of
the CPU 210 as shown in Fig. 5.
The front and back indicator lamps 26 are connected
through lamp drivers 242 to addxessable latches 240. The
addressable latches 240 respond to the incomin~ data and apply
the data to the appropriate indicator lamps 26. More
specifically, the latches are addressed from output pins 23,
2~, and 25 of the CPU 210. With three such address lines,
any of the seven indicator lamps 26 may be selected or
addressed. The addressable latches are enabled by the output
o~ terminal 26 of the CPU 210 and enabled latch is then
controlled by data transmitted over line 241 from the memory
input/output port terminals 41 shown in Figs. 6 and 10.
As illustrated in Fig. 5, output terminals 23-26 of
~0 the CPU 210 also provide four bit data to the printer.
-38
.
~- 1128~79
. .
Fig. 6 illustrates, in block form, the memory 310 which
is illustrated in greater detail in Fig. 10. Referring to
` Fig. 10, the memory includes both RAM memory 911 and ROM
memory 912. These are connected to the instruction/data or
I/D bus 205 through a multiplexer 913 which is connected
to pins 10-12 and 15-19. An address decoder 910 is connected
to the address bus 203 through pins 14, 20, 21, 23, 24, and
28-34; The memory 310 further has sixteen discrete input/
output ports connected at pins 1-8 and 35-42 through receiver
buffers 917 to the multiplexer 913. . :
The read-only memory 912 has a storage capacity of 2k
eight bit words, any of which may be addressed over the
address bus 203 and its stored eight bit word returned to
the CPU over the instruction/data bus 205.
. The random access memory 911 has 128 four bit storage
registers for storing four bit words. Dependent upon the
clock phase and the state of the w/10 line connected from
texminal 14 of the CPU to terminal 13 of the memory, the
addressed memory register will read its four bit contents out
onto the instruction/data.bus 205 and will write, if so
instructed, a new four bit work from the.CPU into ~e addressed
register through the multiplexer 913
Returning to Fig. 6, the output 102 from the threshold
detector 53 illustrated in Fig. 4 is applied to one of the
2~ discrete input/output ports at pin 42 of the memory 310.
Eight othex discrete input/output ports-connected to
pins 1-8 of the memory 310 axe connected to the twelve manual
mode selection switches 22 illustrated in Fig. 6~ Half of
the twelve switches, labelled SW-l, are connected between
Pin 2 and through diodes to pins 3-8 of the memory 310. The
--39-- ,
. .
.
- 11213`~79
.
other half of the twelve switches, labelled SW-2, are
connected between pin l and pins 3-8. Each of the individual
switches of both switches SW-l and SW-2 are individually
and independently actuable and each is labelled with a number
which corresponds to the function liste~ in block 22 on
Fig. 1. Consequently, the microcomputer 54 can interrogate
the condition of switches SW-l by strobing pin 2 and examining
the data of lines 3-8 and can interrogate switches S~-2 by
strobing pin 1 and examining the data of pins 3-8. It is to
be wlderstood that any particular one of these switches may be
assigned any particular operational mode function.
Printex control signals are applied to the printer from
the five discrete input/output memory ports 35-39 of the
memory 310 illustrated in Fig. 6. The "print complete" signal
when received from the printer is applied to the discrete
;~ input/output port ~0 of the memory 310.
Fig. 7 includes, in block diagram form, the general purpose
keyboard and display interface 410. Figs. 7 and 8 illustrate
the keyboard 20 and display drivers connected thereto.
The GPICD interface 410 used in the exemplary embodiment
is a device manufactured by Rockwell International Corporation
`and given their type number P/N 10788. It is interconnected
with the memory 310 and the CPU 210 through the data bus 205
as ~ell as the clock A, clock B, s~nchronized power on and
w.rite/input-output lines of the bus 201.
A block diagram of the circuit of the GPKD interface 410
is illustrated in Fig. 11. Referring to Fig. 11, chip select
decode circuit 1012 compares the chip address data applied
by the CPU 210 to pins 2, 4, and 42 of the GPKD over the
instruction/data bus tv the data on the chip select straps ~t
40-
112~ 79
r`.ns 1 3 and ~1. I the st:~apped address is id~ntical to the
~ dress on the in~t:ructi.on/data bus if tlle instruction/data
line connccted to pin 6 is truc and if the writc/i.nput-output
mode has been sel~cted by the CPU so that the CPU h~s tlAued
~he W/IQ input pin 5 then the G~I{D is sel~cted to execute
the comma~d.
The co~-nand is applied to the GPI~D from the CPU 210 ovc~
that half of the instxuction/data bus which is connected
to p.ins 3~ throu~h 39. The co~mand is decodcd by the command
af~codinc~ :Lo~ic circuitry 1014. A bit time counter ].016 is
pxovided to dividc the c].ock frequency from the PPS clock
and capply ;.ts output to a sc~n counter 101c8. The sc~n counter
1018 provi.des timing si~nals for the display re~ister control
d:i.spla.y bank sel.cct 1026 return samplin~ 102~, key bufcr
xec.~ister 1032, and control 1030 and strobe select circuit
.~24.
Tlle GI)lCD oE Fig. 11 includes two display rcgisters
and B whicll storc display dat~. Th~s~ display re~isters
storc clata ~rom the instruction~data bus and upon co~mand,
output thc data to the:;r associr-lted displays.
Tlle st.lAobe ;.~-~lect c:i.rcuil: 102~, wi.h its ~i.ght outE)ul:
p.ins, 27 I:hroucJh 3~L, s~u~ntial.l~ outputs ciyht strobe si.cJna].s
to its eight: output pins. Thesc outputs may bc us~d to strobe
an 8 x 8 ~yboard mat:rl~ or for multiplexing display characters~
Tlle ret:urn sarn~ling circuit 1028 receives data from the
stro~ecd ~;e~oclrcl indic.lt.i.ng the states of the key matrix
return li.nes i.rom the }ey~o~rd. ~n~en a ~ey clcsure is
detcct:ed at tne returl-l s~mp:l.ing circuit 1028 the key ~ufEer
.register cont.rol circult 1030 loads the Xey code fox that
ke~ into the buffer re~iste.r 1~32. Subsequent key clcsures
~Jhich are detcc~ed may also be stored in the ~ey ~uffer registers
.
llZ8~79
1032 until tlley are called for by and transferred to the
CPU on a first i~, first out basis.
~eturning to Fig. 7, the eight strobe select output
pins 27 through 34 are applied four to the display driver
513 of Fig. 8 and four to the display driver 514 of Fig. 8
The outputs of the display drivers 513 and 514 are applied
to the anode d-ive terminals.of the front,a,nd back displays.
Referring to Fig. 7 ! since various decimal point locations
are required b~ the various countries,, a switch labelled
SW-3 consisting of six individually,operated single pole,
single throw switches is associated with transistors Q3 and
Q4 selectively enabling those digit positions in which decimal~
may be displayed.
Four of,the s~robe select lines at pins 27 through 30
. 15 of the GPK~ ~10 are additionally applied to the four input
; strobe lines of the keyboard matrix of the keyboard 20., The
ke~boarcd return lines are connected to pins :l9'through 21,
23 ancl 2~ o the return sampling inputs of the.GPKD ~10
These permit interrogation of the ke~board for key depressions~
; 20 . opERArr I ON o~ TIIE SYSTEM
The operation of the system can be most conveniently
described in conjunction with Figures l~A through 14Z of the
draw:ings (Fic3ure numbers l~Q,and l~U are not uscd for clarity)~
The flow diagrams of Figures l~A through 14Z graphically
~5 - 'describe the operation o~ the scale system,. ~ typical
operating sec1uence represented by the program list'ing included
'as an appendix in co-pending Canadian application 308,~02,
relating to a Rockwell PPS~.4/2 microcomputer. Hc~ever, it should be
appreciated that the operating sequenc~ of the system utilizing this
operating sequence may be implernentcd on otller types of
-~2-
`~.f
- 112~3~79
commercially available compu-lers in accordance with the
principlcs described herein.
The presen-l- inven-lion, as incorpora-lecl in -i-he
exemF)lary embodiment described herein is arranged to
coopera-~e with many features and opera1-ions which are
described and claimed in U.S. patent r~umbers 3,984,667 to
Loshbough, U.S. patent No. 3~869,005 lo Williams, Jr., and
U.S. patent No. 3,861,479 to Pryor an(l Canadian paten-t
application Serial No. 286,550 of Donivan L. Hall ancl
Edward G. Pryor entitled "Digi-i-al Scale With Antifraucd
Features". In order to more clearly set for~h the prccise
invantTon for which -i-his pa--eni is solicited, in such a
manner as -lo distlnguish it from o~her inventions and frorn
wha-t is old, those operai-ions which are disclosed in -lhc
above references will only be generally described, wi-ih the
prirnary emphasis being given those opcrcltions forming a part
! of -Ihe inslani- invention.
Many of -Ihe opcraiions of i-he scalc sys-~em util-
izing -ille operatlng sequence are performed only partially by
singlo pass throu~rl the operailng sequcnce ~hereinafi-cr
referred io as an opcraling sequence cycle), so tl)al a
pluralil-y of F)asses or cyclos lhrough ~I)e opcrai-ing
sequence may be requircd Tn ordcr io complei-c a particular
opcralion. Such operations arc clearly disclosed in the
~bove reforencos and will be referred to in Ihe instanl
clisclosure only where nocessary I-o clcarly so-i- forl-h i-he
inslanl- invon~liorl. lhe dctails o-f the oporations are
c o m p ! el-ely.di<icl 0 5 0 cl i n the progrcun listing found in the
appendix of Canadian application 308,202 c~nd in the flcw diagrams
Figs. 14A throu~h 14Z.
- ~.3 -
J~/
~2~3~79
The flow diagrams of figuxes 14A through 14~ disclose
in graphical form an exemplary operating sequence of the scale
system, including the operations required for implementing the
analog-to-digital conversion and the net zero tracking descrlbed
herein. The flow diagrams consist of ~ series of geometrical
' shapes, each of ~ihïch corresponds to a particular type of
operation. Each rectangular block represents the per~ormance
of a function which is generally indicated by the notation
`:~ound ~ithin the rectangular block. Each diamond shaped
geometrical figure represents a decision making operation where
'one ~f two alternatives is determined. The hexagons represent
that a subroutine is performed at that particular point in the
operating sequence, with~the subroutine being performed indicated
by the notation within the hexagon. Thb oval-shaped geometrical
1~ ' figures'represent a branch back operation and are used in
conjunction with a subroutine'to.indicate''that the operating
sequenc'e continues at that point in the main operating sequence
. .
.whexe the subroutine was en'tered. A rhomboid geometrical
figure repre~sents either an input or an output operation.
.The numbers placed in circles to the top and lePt of the
geometrical fi~ux~s represent inp-t locations to those particular
operations. The numbers in the circles to the right ~nd below
the blocks in the 1OW diag.rams represent an output connected
to a different location in the flow diagrams indicating a
~5 transfe~' in the operating sequence. The mneumonic designations
~ound in parenthesis adjacent to the circles containing numbers,
indicate labels which have been given to a ~articular group of
; 'operations. rrhese mneumonics may ~e.utilize~ in referring
back to the detailed operating seq~ence dis'closed in the
appendi.~ found in application Serial Nu~ber 308,202 by referring to the
sy~bol table found àt the end of the a~orementi~ned appendlx. ~he's~bol
~ble ~oundi.n the apE~endix lists,
-~4-
79
.. .. .
in alphabetical order, the mne~unonic labels and the corres-
ponding location in the detailed program listing of the operating
sequence where the particular operations represented by the
mneumonic label may be found. Also a table is included showing
the operations represented by the mne~nonic labels.
In order to accomplish the operations illustrated in
Figures 14A - 14Z, data is assigned to and stored in various
registers or memory cells in the random access memory or ~1
911 as illustrated in Fig. 13. Therefore, it is useful to deine
l,0 and explain the various flags, counters, timers and data
registers which are used in the exemplary embodiment of the
invention and which are re~erred to in the flow chart diagrams
of Figures 14A - l~Z.
' The memory unit 310 which is shown in ~ig. 6 and illustrated
.5 in more detail in ~ig. 10, includes a random access memory or
R~ with'a capacity of 128 four-bit wo,rds and arranged as
shown in Fig. 13. Each of the 128 four-bit words may contain
any one o sixteen states. These states can represent numerical
values of data or a st~atus or condition.
0 In Fi~. 13, the register addresses are referred to by the
hex~deci~al e~uivalents o their kinary address. The two most
significant hexadecimal digits of the address within th,e R~M
define a part.icular column or grouping of four bit words ~nd
t~le least signiicant hexadecimal digit defines a row or
. ' r~ particular four bit word ~ithin the R~M. The hexadecimal
address clesignations are also used as reerence numerals below.
; ~ tare done 1ag at address 002 is set to its binary eight
state ater a tare operation has been completea by the entry
OI tare weight data into the appropriate storage registers
,~ and otherwise is reset or cleared to a "zero" state when such
,
-~5-
` ~ ~12~3~79
.
a tare has not been completed.
A digit timer is provided at register 004. The digit
timer is set to its binary "eleven" state upon the depression
of a digit key on the keyboard. Thereafter it begins a timing
cycle by decrementing one count each pass through an Qperating
sequence cycle. The depression of any other digit key before
the digit timer counts to zero will again set the digit timer to
binary "eleven" state to reinitiate the counting cycle. If the
digit timer counts down its"zero" state before all price
digits are entered or the tare key is depressed, all previously
entered keyboard digits will be cleared upon entry of any new
digit. This feature requires that all digits be entered within
a few seconds of each other and consequently avoids the
retention by the apparatu- of accidently entered data or of data
entered a considerable time earlier and forgotten by the
operator.
A manual tare flag having two states is provided at
register 003. Whenever the "T" key is pressed, there is no
motion of the platt~r and the digit timer of register 004
is at its "zero" state ~i.e., is not running), the manual
tare flag is set to its "eight" state. It is reset or cleared
to its "zero" state ater its condition has been sensed in
subsequent operations.
The addresses of registers 005 through OOF are labelled
~'S as a result register and are used as a scratch pad.
~ ilter Cotlnter is provided at address 010 and is used to
provide four states, "zero" through "three". Whenever, during
the sequence of operations, no difference is found to exist
between a most recently generated, fully processed weight and
the weight currently being displayed, the ~ilter counter is
-~6- -
~ ~ ~128~79
reset or cleared to its "zero" state. However, each time a
difference is found to exist between the most recently generated
fully processed weight and the weight being displayed, the fil~-er
counter counts up one count. If such a difference is.found
three times in succession, the filter counter counts one count
at a time, to its "three" state to signal that the displayed
weight should be updated with the most recently generated fully
processed weight. This avoids a display blink from an
: unnecessary updating of the displayed weight with weight data
which is identical to that which is currently being displayed.
A zero lamp flag is provided at address 011 and is used to
provide three states "zero" through "two". Whenever a weight
is detected which is not within a small range of the previously
established scale zero, which range is different for different
1~ scale capacities, the zero lamp flag is set to its "two" state
for purposes of causing the zero lamp to be turned off to
indicate that the scale .is not zeroed. However, each time a
weight within this range is detected, the zero lamp flag is
decremented. Consequently, if the scale is found to be within
this xange for two such detections in succession, the zero
lamp flag gets decremented to its "zero" state so that the
zero lamp is turned on to indicate that the scale is zeroed.
A net flag is provided at register 012 and is set to its
"eight" state when the weighing scale is in its net mode of
2.'i operation, that is, when a positive weight is stored in the
tare memoxy register. Otherwise, the net flag is in its clear
- or reset state of "zero".
A ~actor flag is provided in xegister 013 which is reset
or cleared to its "zero" state when the~e is no price factor,
set to its "two" state when pricing is per 1/2 uni.t of weiyht
,. ,
: 47-
79
and is set to its "four" state when pri~ing is per 1/4 unit
of weight.
A verify test flag is provided in register 018. This flag
is set to its "eight" state in response to depression of the
"clear" key to signify that a verification test is in progress.
The verify test flag is reset or cleared to its "zero" state
when t~e sequence of operations pass through the reset operation
III beginning on Fig. 14A.
Registers OlA through OlF provide six, binary coded
1~ decimal digits of temporary scratch pad data storage for use
in carrying out the sequences of operations of the exernplary
embodiment of the invention. The sign of that six digit
number is stored as a fifteen or zero in register 01~.
Registers 020 through 0~6 store, as an "eight" or
"zero", on the "on" or "off" state of the indicator lam~s
labelled at those addresses in Fig. 13.
The presence or absence of a print command is stored
as an "eight" or "zero" at register 027.
Registers 02A through 02F store the si~ binary coded
decimal digits which represen~ a detected weight while register
029 stores the sign of that weight.
In order to require that the "Z" be depressed for a
sufficient length o time before such depression is accepted
and to thereby prevent accidental erroneous or fraudulent
zeroing o the weighing scale, a zero key timer is provided
at register 030. ~he zero key timer has even states "zero"
through "fourteen". An initial depression o the "Z" key
causes the zero key timer to switch to its "two" state.
Thereafter, on each pass through the operating sequence cycles,
the zero key timer is incremented to its next highe-r even
~'
-48-
" ~128~79
state so long as the "Z" key remains depressed. If the "Z"
key is depressed sufficiently long that the zero key timer
counts through all its even states and returns to "zero",
~ the depression of the "Z" key is then accepted, the scale is
zeroed and the zero done flag at register 031 is set to its
`'fifteen" state to indicate that the scale has been zeroed.
The zero done flag is reset or cleared to its n zero" state
in the initial, main progra~ power-up operation I beginning
on'Fig. 14A.
An auto cleax flag is provided at register 033 to help
'in the automatic clearing of a previously entered tare weight
and pr'ice each time a weighing operation is completed. The
' auto clear flag is a seven state counter which is reset to
'` its "zero'` state whenever the detected weight is greater than ' a weight corresponding to one hundred raw weight increments.
! Whenever the scale weight exceeds this 100 increment band, the
auto clear flag begins counting towards its '`six`' state. This
auto'clear flag counter is incremented each pass through the
sequence of operations. If the detected weight falls within
the 100 increment band before the auto clea'r flag counter reaches
its ''six'`' state, the auto clear counter is reset to its "zero"
state and the tare data is not automatically cleared. However,
if the~scale weight is above the 100 increment band long enough
' for the auto clear flag to reach its "six" state, it will '
remain'in its six state to enable the auto clear function. After
the scale weight returns to within ~he 100 increment band, the
tare weight and price will then be cleared~
Registers 03~ and 035 are provided to store the least
: significant binary coded decimal digits of a first previously
detected'and a second previously detected weight.' These are
utilized as descriked below in the filtering operation of
1:~28'~!79
the preferred e~bodiment of the invention.
Registers 039 through 03F are used for the sign and
the six binary coded decimal digits of a partially processed
weight which represents a previously detected weight.
Registers 0~0 through 045, 050, 051, and 053 through 055
are two-state registers which store each mode selector switch
status as an "eigh,t" state or a "zero" state. Registers 046
and 047 store data which represent a keyboard key which has
been depressed and detected. Register 048 stores in its four
bits the status of the switches or keys labelled in those
positions in Fig. 13.
Registers 049 through 04F form the auto zero register
in which the zero correction factor is stored.
Registers 050 through 055 are used to store data as
indicated.
A recompute ~lag is provided at r,egister 057. It is set
to a non~zero value whenever there is a change in a price digit
ox output weight in order to signify, during the next pass
through an operating sequence cycle, that a new total price
should be computed. However, i~ no such change is detected,
the recompute flag r~main~ in its "zero" state so that no
new total price is computed. The recompute 1ag is cleared
ir~mediately prior to the compute total pric~ operation XX.
A verify mode flag is provided at register 058. This
flag has two states and is switched from its "zero" state to
its 15 state upon the first depression of the CLE~R key and
is returned to its "zero" state upon depression of any other
key.
Registers 059 through 05F store the tare weight.
Registers 060 through O~E store the total price, price and
ou-tput weight as indicated. Registers 070 through 07F are
~50--
-
.Z8~7g
~s a ~i~orli area .~n(l tempor;lry scratch pad clurin~ the display
and othel: routines.
'.I`I~e~ vario~ls nle.ms and appaIatus for peric)r~lling the
E(mction.c; and improvements in accordance ~ith the e~emplary
embodimellt of the invention comprise the scale mechanism, keys,
switches, 1ags, registers, counters, timers, and storay,e
sl~aces together wlth program sequences or routines and routine
loops i.n co7nbination WitJI the computer, and the output or
displcly appctratus and the control thereof.
Thus the means :Eo~ controlling tlle time the integrator
means is connected to the scale means comprises gate 9~ and
the control thercof including pro~ram sequences of blocks
~ .17, 14~20, or 14A22 and the pro~ram loops or sequences o
Fjc~. 14W i.n coml~.ination with the computer.
Thc ~e~ns for reading the weight includes tlle 10w
diagrarns begi.nni~ , at: B~ of Fig. 14l3 of the drawin~.
The structure o:E the timin,., ~nd counting c~rr.~ngement
oper..lti.ve dtlring t.l-e T2 .-lncl T3 intervals comprist.~. counter l,
counter ~, and counter 3 together wi~h the program sequcnces
1~1CI loops ~e.~illT~ g at B9 o~ Fi~. 14B ~hich sequellc~ and
; l.oops co~rlprisie tl~e ~.t.ructure o~ tht correspondinc~ seetions
of the R0~l s~orn~,e. These~ secluc?llc.eC; and loop~ ~o~cther with
the colnputt!l clt~termille ~he T2 .ltl~ T3 times.
The pro~Lam sequelltt-~s employed to derive the raw wei~ht
~rom the T2 an~ T3 t:imes are shown in the draw:i.nc~ beg~inninO
~iith block 14r~22 o.E Fi~. 14~ arld extend throu~h block 14Cll
C~ l C .
The oreration of the exemplary em~odiment of the
invellt.ion is now described wit.h reEerence to tlle Elow chart
clia~,ral)ls o.f Fi~s. l~ ].~Z. The :Eirst two cli"its of the
l~Z8Q79
alphanumeric reference numerals for the individual steps of
the operation are the Figure numbers on which the particular
steps are illustrated. The latter alphanumeric digits refer
to the particular step in th~tFigure. The labels which
are shown in parentheses on the drawin~s are the labels
used in the pro~ram and therefore provide cross references
to the appended program listing in application 308,202.
Main Program Power-up
The power-up sequence is an initialization sequence
which is performed when power is first applied to the central
processor or there is an interruption of power to the
central processor.
During step 14A2 various registers within the
computer are cleared to an initial state to provide a known
starting state for the operating sequence.
A~te~ the main pro~ram power-up se~uence the -
operating sequence then proceeds to the ~lQ CLEAR sequence
beginning at step 14El which causes a clearing operation to
take place with respect to the tare and auto-zero~ The
operating sequence then proceeds to the output sequence
beginning at 14Ml~.
The main pro~ram then advances through the remaining
sequences shown in Fig. 14M and then transfers to the sequences
of Figs. 14N and 140 and through the yarious sequences of
Fig. 14P through 14P15. These output and printer sequences
are analogous to the output sequences such as described in
the above identified patents and applications~ The main
program then advances through the various keyboard sequences
or
~ 51A -
cg/
.~
l~Z8~79
:
routines beginning at 14P16. If no key i5 operatecl the
'procJram transfers to T19 of Fig. 14T and then to ~g as,suming no
verifying operation.
Upon transfer to block 14A8 via transfer A8, the various
control and mode switches are scanned and the various registers
in the RAM 911 conditioned or set in accordance with the
condition of the various control and mode switches. These
various operations are designated in blocks 14A8 through
14Al],. These operatio,ns and the operations relating to the
scanni.ng and response to the keyboard digit keys are analo~ous
to the corresponding operations described in the above patents
and applications,
In the beginning under the assumed conditions, the digit
timer was previously or already zero so control transfers
froin block 14All vi~ transfer A15 to block 14A15.
Beginning with block 14A15, the xead weic~ht sequence
~ of operations VI is performed in which the analog to digital
; conversion in accordance with the present invention is
accomplished~ '
~t the beginning o the read weight se~uence of operations,
: ~ find scale capacity sub.routine is pèrformed. This subrouti.ne
' is illustrated on Fig. l~V. It performs the interrocJation
:' o R~M r~gisters 0~3 and 044 to determine what scale capacity
; is selected and returns to the main proyr,am data which is
dependent upon which capclcity is selectecl.
.' ~eferring to FicJ. l4V, at step l~Vl, the arithmetic scratch
pad reg:i.ster OlA-.OlF i.5 c.l.eared and Ela~ 1, i.e~., flip flop
:, 825 of the CPU 210 is s~t to make an .initial assumption that
the 15 kilogram scale is not selected. Similarl~, the carry
register 812 of the CPU 210 is set for an initial,assumption
that the 6 kilocJram scale is not selected.
~ -52-
112~3~79
Then, in step 14V2, the 30 lb. enable RAM register
043 is examined to determine whether the 30 lb. scale i5
selected. If it is, operation jumps to step 14V6. However,
if it is not, the carry is then reset in step 14V3 to assume
that the 6 kilogram scale is selected~ Then, in step 14V4
the 6 kilogram enable register RAM 044 is examined to determine
whether the 6 kilogram scale is selected. If it is, operation
j~mps to step V6. However, if it is not, the carry register
is set and flag 1 is reset to note that the 15 kilogram scale
is selected.
Then, at step 14V~, the flag 1 (FF825) and carry register
812 are used to load into the X regist r 813 of the CPU 210
a 5 if the 15 kilogram scale was selected, a 3 if the 30 lb.
scale is selected and a 6 if the 6 kilogram scale is selected.
In step 14V7 there is loaded into the accumulator 810 a 5 if
! the 15 kilogram scale was selected, a 1 if the 30 lb. scale
is selected, and a 2 if the 6 kilogram scale is selected.
Then, in step 14V8 the address DDlA of the arithmetic scratch
pad register ARI is loaded in the BL section o~ the address
register 814 and operation returns to the next order iII the
~equence of operations at which the ~ind scale capacity
sequence of operations was called.
Referring n~w again to Fig. 1~.~, data returned in this
manner is then used in steps 14A16 through 14A?2 to set up
a timing sequence for providing the time interval during which
the analog weight signal is integrated as part of the analocJ
to digital conversion.
In the exemplary embodiment of the present invention three,
four bit, digital tlmers are employed; a "Long Timer" in
30 ~M register OOA, a '~Mid Timer" in ~A~I register 009, and a
. . ,
-S3-
.
" l~Z13~79
;'Short Tl~er" in tht?. accumulc-ltor tnd initicLliY.ed t-o the
.~l.ue, sllo~ln i.n .steps 14A17, l~A20, or ~IA22. Thcse ti.mers
,.re then ~)rocc~scd accord;nc~, to t-le subsequcntly descri~)ed
tirl~itl ,ul~routi.lles i.n order to provide tl~e desircd integrating
~ime i.nterval Tl i1].ustrated in 1 i~J. '12.
~ ,1t:hougll ~ sin~le timer re~ister havin~ sufficient bit
capacity cou1(1 be used to ~rovide the clesire~d tim~ interval~
it is adv~nta~,eous to use the short, mid and lon~ tiTners
describe(l abovc.
~s ~tn example, i~ the scale ~las been set or conditioned
to o~eratt~ as 6 ki.].o&r~m scale, the lonc~, timer OOA, is set
to a 15 s-l-.ate, t.l-le mid-tirller 009, is set to its 3 state,
; and t he short l-i.t;lt'r in t-.he accu~ulator is set to a 9 state.
~;Etcl 1O.L~ lf~ tllis iniLial t1min~ data into the lonc",
mi.d ~lnd S~lOI^t Limcr~" tht~ CPU 2L0 at step l~Bl switches the
t.ransi.stor 94 (J.~`i.g. ~l) of th~ s~itchin~, circui~ 50 to iT.S
cond~lctI.olt st~.a~c ;n ortler to ~pply the an~1o~ wei~T,ht si~,nL~l
to tlle inl:c&rator clrcu;.t 51 alld b~git- the int~?gration.
The delay s~lbrout-i.ne at ~t-c~ B2 then uses the previously
].oad~ '.ong~ Illid .~lld short ti.mcrs to p~ovide t:he desirecl
t.1T~Ie-cle].cly s~ T.]. 'l'lli~ d~lny stl~ro~ltine colnprisin~ a
count:it~; arL(l ~i.m~ Lo~r.lm lool) oE i.nst:~-uctions is 111ustrated
ill dctaiL on Fi.~ lJ.
R~:C`l^ri.ll~ IlOW to ~`i.g. I.~ J, tlpC)lt entry into the de1~y
subrout:irle ,:)t. ~.;t:eE~ tlte our b;.t colltentC.; of the mid-
timer i.s 1o~ldc?d to r.c~:r~:is~er X~,13 o:F t:lle C~'U. The ~our bit
contelit; o.E the ~ c~rt- ti.mcr ;~. t-~el- l.o.~led a~ ep 14.12 ;.~lto
t:hc l1ceum~ Lt-or and dec.retnel:ltc~d. The -L:inler is checked at
step l~W3 to de~:c-rtnirLe whethel- itt h~d l~r~?vio~1sly ~ecn 0. If
it' W~ S not 0, then at: step L4~J~ a 105 microsecond delLay is
ill~d l)y C~Si.!lg ~.he CPU 21.0 to pelEorm some instructions
caus:i.nt~t:l-e CPIJ to count cycles for t-he puLpose cf gainin~r
` `` l~Z~3~79
the delay. Thereafter, the sequence of operation loops
back again to step 14w2. Operation continues to loop
through these 14W2 through 14W4 steps until the short timer
is decremented to zero. Thus, it will loop through these
5 steps a n~ er of times equal to the number initially loaded
into the short timer.
When a 0 is detected in step 14W3, the operation jumps
to step 14W6 in which the mid-timer is loaded into the
accumulator and decremented. The contents of the mid-timer
is then checked at step 14W7 to determine whether it was a
0. If the mid-timer was not 0, a 1.3 millisecond delay is
provided by setting the short timer to a 12 state and looping
back to step 14W2. This causes the operations to loop through
steps 14W2, 14W3, and 14W4 twelve times until the short timer
again is decremented to 0.
Thereupon, steps 14W6, 14W7, and 14W8 will again be
performed and the entire procedure repeated until the mid-
timer was found to be 0 at step 14W7. Upon finding the mid-
timer to be 0 at step 14W7, the operation jumps to step 14W10
which sets up a 14.3 millisecond time delay by loading an
11 state into the mid-timer. The previously set lon~ timer
is then loaded into the accumulator at step 14Wll and is
decremented. Then, at step 14W12, the timer is checked to
detennine whether it was previously 0. If the lon~ timer was
not previously 0, operation loops back to step 14W8 and then
to step 14W2 and repeats the previously described loop until
operation arrives again at step 14w12 and finds that the long
timer was decremented to zero. This will signify that the
entire selected time delay such as Tl, during which the analog
signal was integrated has expired and operation can return to
_~5_
-.
~-~28~
. .
step 14B3 of Fig. 14B.
Returning to Fig. 14B; at step 14B3, the timing loop
counters which are going to be used during the time intervals
for integrating the reference DC source are cleared. The
S discrete outputs of the CPU 210 are disabled and the state
o the output 102 of the threshol~ detector'53 is examined.
If, during the first integr~ting interval Tl then (See
Fig. 12), the output of the integrator 51 becomes opposite
in polarity from the initial level V0 along a slope such as
~ SD to a level such as V3 such output xepresents a negative
raw weight oE relatively large magnitude. This might happen
if the platter were removëd or if an opera~or lifted up on
i~. I't will immediately cause the output of the threshold
detector 53 to switch to its low state. If the compara~ox
; 15 is found to be in a low state at step 14B5; then this indicates
at step 14B6 that a'large negative raw weight was detected
and therefore all the discrete outputs of the CPU are enabled
and operation jumps to step 14E14 at Fig.- l~E and then to
step 1~10. This xesul~s in skipping of many intermediate
2~ operations which check, filter, correct; or ot'h~rwise process
the raw weight and whLch would no~' be mèaningful with such nega-
tive weight d~ta.
However, if a positive raw weight'is found in step 14BS
such as would result rom the integration along slope Sl to
~1~ operation proceeds to step 14B8 which stops th~ int~ration
of the analog sisnal by switching transistor 94 to a non-
conductins state and besins the first reference source
integration, such as time interval T2, by switching the '
transistor 95 of Fig. 4 to its conducting s~ate.
Steps 14B9 through 14Bll form the interrogation and
counting cycle or instruction loop for the integration of
-56~
- `` 11~8~79
le COI~lparc!t O]- or tllresho1d detector durin~ the T2
ntc~,r~-ltion tiinfe of the :L'irst re~erence I)(, ~ource. Duri.nf~j
f'aCh illS tr.~cti.on loop, thf-~ output of the thresho1cl (lctec.~or
53 is }le-rioclica11y i.nterro~ated ancl a countc1- is incrcmented
eaC'.l time the output of the co~par~ltor h~ls not
chan~e~ si.C~n. Tllis countin~, ~or both the irst an(l secnnd
reference DC source inte~rating intervals T2 and T3 is done
in three, four-bi.t counters, one counter ~or each of three
llexa~lecim~l]. digi.ts.
While each of these thrce, four-bit counters could ~e
formecl in tilree, fo~lr-bit RA~I rc~isters, it is more conven-
ient to orm them in ~he ~Lve register ~17 forminc~ a part o~
the CPU 21.0 111ustrlted i.n Fi~. 9. The twe1ve bits oE the
save reg-i.st.er 817 comprise. three, four-bit counters
re.~errecl to as countc!r 1, counter 2, ancl co~mter 3. This is
; convcnient bec~u.se the Rockwc11 PrS-4/2 CPU has an instructioIl,
with tlle l~memonic C,YS, whi.ch cycles thc save registcr 8l7
nnd tl~ ccumu1nl:or. 'rhis convenicnt in~t:ruct:ion provides
; cl fol:lr-bi.t rift~ tt sh1t o.E the SilVC rcgistcr ~17 with the
our-bi.ts w'llic~l cr~e ~s~ tc(l o:~E the rif~ht et~ tlle save
rep,ister 81-/ bc;llf, t~ nscrrc?.~l to t~le accumu1ato~ nn~ with
t:hf.~ contents of thc accur~lu1.ltor beln~, transEerrcd into thc
Ieft elld o.~ tt~e sa~f! rc~:istcr f~17.
A~.; sl~own .in ~steps 1~9-14~A11, the coullti.n~ begins by
~etti~ e. carry r.~e~.L~.;ter ~2 of tllc CI'U 2lO (Fi.~. 9) to
its l. x~lt.e. Th;l~: carry i.s a(~(lecl to t:he conl:ent-s of counter
1. wi.t-.h t.llf: resu1ts ~ ced in collnlc~r 1. 'I`llen iu-)/ c~lrry
~o~neriltcd J:':rom counter 1 i.s aclded to tl~c contentC; of counter
:i.t~h t-hf' resu1t rlilced i.n countcr ~. Tl~en ,Iny carry
I-ro~uced ~y counter 2 is ~l~lde(l to tlle con~erlts oE oounter 3,
ancl t'l~e resu1t ~)1acecl in counter 3.
-57--
.
~ZY~79
. .
At step 14B10, the output 102 of the threshold detector
is then loaded to the accumulator and examined in step l~B12
to determine if it is yet low, that is whether the VO level
has been crossed. If the comparator is not low, operation
then loops back to step 14s9 where it passes again through
steps 14B9-14Bll. Each pass through this loop requires 65
microseconds using the specific selected CPU instructions.
Operation continues to loop through steps 14B9-14Bll until
the compaxator is found at step 14Bll to have switched to
its low state. This indicates that the output of the integrator
circuit 51 has crossed its initial voltage level VO.
An addit.ional 65 microsecond delay is then provided at
; step 14B12 to extend the second integrating time by the
interval T2C shown on Fig. 12 and described above. Then,, at
step 14B13, transistor 95 of Fig. 4 is switched to its non-
conducting state t:o halt the integration o~ the first reference
DC source.
The count contained in the three timing loop counters
~or the second integrating time interval T2 is then stored,
in the scratch p~d registers 70, 71, and 72 of the RAM,memory
and the counters (the S~ register 817) are cleared for ceuse.
Then at step 14B15, the third timing intexval T3 illustrated
in Fi.g~ 12 is hegun by switching the transistor 96 of Fig. 3
to its conducting state to apply the second rcerence DC
~25 source to the in-tegrator circuit 51.
'~ Then steps l~B16, 14B17, and 14B18 provide an interrogation
and counting cycle ox loop of steps 14B9-14Bll. ~lile the
steps of the T3 counting loop are not identical with the
steps of the T2 loops, they require the same overall time of
65 microseconds. During each pass through this T3 cycle, the
output 10~ of the threshold d2tector 53 is examined to
-58-
128~)79
,
determine whether it has returned to its high state. So
long as it has not, operation continues looping through
the T3 interrogating and counting cycle of steps 14B16 -
14B18. However, whenever in step 14B18 the output 102 has
found to have shifted to its high state, then at step 14Bl9,
the transistor 96 (Fig. 4~ is turned off to stop the integration
of the second reference DC source and the integrator 51 is reset
by switching the transis-tor 97 to its conducting state.
Then, at step 14B20, the contents of counter 1 and counter
2 of the T3 counters is stored in RAM memory register spaces
73 and 74. At step 14B21, the scratch pad memories (i.e.,
register spaces OlA through OlF) iIlustrated in Fig. 13
are cleared for subse~uent use.
Thus the contents of each four-bit register 70, 71, 72,
73, and 74 now represents a hexadecimal digit of the T2 and
T3 count which in turn represent the raw weight on the scale.
Next these counts are converted to decimal notation and then
finally to raw weight increments. This is begun in step 14B22
by multiplying the contents of register 72 ~which has stored
~0 in it the most significant hexadecimal of the T2 count) by
256 and moving the result to the weight register 02A through
02F illustrated in Fig. 13. Then, at step 14Cl, the weic~hk
sign is clear~d and the temyorary scratch pad register is
again cleared. The contents of register 71 (which has stored
?.S in it the next most significant hexadecimal of the T2 count)
the T2 counter is multiplied in step 14C2 by 16 and the result
moved to the arithmetic scratch pad register illustrated in
Fig. 13. Then, at step 14C3, the results of these two multi-
plications are added together with the result being moved to
the weight register. Then, at step 14C4 the least significant
hexadecimal digit of the T2 count is converted to decimal
-59-
- l~Z8~79
form and added to the sum in the weight register. At 14C5
the resulting total is placed in the weight register and
represents the total count during time interval T2 in decimal
~ digits. The arithmetic scra.ch pad register is then cleared.
While the digits of this decimal number are different from
the digits of the hexadecimal number, both numbers represent
the same number of counts or cycles obtained during the T2
interval and each coun~t represents 32 raw weight increments.
The decimal conversion of the T3 count then begins at
step 14'C6 by moving the contents of reqister 74 (which has
stored in it the most significant h'exadecimal digit of the
T3 count) to the arithmetic register. As stated pr'eviously,
the reference signal level during time intervaI T3 is 1/32
the re~erence signal level which is integrated during time
interval T2 and therefore each count during time interval
T2 represents 32 times as muah analog weight signal (i.e.,
' 32 raw weight increments) aS does each T3 count. In order to
eliminate the effect of the addition~l 65 microsecond delay pro-
v.ided at step 14B12 during time interval T2, (one additional
T2 count) 32 counts are sub~racted from the T3'count in
step 14C6.
Conversio~ of the ~3 count to decimal form then proceeds
at step 14C7 by multiplying the result of the subtraction in
step 14C6 by 16 and moving the result to the temporary
2~ scratch pad register (~ig. 13). The arithmetic register is
also cleared and in step~l4C8 the low digit of the T3 coun-t
, ' is moved from register-74 (Fig. 13) to the arithmetic
' register and converted to decimal~form. The result o~ the
multiplication in step 14C7 which is stored in the tempOrary
scratch pad re~ister and the result of the decimal ~onversion
~0-
, .
.
112~3[)79
of step 14C8 which is stored in the arithmetic register are
then added together in step 14C8 to repxesent the total counts
(raw weight increments) during time interval T3 reduced by
32 counts to compensate for the 65 microsecond delay as
described above.
Because each T2 count represents 32 times as much analog
weight signal amplitude as each T3 count, at step 14C9 the
total of the T2 counts is multiplied by 32 and the result is
moved to the weight register. Then, at step 14C10 the T3
count is subtracted from the T2 count in order to provide
the net number of raw weight increments. This final number
of raw weight increments, which is proportional to the sum
of the weight on the scale platter and the analog offset, is
then moved in step 14Cll to the weight register and is referred
to as the raw weight.
Process Weight
t
In the process weight operation VII, the presence or
absence of platter motion if first detected and noted, the
digital weight data resulting from step 14Cll is then filtered
or updated, the appropriate initial analog offset is digitally
subtracted and finally the "xlO EXPAND" operations are
per~ormed i~ that mode is selected.
The detection of motion begins at step 14C12 with the
subtraction of the filtered weight, which represents a
~5 pre~iously detected and processed weight which was stored
in the filtered weight register during a previous pass
through an operation sequence cycle. It is subtracted from
the most recently detected raw weight resulting from step
l~Cll. The sign of the result of this subtraction is moved
to the arithmetic sign register 019 in step 14C13.
-6]-
1~28~79
In step 14C14, a determination is made whet'her the
result of the above subtraction is l'ess than or equal to
five raw weight increments. If'this`result is Iess than
or equal to five raw weight increments, then this is
S accepted as one dètection of a no mot'ion condition and
operation goes to step 14C17 wherein a fifteen is loaded
into the accumu~ator and then added to the motion flag to
~ decrement the mot;on flag. It will be recalled that the
motion flag is a three state flag which required two
detections of no motion prior to concluding that no platter
mot.ion exists. Consequently, at step 14C18 the motion flag
is examined to determine whethex it had decremented to zero.
If the motion ~lag had already been zero, then no motion
existed for the last two passes through the operational
sequence cycle and conse~uently operation proce'eds to step
14C22. Howevex,'if the flag was not 'already zero, then'operation
:a~ ances to step 14C19.
I~ at step 14C14 the result of the subtraction was found
to be greater than 5 counts, then a motion condition exists
so in step 14C15 a two is loaded into the accumulator for
purposes o~ subs~quently settin~ the motion flag to its
two state and ope~ation proceeds to step 14Cl9.
At step 14Cl9 t~e motion flag is updated with eithex the
2 from step l~C15 or its decxe~lented state from step l~C17.
Then, at step l~C20 the output filter counter is set to its
three state to indicate that new weight data has been
detected. The recompute flag is also set to inaicate that
new price computations must be made subsequently and operati.o~
advances to step 14D5.
However, if at step 14C18 the motion fla~ was found to
have been zero, so that a no motion condi-tion was found to '
-62-
79
.~ i .,
exist, then the initial raw weight filtering operation
will occur at step 14C22. The purpose of raw weight
'~ fi.ltering is to eliminate the effects of noise and random
data shifts. In step'14C22-the least significant digit of
the most recently dete'cted raw weïght from step 14Cll is
written into RA~I register 035. The least si~.nificant digit
'' ' of the previously detected weight count is .written into RAM
register 034. Then, using the most recently detected raw
~eight and the two previous raw weights, a determination is
made at step 14Dl whether the least significant digit of
~the second previous detected raw weig'ht is e~ual to the least
" ' significant digit of the first previous raw weight. If these
are not equal then the filter'ing operations must be performed
beginning in step 14D3. I, however, at s~tep 14Dl these
digits are' found to be equal, then at.step 19D2 a determination
is made whether ~he least significant digit.of the first pre-
vious raw weight is equal to the least significant digit of the
most recently detected raw weight. If these are not.equal,
then filtering must be performed beginning at step i4D3.
Howevèr, if the 'least significant digits are found to be
equal in both steps l~Dl and 14D2, filtering~may be skipped
and operation jumps to step 14D5.
~he filtering operation whi'ch begins at step 14D3 consists
' essentially of forming a new filtered ~eight by adjusting the
'25- mo~t recently detected weight toward the previously detected
and modified weight which is stored in the filtered weight .
regis`ter ~E'ig. 13~. The most recently detected raw weight is
' adjusted toward the previously filtered weigh-t by one count
more than one half the difference between the previously
30 filtered~raw weight and the most recently detected weiyht.
Therefore, in step 14D3 the least siynificant digit of the
~63-
l~Z8~79
difference between the most recently detected ~leight and the
previous filtered weight is dlvided by 2 and then the integer
part of the result added to 1.
If in step 14D3A this difference divided by 2 is
found to be 0 (i.e., if the difference was 0 or 1, then the
filtered raw weight is written into the weight register (Fig. 13).
However, if the difference is not 0 or 1 then at
step 14D4 the most recently detected raw weight is adjusted
toward the previously filtered wei~ht by 1 count more then
~ the least si~nificant digit of the above difference. This
is then treated as a new filtered raw wei~ht and is first
moved to the weight register. Then, in step 14D5 this weight
is moved to the filtered weight re~ister to provide an updated
Eiltered raw weight for subsequent use.
It was previously described that potentiometer 76
is adjusted to provide a fixed analog o~fset under no weight
conditions. Therefore, this initial oset must be removed
from the detected raw weight data~ This is done in steps 14D6
through 14D14. However, because a different analo~ si~nal
integrating time interval is used for di~erent scale capa-
cities and the load cell ouput voltage is interpreted differ-
ently for different cap~cities, a different number m~st be
subtracted from the raw wei~ht for each scale capacit~.
Therefore, in step 14D6 the find scale capacity
subroutine o Fi~. 14V is performed which returns the data
described above. The returned data is used to set the
arithmetic scratch pad register to 003700 i~ the 6 K~ scale
capacity is selected, to 001600 if the 15 kilo~ram scale
capacity is selected, and to 001700 if the 30 pound scale
capacity is selected.
- 64 -
cg/~ ~
l~Z8~79
After the arithmetic scratch pad register is set to one
of these three numbers, which is the analog offset expressed
in raw weight increments for the par'ticular scale capacity
` selected, then in step 14D14 the chosen'number of raw weight
S ` increments is subtracted'from the raw weight and the result
is moved to the weight register.
` ` In step 14DlS a check is made to determine whether the
'' "x10 EXPAND" mode has been selected. If it`is not, which
` is the usual situation except when servicing, etc., operation
'' jumps to step 14E3.
. However, if the "x10 EXPAN~" mode has been' selected, a
;deter~ination is made at step 14D16 wheth~r the raw weight
is less than or equal to 2 raw weight increments. If it is,
operation proceeds 'to step 14D17 in which an 8 is loaded into
lS the accumulator for subsequent use in t~rning on the zero
lamp to indicate that the scale is zeroed; If, however, the
weight is found to be greater than 2 raw weight increments,
then operation proceeds to step 14Dl9 in which''a ~ is l'oaded
into the accumulat'or for subsequently turning off the zero
~lamp to indicate that the scale is not z~eroed.
After steps 14D17 or 14~19, operation proceeds to step
14D20 in which the 0 or 8 from the accumulator is loaded into
the zero lamp register 021 (Fig. 13) for later use in control
~ of the zero lamp. Also flag 2, 825, of the CPU 210 illustrated
; 25 in Fig. 9 is set to note that the "x10 EXPAND" mode has been
; selected. This flag is used in step 14D21 ~Yhich is the
subroutine for updating the output weight.
In the Update Output Operation XVII of step 14D21, the
five most or five least signiflcant digits of data in the
weight register ~Fig. 13) are moved to the output weight
register (Fig. 13) unless a negative weight is found or the
-65-
1128~79
., .
300 printer enable moae 10 is selectedO If either of
these two latter conditïons exist, op'eration jumps to
the weight blanking sequence of operations beginning at
step l~E14.
Referring in detail to the Update Output Weight
operation in Fig. 14X; at step 14Xl, the computer is set
up to check the five most significant digits of the weight
register for all zeroes and flag 1 of the CPU 210 is set.
' Then, in step 14X2 flag 2 of the CPU 210 is checked to
determine whether it is set to indicate the normal mode
'' of operation or whether'it is reset to note the "x10
EXPAND" mode of operation. If flag 2 is found to be reset,
then in step l~X3, the previous step 14Xl set up is changed
to set up to check all 6 weight register diyits as is
~ appropria'te for the "x10 EXPAND'i ~ode. Otherwise, if flag
! 2 is found to be set in ste~ 14X2, operation proceeds directly
to step 14X4.
In step 14X4, the digits are checked to de~ermine if they
are all 7~ero. If ~11 digits are'found to be zero, then in
step 14XS fl~g 1 of the CPU 210 is reset to note that the'
weight is zero.' If, however, the digits are no~ all ~ero,
' then operation proceeds directly to step 14X6.
: Then, in step 14X6, the weight register s'ign data is
'~' decremented to 15 if it is a plus and to'14 if it is a
~5 minus. Additionally, the carry is set if it ïs a minu's. In
. step 14X7, the registers ar'e'set up'to adctress the most
significant digit o the 5 digit we'i~ht for the normal m'ode
''of operation. Then in s~ep 14X8 flag 2 is interrogated to
determine whe~her it is sét to indicate a normal mode of
3~ operation. If it is set, operation jumps directly to step
14X10. However, if ~lag 2 is not set, then the "x10 EXPAND"
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mode is selected and the next lowex significant digit is
addressed for the "xlO EXPAND" mode.
In step'l4X10, the weight is interrogated to determine
if it is 0. If the we'ight is not O'then a'15 is loaded
into the appropriate digit position so that the negative
sign is not displayed for a zero weight. If, however, a
non-zero weight is detected at step 14X10, then operation
proceeds to step 14X12.
In step 14X12 the proper sign is placed in the proper
position and in step 14X13 the removed weight digit is '
~examined to determine whether it is zero. If it is zero,
operation jumps to step 14X17. If it was not zero, the
digit is returned to the proper position in step 14X14 and
' the sign is forgotten. Then in step 14X15, the weight sign
is examined. I the weight sign was minus; operation loops
'back to the blank weight step 14E14; If, however, the sign
was not minus, then R~M register 040 is interroga~ed in step
' 14X16 to determine whether the Toledo Scale ~00 printer is
enabled.' If the 300 printer is enabled, then operation loops
'20 back to the bla~k weight step 14E'14 because the 300 printer
cannot accommodate the required numbe~ o'f significant digits.
i~ the 300 printer is fo~nd in step 14XI6 not to be enabled
or if the exchanged digit examined in step 14X13 is found to
; be zero,'then operation advances to step 14X17~
In step 14~17, the reg:isters are set up to move the five
most significant digits of'weight to the output weiyht
register. Then, in s~ep 14X18 flag 2 is chec~ed to see if
it i5 set so that operation is in the normal mode.' If flag
2 is set, operation advances to step 14X20 and the output
weight register is updated with the 5 most significant digits
; of the weight register.
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llZ8~t79
If, however, flag 2 is not set, thereby indicating
that the "x10 EXPAND" mode has been selected, then operation
advances to step 14Xl9 which sets up the registers to write
the 5 least significant digits of weight into the output
weight register at step 14Xl9. Then, in step 14X20 the
output weight register has the selected five significant
digits of the welght register written into it. After step
14X20 operation returns to the'next step after it was called.
~ Returning therefore to Fig. 14D, after the output weight
register is updated, the price and total price registers are
blanked in step 14D22 because they are not used in the "x10
EXPAND" mode. Operation then proceeds to step 14El in which
the tare register and the auto-zero register are cleared.
Operation then jumps to the output operation XXl at step
14'M19 because the intermediate steps are not significant in
the "x10 EXPAND" mode.
Manual Zero Capture
In the usual situation, where the "xl0 ~XP~ND" mode is
found at step 14D15 to not have been selected, operation
advances to the manual zero capture operation VIII at step
14E3.
i In the manual zero capture operation VIII, a series of
checks are first made to determine whether the scale should
be zeroed. If the scale should be zeroed, the raw weight
in the weight register is written into the auto'zero registar
(Fi~. 13). The data in the auto zero register is then
subtracted ~rom ~he detected weight to provide a corrected
` raw weight and A chëck for overcapacity is made.
Considering the manual zero capture check'operation VIII
in ~reater detail, the RAM memory is checked at step 14E3 to
determine ~hether the "Z" key was pressed. If the "Z" key '
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was not pressed, then the zeroing operation is skipped and
operation jumps to step 14E10 because manual zeroing is not
desired where not initiated by depression of the "Z" key.
If, however, the "Z" key is found in step 14E3 to have
been depressed, then operation proceeds to step 14E4 to
check the net flag to determine whether the system is in the
net mode. If the system is already in the net mode then
gross zeroing is not appropriate and operation jumps to step
14E10. However, i~ the system is found not to be in the net
mode, then at step 14E5 the motion flag is checked to determine
whether motion exists. If motion exists, then the weight data
detected during such motion should not be used for zeroing
purposes and operation similarly jumps to step 14E10. However,
if the motion flag has not been set then at step 14E6 a two
is added to the zero key timer and it is ~hecked in step 14E7
i to determine whether it is zero. If the zero key timer is
found not to have advanced to zero, then the 'IZ'! key has not
been depressed sufficiently long to permit zeroing of the
weighing scale so that operation jumps to step 14Ell.
However, if at step 14E7 the zero key timer has gone to
zero, then at step 14E8 a check is made whether the weight
count is less than 400 raw weight increments. If the weight
count is greater than 400 raw weight increments, a signi-
` ~icant weight must exist upon the platter ahd conse~uently
zeroing would be undesirable and operation jumps to step
14Ell. However, if the weight is less than 400 raw weight
increments, operation proceeds to step 14E9 in which the
detected weight data is moved into the auto zero register
and the zero done flag is set to indicate that the scale is
zeroed. At step 14E10, the zero Xey timer is cleared.
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When operation proceeds to step 14Ell, the data in the
auto-zero register is subtracted from data-in the weight
register. The da~a in the auto-zero ~egister represents
the correction factor used to zero the weighing scale.
5 .Consequently, when subtracted fr.om weight data the result
represents the accurate, zeroed weight upon the weighing
scale plat~er.
~ hen, at step 14E12 this zeroed weight is su~tracted
from 030050, which represent a weight which is' 50 raw weight
increments beyond the scale capacity to determine whether
the scale is reading a weight beyond its maximum capacity.
A check is then made in step 14E~3 to determine w~ether
the result of this subtraction is positive. If it is negative,
this indicates that the scal'e is not beyond. its capacity and
conse~uently operation proceeds to-the gross auto zero
correction operation IX at step 14E16.
However, if the result of the subtraction is positive,
the scale is overcapacity and operation advances to step
14E14 wherein the output weight is blanked~ From step l~E14
operat'ion advances to step 14E14 wherein the output weight
is blanked. From step 14E14 operation-then jumps to step
14M10 for blanking the total price and continuing the operation.
Gross Auto Zero Correction ' '~ ~ '
Although the weighing scale~of the''present invention may
be manually zeroed às provi~ed in oper~tion VIII the' zero will
still be subject to some d.rift or t~andering. It is ther'efore
desirable to automa'tically track these changes in order to
maintain an accurate correction'factor in the auto zero
' register.
In the gross auto zero correction-operation IX, the
corrected weight from'step l~Ell is exa~ined to determine
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. , .
whether the scale is within an auto zero correction band o
4 raw weight increments within which the gross zero will be
automatically tracked or corrected. If the raw weight is
within the auto zero correction band, the zero increment
-flag lS set. If the total auto zero correction factor will
less than 400 raw weight increments and the corrected raw
weight is not already exactly zèro, then the auto zero
correction factor is corrected by one raw weight increment.
~ Examining the gross au~o zero correction operation IX
~0 in detail, the raw weight from step 14Ell is examined in step
14E16 to determine whether it is less than or equal to 4 raw
weight increments. If the raw weight is found to be less than
or equal to 4 raw weight increments then the scale is within
the auto zero increment and operation proceeds to step 14El9.
15 In step 14El9, a 15 is loaded into the accumulator in order
to subsequently set the zero increment flag to note that the
scale is within the auto zero increment.
If in step 14E16, the corrected raw weight from step 14Ell
is found to be greater than 4 raw weight increments then in
step 14E17, a 0 is loaded into the accumulator for subsequent
clearing of the zero incrèment flag to note that the scale
is not within the auto zero increment.
Then, in step 14E20, the number previously loaded into
the accl~mulator is written into the zero increment flag and
25 flag 1 of CPU 210 is set to note the gross weighing mode.
At step 14E21, the aorrected-raw weight is again examined
to determine whether it is either outside the auto zero
correction band or equal to zero because in either situation
correction of the auto zero register will be skippea. There-
30. fore, if at step 14E21 the.raw weight is found to be greater
than 4 counts or èqual to 0, operation jumps to step 14Fl .
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1~213~79
If, ho~ever, the raw weight is within the gross auto zero
~correction band but is not equal to zero, operation proceeds
to step 14E22 which is the "Correct Auto Zero" operation
XXVIII beginning at step 14Yl of Fig. 14Y.
Referring now to Fig. 14Y, at steps 14Yl and 14Y2, the
arithmeti~ scxatch pad register is cleared and 2 factor of
one is written into its least significant digit. The weight
sign is loaded to the accumulator and complemented and then
is written into the arithmetic scratch pad sign register.
Then t~e auto zero register is addressed.
In step 14Y3, flag 1 is interrogat'ed to determine whether
it is set to note the gross mode or reset to note the net
mode since the Correct Auto Zero Operation XXVIII is used for
gross ~auto zero correction as well as net zero trac~ing.
Therefore, i~ flag 1 is found in step 14Y3 to be set, opPxation
jumps to step 14Y5 for.the gro~ss auto zero correction while,
if ~he flag 1 is found in step 14Y3 to be ~eset, then operation
advances to step 14Y4 in which the'address is changed to the
tare register which is correcte~ in net zero trackiny.
In step 14Y5 the 1 which was prevously loaded in the
arithmetic scratch p~d regi.ster is a,lgebraically added t:o
' either the auto zero register or the tare register depending
' upon which is addressed as a r~sult of steps 14Y2, 14Y3 and
14Y4. ~he result of this correction is written into the RAM
~5 result'registers 005 thra~gh 00~.
Then, in step 14Y6 flag 1 is again interrogated to
determine whether the scale is in the gross mode. I it is
not in the gross mode, operation returns to the calling
operation. However,'if the scale is in the gross mode
3Q ' operation proceeds to step'l4Y~ in which the corrected result
is examined to determine whether it is less than 400 raw
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.1 . .
weight increments.
If the resulting gross auto zero correction factor is
less than 400 raw weight increments, then at step 14Y10 the
auto zero register is updated with the corrected auto zero
factor from the result register. However, if the result is
equal to or greater than 400 raw weight increments then no
further auto zero tracking is permitted. This prevents the
zero increment from being more than 400 raw weight increments
from the factory determined zero. Operation then returns
to the step after the calling operation leaving the auto zero
register with its previous contents~
MuIti 1 Raw Wei ht B Pro er Factor
p ~ g Y P
Referring to Fig. 14F, up until this point in the sequence
of operations, the weight is represented in raw wei~ht increments
regardless o the scale cap~city which has been selected with
30,000 raw weight increments representing full scale capacity.
In this operation X, the raw weigl-t is multiplied by the
proper integral factor to con~ert the raw weight digits to
digits representing the selected and convention~l units of
~0 weight.
At step l~Fl with the find scale capacity subroutine
operation XXV is performecl and will return to the accumulator
a 5 if the lS kilogram scale is selected, 1 if the 30 lb:
scale is selected and 2 i the G kilogram scale is selected.
Thus, in step 14F2 the returned multiplier is written into the
arithmetic scratch pad register and in step 14F3 it is multiplied
by the raw weight with the result being moved to the weight
xegister. Therefore, after step 14F'3, the digits in the weight
register represent the decimal digits of the detected weight.
In step l~F4, the most significant digit of the price
register is examined to determine whether it is greater than
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o.r Pqual to 8. This interrogation of the most signiicant
digit of the price register is necessary because, if the
verify key was depressed elsewhere in the sequence of the
operation, that will cause all 8's to be loaded into the
price digits. Therefore, lf an 8 or 9 is found in the most
signiflcant p~ice digit, operation will proceed to step 14F5
to clear the price register, factor flag and digit timer and
to clear the total price if the weight is positive and to
blank the total price if the weight is negative.
However, if the veriy key was not depressed and consequently
an 8 or 9 is not found in the most si~nifica~t price digit,
ope.ration jumps from step 14F4 to step 14F6. It might be noted
that a result of steps 14F4 and 14F5 is that the operator will
not be permitted to input an 8 or 9 to the most significant
price digit and get meaningful results. However, this presents
no problem because such large prices are not encountered in
the usual operation of the weighing scale.
Manual Tare
The manual tare operation XI permits the operator to place
~0 a tare object on the sc~le platter and have the tare weight
w.ritten into memory. In this operation, ~ seri~s of checks are
performed and if conditions are proper, the ~eight is written
into the tare weight regi.ster, some flags are conditioned and
some registers ar~ then cleared.
2.S At step l~F6, the zero done flag i5 interrogated to see
: whether the weishing scale was previously zeroed. If it was
not, then the tare operation and the net mod~ of operation
are not permitted so that operatlon will jump to s~ep 14F22.
However, if the scale was zeroed, the state of the manual
tare flag is written into the acc~ulator and the manual tare
flag xegister is itself cleared in step 14F7 ~ In s~ep 14F8
:
~'.
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`` 11~8~79
.
The manual tare flag is examined to determine whether it is
set. If it is not set this indicates that the tare key was
not depressed and detected during the read keyboard operation
XXIII and therefore operation jurnps from step 14F8 to step
S 14Gl, skipping the manual tare operation.
If, however, the manual tare flag is set then in step
14F~ the motion flag is in.errogated to determine whether
there is motion. If the motion flag is found to be set so
that motion exists, then erroneous tare weight data would be
on the scale. Therefore, operation jumps from step 14F9 to
s~ep 14G1.
However, if no motion is detected, then in step 14F10
the most significant digit of the weight register is examined
to see if it contains a zero. If it does not, operation must
lS jump to step 14Gl and the manual tare operation skipped because
; the most significant welght digit will be used to display a
negaki~e sign in the net mode of operation.
If the most significant digit of the weight register is
found to be zero, operatior~`proceeds to step Fll, in which the
zero increment f~ag is examined to determine whether the
scale is within khe auto æero correction band. If the scale
was within the auto zero correction band, operation proceeds
to step 14F13, but if it is not then the weight sign is
examined to determine whether it is minus. If the weight sign
~5 is not minus, operation continues to step 14F13.` However,
if the weight sign is found to be minus, operation jumps to
step 14Gl.
In step 14~13 preparations are made for moving the weight
to the tare`register. The zero increment flag is then examined
in step 14F14 to again determine whether the scale is within
the auto zero cor1-ec~ion band. If it is not, operation
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:
proceeds to step 14F16 at which the weight data in the weight
register is moved to the tare register to store it as the tare
weight.
If at step 14F14, the scale is found to be within the auto
zero correction band, then at step 14F15 the register is
cleared so that in step 14F16 alI zeroes will be moved into
the tare register. Steps 14F14, 14F15, and 14F16 permit the
entry of a zero tare weight in order to permit the operator to
intentionally override or~ satisfy the tare mandatory mode if
that mode was selected at the factory. It also assures that
zeroes will be displayed whenever the weighing scale is within
the auto zero correction band even though it is not at absolute
zero.
Operation then proceeds to step 14Fli in which the zero
increment flag is again examined to determine whether the
weighing scale is within the auto æero correction band. If
it is not, an 8 is loaded in step 14F18 into the accumulator
for subsequent use to set the net flag and thereby indicate
that the weighing scale is in the net mode. If, however, the
weighing scale ïs found in step l~F17 to not be in the auto
zero correction band, then operation jumps to step 14F20
in which zeroes are loaded into the accumulator for subsequent
use to clear the net flag and thereby indicate that the
weighing scale is in the gross weighing mode.
Then ~t step 14F21, the contents of the accumulator from
either step 14F18 or 14F19 is wri~ten into the net flag, the
tare done flag is set to indicate that the tare operation has
heen completed and the recompute flag is set to indicate that
a new price must be computed upon entry into the compute total
price operation XX. Then, in step 22 the price register,
~: -76~
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factor flag and the digit timer are all cleared. The total
price is cleared if the weight is plus and is blanked if the
weight is minus.
Subtract ~are
Operation then proceeds to step 14Gl at whic~ the tare
weight is subtracted from the weight and the resulting net
weight is written in-to the weight register.
Net Auto Zero Correction
-
As explained abov~, the exemplary embodiment tracks changes
in the net zero by modifying the tare register data to correct
for such changes. This is done in steps 14G2 through 14G15.
In step 14G2 the weight in the weight register is examined
to determine whether it is zero. If the weight is zero then
no net auto zero correction is needed and operation jumps to
the auto clear operation XIV at step 14F16. If, however, the
weight is not zero, then the net flag is interrogated to
determine whether it is set. If it is not set indicating that
the weighing scale is in the gross weighing mode, then the
net auto zero correction is skipped and operation jumps to
step 14G16. I~; however, the net flag is set, then operation
proceeds to the find scale capacity op~ration at step 14G4.
Because the weight data in the weight regist~r is no
longer in raw weight incremen~s but has been c~nverted to
weight units appropriate for the selected scale capacity, the
~5 band for the net ~ero correction will be diferent ~or the
diferent scale capacities.
Therefore, in steps 14G5 throu~h 14Gll, the data ret~rned
by step 14G4 will set the arithmetic scratch pad register to
0000'~9 i.f the 6Kg scale capacity is selected, to 00025 if the
15Kg scale capacity is selected and to 000005 if the 30 pound
scale ca~.lcity is selected.
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.
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11~8U79
Then, at step 14G12 the number written into the arithmetic
scratch pad register is subtracted from the weight and Elag 1
of the CPU 210 is reset to note the net mode. Then in step
14G13, the result of the above subtraction is checked to
determine whether it is po~itive. If the result is positive r
then the weight is above the net zero correction band and
operation proceeds to step 14G16 without any correction. If,
however, the result of the subtraction of step 14G12 is found
in step 14G13 to be negative, then the tare register is
corrected in step 14G14 as previously described by the correct
auto zero operation XXVIII, with the result of the correction
being written into the tare register in step l~G15.
Auto Clear
In the auto clear operation the tare and price registers
are to be automat.ically cleared after an object has been
weighed if that mode is selected. They are cleared if the
scale rises above ten scale increments, remains for a
sufficient length of time above the ten scale increments and
then falls below the ten increments.
The auto clear operation XIV begins at step 14G16 with
the find scale capacity operation. The multiplier digit
which is returned to the accumulator is then w~itten into
the ~hird least significant digit of the arithmetic scratch
~d rc~gister in step 14G17. The number written into the
.5 scratch pad register at step 14G17 represents 100 raw weight
:irlCLementS for the selected scale capacity. That number is
then subtracted at step 14G18 from the weight and the result
is examined at step 14Gl9. If this result is plus, this
indicates that the scale is st.ill weighing a weight above
the 100 raw we.i~ht increm~nts and that therefore the price
and tare registers should not yet be clear. Therefore,
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operation will jump to step 14H4.
However, if at step 14G19 the result is found to be
negative, then the weight is below 10 scale increments and
the auto clear flag is cleared at step 14G2G. Then in step
l~G21, the state of the auto clear lag prior to clearing
in step 14G20 is examined to determine whether it was equal
to 6. If the auto clear flag was equal to 6, this indicates
that the weight previously had been above 100 raw weight incre-
ments ~or a sufficien, length of time that the tare and price
registers should now be cleared and operation will advance
to step 14G22. If, however, the auto clear flag had not
advanced to a 6, then the weight was not above 100 raw weight
increments for a sufficient length of time and clearing of
these registers should not be done. Therefore, operation
will jump to step 14H6.
At step 14G22, a determination is made whether a
~'prepack" or "by count" mode is selected. If a "prepack"
or "by count" mode is selected, then auto clear will be
s~ipped because any price and tare data in the price and tare
registers will be used in subsequent weighing operations.
However, if in step l~G22 neither the "prepack" or "by count"
mode is selected, operation advances to step 14Hl in which
memory register 053 is examined to determine whether the
auto clear mode was selected. If the auto clear mode was
not selected, operation jumps to step l~H6 and automatic
clearlng is skipped. I~, however, auto clear is enabled,
then operation advances to step 14H2 and the tare register,
the price register, the factor flag and the digit timer are
: cleared. The total price is cleared if the weight is positive
and blan~ed if the weight is negative. After step 14H2,
. .
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operation advances to step 14H6.
lf in step 14Gl9, the result of the previous subtraction
indicated that the weight was still above the 100 raw weight
increments, then operation advances to step 14H4 in which
the auto clear flag is interrogated.
If the auto clear flag is found to have advanced to its
"six" state, this indicates that the weight has been ahove
100 raw increments sufficiently long to permit automatic
clearing whenever the scale weight falls below the 100 raw
weight increments. Therefore, nothing is done to the auto
clear flag and operation advances to step 14H6. If, however,
the auto clear flag has not advanced to its "six" state,
then in step 14~5 the auto clear flag is incremented.
Zero Lamp
In the Zero lamp operations of steps 14H6 through ~4H20,
a check is made to determine whether the weight data is within
a small range of zero referred to as the zero increment range.
If it is found to be within this range on two successive
checks it is considered to be in this range and the zero lamp
is turned on.
In operation l~H6, the find scale capacity operation XXV
is performed, and in operations 14H7 through 14H13, the data
xeturned by step 14H6 is used to set the arithmetic scratch
pad register to a S i~ the 6 kilogram scale is selected, a
1-~ if the 15 kiloyram is selected and a 3 if the 30 lb. scale
is selected. Then, in step l~H14 the number set in the
axith-netic scratch pad register is su~tracted from the weight
and the result is examined in step H15 to determine whether
it is plus. If the result is plus, the weight is above the
zero increment range. Therefore, in step 14H16, a 2 is loaded
to the accumulator for subsequent use in setting the zero lan)p
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flag so that the zero lamp will be turned off. Operation
then jumps to step 14H20.
If in step 14H15 the result of the subtraction of step
14~14 is found to be negative then the scale is within the
zero increment range. However, since it must be within the
zero increment range on two successive checks before the
zero lamp is to be turned on, operation advances to step
14H18 in which the zero lamp flag (which has three states)
is written into the accumulator and decremented. Then in
step 1~19 the flag is examined to determine if it was zero.
If it was not zero, operation advances to step 14H20 in which
either the decremented state of the zero lamp flag from step
14H18 or the set state from step 14H16 is written into the
zero lamp flag register. If it was zero, then the zero state
in the zero lamp flag register continues so that the zero
lamp remains on.
Round Off
; ~11 the above operations involving weight data have been
done with six significant digits of weight data. In the
round off operation XVI, the weight data is rounded of to
fewer significant digits.
Consequently, at step 14H21 the find scale capaci~y
operation XXV is performed and its results examined to determine
which scale is selected. If the 6 kilogram scale is selected
operation jumps to step 14I4. If, however, the 6 kilogram
scale is not selected operation advances to step 14Il in which
the 6 digit weight in the ~eight register is rounded off to
; 5 significant digits and the 6th digit is cleared.
Then, at step 14I2, the data returned at step 14H21 is
examined to determine whether the 30 lb. scale has been
selected. If it has been selected, no further round off is
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required and operation jumps to step 14I14 at the beginning
of the output filter operation XVII.
However, if the 30 lb. scale is not selected then the
lS kilogram scale must be selected and operation jumps to
S step 14I7 for rounaing off by 5. At step 14I7 the 5th least
significant digit of the weight is examined and if it is
less than 3, operation jumps to step 14Ill in which a zero
iS lOadea iIl the accumulator. If, however, the 5th least
significant digit is not less than 3, then it is examined
at step l~I8 and if it is not less than 8, operation jumps
to step 14Ill in which a zero is loaded into the accumulator.
However, if it is less than 8, a 5 is loaded into the
accumulator at step 14I9 and operation advances to step
14I12.
If the fi kilogram scale was found in step 14H22 to have
been selected then in step 14I4 the least significant ~igit
of the five digit weight is examined. If it is odd, the
carry xegist~r of the CPU 210 is set and operation jumps
to step 14I13. If, however, in step 14I4 the least
significant digit o~ the S digit weight i5 found to b~ even,
then operation jumps directly to step 14I13.
In step 14I12 whatevex is loaded into the accumulator in
step l~I9 or 14Ill is wxitten into the 5th least significant
weight di~:lt register. Then at step 14I13 the carry register
is added to the 4th least significant digit of the weight
register with the result being written into the weight
register.
Out~ut Filter
In ~he output filter operation XVII, the most recently
detected weight is compared to the weisht currently being
displayed to de-termine if it is different enough from the
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displayed weight to justify an update of the displayed
weight. If a suf~icient difference occurs 3 times in
succession, such an update will be made.
Therefore, in step 14I14 the output weight is moved
from the output weight register to the arithmetic scratch
pad register along with its sign. This output weight is
then subtracted from the weight in the weight r~gister in
step 14I15. Then in step 14I16, the motion flag is examined.
I~ the motion flag is set, operation jumps to step 14I22.
If the motion flag is not set then at step 14I17 the find
scale capacity operation XXV is performed. Then, at step
14Il9, a determination is made whether the result of the
subtraction in step 14I15 is less than or equal to the
number xeturned by step l~I17 which represents 10 raw weight
increments for the selected scale capacity.
If the result of the subtraction is not less than or
equal to the returned dlgit, then operation jumps to step
14I22. However, if the result is less than or equal to the
returned digit then in step 14I20 the result is e~mined
to see if it is zero. If it is found to be zero, then there
is no di~ference between the recently detected w~ight and the
output weight and updating is unnecessary and consequently
operation jumps to step 14J4. However, i~ the result is not
zero, the filt~r counter is examined to determine if it is
less than 3. If it is not les.s than 3, then it has not timed
out and a diffexence has not been observed ~ sufficient number
of times to require updat:ing of the output weight. Thexefore,
if the output filter counter i5 less than 3, operation jump5
to step 14J6 where the output ~ilter counter is loaded into
the accumulator and incr~ented. If r however, the output
~ilter counter is found to not be less than 3, operation
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` ` ~128~79
advances to step 14I22.
In steps 14I22 flag 2 of the CPU 210 is set to note that
the S most significant digits of weight data will be subsequently
used. Operation then advances to step 14Jl. At step 14Jl,
the memory is checked to determine whether the "by count"
mode is selected. If it is, no updating of the output weight
display data is appropriate and therefoxe operation jumps to
step 14J4. If, however, it is not in the "by count" mode,
then operation advances to step 14J2 which is the update
output weight subroutine operation XXVII illustrated in
Fig. 14X and described above. After the output weight is
updated, then in step 14~3 the recompute flag is set and the
print flag is cleared. In step 14J4 the output filter
counter is cleared and operation jumps to step 14J7.
In step 14J7, the output filter counter is updated with
either the incremented filter counter from step 14J6 or the
cleared filter counter from step 14J4.
Load Lamps For Output
In this operation the various lamp status flag registers
are checked and~their status used to update the lamp statuc:
registers 020 through 026 for use in controlling the front
and back indicator lamp displays.
In step 14J8, the motion flag is examined. If the motion
; flag is set then motion exists and a zero is loaded into the
2~ accumulator and used in step 14J9 to update the LB/KG lamp
re~ister so that the LB/KG lamp subsequently will be turned
off during the motion condition. I~, howev~r, the motion
flag is not set, then an 8 will be loaded to the accumulator
or subsequent use in step 14J9 for updatiny the LB/KG lamp
register so that the LB/KG lamp subse~uently will be ~urned on.
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llZ8~79
In step 14J10, the zero lamp flag is examined. If the
zero lamp flag is found to be 0, then an 8 is loaded to the
accumulator for use in step 14J11 to update the zero lamp
re~ister to subsequently turn on the zero lamp indicating
that the weighing scale is zeroed. If, however, the zero
lamp is not zero, then a zero is loaded into the accumulator
for use in step 14Jll to update the zero lamp register and
subsequently turn off the zero lamp.
In step 14J12, the net lamp register is updated with
the state of the net flag.
In ~tep 14J13, the second bit of the factor flag is
examined. If it is set, then an 8 is loaded into the
accumulator for use in step 14J14 to update the per 1/2
lamp register. However, if it is not set, then a 0 is loaded
into the accumulator for use in step 14J14 to update th~ per
1/2 larap register so that the per 1/2 lamp will be turned
off.
In step 14Jl~, the 4th bit of the factor flag is examined.
If it is set, an 8 is loaded into the accumulator for use in
step 14J15 in updating the per 1/4 lamp register so that the
per 1/~ lamp will be turned on. However, if the 4th bit of
the factor flag is not set, then a 0 is loaded into the
accu~ulator for use in step 14J15 in updating the 1/4 lamp
register so that the per 1/4 lamp will be off.
In step l~J16, R~ register 045 is interrogated to
determine whether the U~ scale has been selected. If it has
been selected, then operation jumps to step 14J20. If the
UK scale has not been selected, then a determination is made
in step 14J17 whether the "prepack" or "by count" mode has
been selected. If the "prepack" or "by count" mode has been
selected, an 8 is loaded into the accumulator for use in
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step 14J18 in updating the prepack lamp registers. If,
however, the "prepack" or "by count" mode is not selected,
a 0 is loaded into the accumulator for use in updating the
prepack lamp registers in step 14J18 so that the legend
will not be backlighted.
Interlock Check
In the interlock check operation, various conditions
are checked to determine whether operation should proceed
to the computation o a total price in operation or should
skip that operation and jump to the next.
In step 14J20, the "by count" mode is checked. If the
"by count" mode has been selected, then operation advances
to step 14Kl in which the output weight is blanked as is
appropriate for the "by count" mode and then operation j~ps
to step 14K6 skipping the check to determine whether tare has
been done. If it has no1 been selected, opPration proceeds
to step 14K3 to determine whether tare has been done.
At step 14K3, a determination is made whether tare has
been done. If tare has been done, operation jumps to step
14K9 to determine whether the recompute flag is set. However,
if tare has not been done, then in step 14K4 a determination
is made whether tare is mandatory. I tare is not mandatory,
then o~eration advances to step 14K9. However, if tare was
not done and tare is mandatory, then a price should not yet
be computed so operation advances to step 14K5 which clears
any total price if the weight is positive and blanks total
price if the weight is negative.
Operation then continues to step 14K6 in which the
contents of the recompute flag register is written into the
accumulator and the recompute flag register is cleared. Then
in step 14K7 the condition of the recompute flag as written
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128Q79
into the accumulator is checked. If the recompute flag
was set, operation skips to step 14Mll and i~ the recompute
flag was not set then operation skips further to step 14N15.
However, if the tare was done or was not mandatory, then
in step 14K9, the recompute flag is similarly written into
the accumulator and the recompute flag register is cleared~
In step 14K10, the condition of the recompute flag as writt~n
into the accumulator is examined. If the recompute flag is
set so that a new computation of a total price is called for,
operation advances to the compute total price operation
beginning ~ig. 14K. However, i~ the recompute flag was not
set, then the currently exhibited price, weight and total
price data do not need modification. Therefore, both the
compute total price operation XX and that portion of the
; 15 output operation XXI which outputs new weight, price and
total price data may be skipped. Operation therefore jwmps to
step 14N15.
; Compute Total Price
In the Compute Total Price Operation XX, the presence
~0 of a factor is checked and if one has been input, the price
i5 multiplied by the factor. This product is checked for
overprice and if not overpriced a check is made whether
pricing per unit is mandatory. Then if the weight is positive
it i5 multiplied b~ the price and the resulting total value
~5 is rounded o, checked for overvalue and if not overvalue
is stored in the total price register (Fig. 13).
The computation of the total price begins in step 14K11
with the clearing of the arithmetic and temporary scratch
pad registers and the setting of flag 2 to assume that the
weight is to be multiplied by a factor. 'rhen, in step 14K12
a determination is made whether the price is to be multiplied
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, :
' ' ~IZ8~P79
by a factor of 2 or 4. If the weight is not to be multiplied
by a factor, operation proceeds to step 14K13 in which flag
2 is reset to note that the detected weight is to be
multiplied directly by price without first requiring that
S the price be multiplied by a factor. Operation then jumps
to step l~L10. However, if the price must first be multi-
plied by 4 or 2, operation proceeds to step 14K15 in which
the price is multiplied by the appropriate factor.
The result of this multiplication will be 11 digits
long. If 5 digit pricing ls used, then the 6 most significant
digits of the result must all be zeroes and if 4 digit pricing
is used, then the 7 most significant digits of the price must
be zeroes.
Therefore, in step 14K16, a determination is made whether
5 digit pricing has been selected. If it has, the 6 most
significant digits of the result are checked in step 14K17
for any non-zero digit. However, if 5 digit pricing is not
selected, then in step 14Kl9 the 7 most significant digits
of the result are checked for any non-zero digit.
Since the presence of a non-zero digit in the check of
steps 14K17 or 14K19 will indicate that the price constr~ints
have been exceeded, in step 14K20 the results of these checks
are examined to determine whether the multiplication has
produced an overprice. If the result is overpriced, operation
advances to step 14Ll in which the price register, factor
flag and digit timer are cleared. The total price is cleared
if the weight is positive and blan~cd if the weight is
negative. Thereafter, operation jumps to step 14Ml9.
However, if there is not an overprice, operation advances
3~ from step 14~20 to step 14L3. In this step, a determination
is made whether the mandatory pricins per unit mode is
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` ` l~Z8~79
.
selected. If it is not, operation advances to step 14L8
in which the address registers axe set up to move the result
of the price times factor multiplication to the weight
register. Therefore, with the mandatory pricing per unit
not selected, the result of the price times factor multi-
plication will, in step 14L9, be moved into the weight
register.
However, if price by unit is found in step L3 to have
~een selected, then in step 14L4 flag 2 of the CPU 210 is
set to note that the price will be multiplied by the weight
to determine the total price. Then, in step 14L5, a 1 is
written into the factor flag register 013 to note that
factoring is done and the 2 or 4 previously stored therein
is removed. Operation now advances to step 14L6 in which
the recompute flag is set and the règister address is
; modified to set up to move the result of the price times
factor multiplication into the price register.
Operation then advances to step 14L9 from either step
14L6 or step l~L8. The result of the price times factor
multiplication is moved to either the weight register or
the price register depending upon whether step l~L6 or l~L8
preceeded step 14L9.
In step 14L10, the output weight sign is examined. If
it is found to be negative, then an error occurred in the
computa~ion and operation advances to step 14Lll which sets
the recompute ~lag and loops the operation back to step 14K5.
However, if the output weight sign i6 positive, then operation
advances to step 14L13 in which the contents of the output
weight register is moved to the arithmetic scratch pad
register, the blank bit therein is replaced with a zero and
the we~ght register is addressed.
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` ` 1128~9
Then, in step 14L14 flag 2 is examinedr If it was
set, operation jumps to step 14L16. If flag 2 is not set,
operation proceeds to step 14L15 in which the register
- address is changed to the address of the price register.
In step 14~16, the data in the register which is
; addressed in either step 14L13 or 14L15 is multiplied by
the data in the output weight register to give a total
price.
This total price must now be rounded off to the proper
number of digits. In order to determine which digit to
round off, step 14L17 is performed which is a subroutine
operation for returning the address of the proper digit to
be rounded off. This subroutine is described in detail in
connection with Fig. 14Z.
Referring to the Total Price Roundoff Digit Search
Operation of Fig. 14Z, in step 14Zl, the digit address of
the digit which is rounded off under non-UK conditions is
first addressed in the result register. Then, in step 14Z2
the 30 lb. enable register is examined and if the 30 lb.
scale capacity has been selected, the address of step 14Zl
is decremented shifting the address to the round off position
for the 30 lb. scale.
~ iowever, if the 30 lb. scale capacity is not selected,
operation jumps directly to step l~Z4 in which the UK enable
7.5 register is examined. If the UK scale has been selected, the
address is again decxemented in step 14Z5 to the position
~hich is appropriate for rounding off for use in the UK. If
UK is not selected the address is correct.
This therefore provides, as stated in step 14Z6, the
proper round o~f address. This address is then loaded into
the accumulator and operation returns to the step in the
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l~ZI 3~79
main sequence of operations at which the total price
round off digit search operation was initiated.
Returning to Fig. 14L, the total price is then rounded
off using the address returned ~rom step 14L17 and a
S determination is made in step 14Ll9 whether the UK mode is
selected. If the UK mode is not selected, operation jumps
to step 14M5, no further round off being necessary. However,
if the UK mode is selected then a further round off must
be performed. Therefore, operation again advances to the
total price round off diyit search subroutine operation
XXIX at step l~L20.
The address returned in step 14L20 is then incremented
to the next most significant digit in step 14L21 and a 2 is
added to that digit with the carry being propagated. Then
at step 14L22 the total price round off digit search sub-
routine operation is performed and at step 14Ml the returned
address is incremented.
If the currently addressed digit is in the ran~e 5 to 9
inclusive, this indicates that the 1/2 legend should be
illuminated. Therefor~, in step 14M2 an 11 may be added
to that digit. If a carry is produced, then the digit was
in the stated range and therefore half-penca is desired.
Consequently, in step 14~13 the carry may be inspected to
determine if half-pence is desired. If it is, an 8 is
loaded to the accumulator or being written into the prepack
or half-pence registers 02S and 026. However, if half~pence
is not desired, a zero is loaded into the accumulator for
writing into the same registers in step 14M4.
Operation then proceeds to an over value check. At
step 14M5 the total price round off digit search subroutine
operation XXIX is again repeated. The lower 4 digits of
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the returned address axe complemented and added to 11
in order to form an address counter for performing the
over value check. Then, in step 14M7, a determination
is made whether 5 digit pricing is selected. If it is
S not, then in step 14M8 the check counter formed in step
14M6 is incremented so that the over value check will be
done for 4 digit pricing. However, if 5 digit pricing
is selected, operation jumps directly to step 14M9.
At step 14M9 the addressed digit and the more signi-
ficant digits of the total price are examined to determine
whether they are 0. If all are 0, then in step 14M9 the
total price is found not to be over value and operation
jumps to step 14M14. However, if a non-zero digit is
found, the total price is over value and in step 14M10 the
total price is blanked.
In step 14Mll, a determination is made whether the UK
scale is selected. If it is not, operation jumps directly
to step 14Ml9. However, if the UK scale is selected, then
in step 14M12 the prepack lamp registers are cleared.
If, in step 14M9, an over value did not exist, operation
advances to step 14M14 to prepare and move the computed
total price to the total price register. To do this the
total price round off digit search subroutine operation
XXIX is performed at step 14Ml~ and then at step 14M15 a
5 is added to tlle returned address so that the most signi-
ficant digit of the total pxice may ~e addressed. Then,
at step 14M16 a determination is made whether the UK scale
mode is selected. If it is, in step 14M17 the address is
incremented so that in step 14M18 the appropriate number
of total price digits are moved from the result register
to the total price register.
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Output
In the Output Operation XXI, the proper digits are
output to the GPKD 410 and displayed and the contents of
the lamp status flags are output to the lamp latches for
display.
In step 14Ml9, the output weight, price and total price
are moved to RAM registers 070 through 07F in the proper
sequence for output to the GPKD. Then, in step 14M20 a
determination is made whether 5 digit pricing is selec~ed.
If 5 digit pricing is selected, operation advances directly
to step 14M22 while if 5 digit pricing is not selected, then 4
digit pricing will be provided and in step 14M21 the most
significant digit of the price register is blanked.
Similarly, in step 14M22, a determination is made whether
5 digit total price is selected. If it is, operation j~ps
! lS directly to step 14N2 while if the 5 digit total price is not
selected, then operation goes to step 14Nl in which the most
significant digit of the total price is blanked.
Then, in step 14N2 a determination is again made whether
the UK mode is selected. If it is, the next most significant
digit in the total price is also ~lanked while i~ it is not
operation jumps directly to step 14N4.
Steps 14N4 through 14N12 operate to O-ltpUt the digits in
RAM register 070 through 07F to the GPKD for display~ Then,
in step 14N14, the CPIJ sends the KDN instructions to the GPKD
2S to turn on the display and display the digits which were output
to the GPKD.
Finally, in steps 14N15 through 14N18, the 7 lamp states
a~e output to the latch, decoder and ariver circuitry 56.
Print
In the print operation determina-tions are made whether
a print co~mand was entered, whether a print should be dis-
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abled because the weight is below the minimum established
for printing and what type of print is desired. The data
is then output to the printer and a print is performed if
the print command was entered. The printer is then reset.
Loo~ing now at the print operation XXII in more detail,
in step 14Nl9, the contents of the print command register
is written into the accumulator and the print command
register is cleared. ~lag 2 of the CPU 210 is then reset.
Then, in step 14N20 the contents of the accumulator is
examined to determine whether the print command was set. If
the print command was not set, then operation jumps to step
1401. However, if the print command was set, flag 2 of the
CPU 210 is set in step 14N21 to note that a print command
existsu Then, in step 1401 the find scale capacity subroutine
'5 operation XXV is performed and its returned data is used in
step 1402 to make a determination whether the weight is less
than 20 raw wei~ht increments. Then, in step 1403, the print
complete signal from the printer is input to the CPU 210
and examined in step 1404 to determine whether a character is
being printed.
If the printing is not complete, operation jumps to step
1408 in which flag 2 is reset in order to disable an initiation
of another print operation while a print operation is being
currently carried out. However, if printing is complete, a
'j determination i5 made in step 1405 whether the print inhibit
mode has been selected. If~it has not, operation jumps to
step 1~09. However, if the prlnt disable mode has been
- selected, a de-termination is made whether a print command
exists. If a print command does not exist, operation jumps
0 to step 1409. Howevex, if a print command does exist, a
determination is m~de whether the weight is less than 20 raw
_9~_
1128~79
.. .
weight increments. If the weight is not less than 20
raw weight increments, operation jumps to step 1409.
However, if the weight is less than 20 increments flag 2
is reset in order to disable a print. Then, in step 1409
a determination is made whether the Toledo Scale 300 printer
mode has been selected. If it has not, the output data is
written into RAM registers 070 through 07F in the proper
format for a 5 digit printer. However, if the 300 printer
s found in step 1409 to have been selected, operation
advances to step 14012 in which the data is loaded into the
same registers in proper format for the 300 printer.
After the data is loaded in the proper format, then in
step 14013 a determination is made whether the "by count"
mode is selected. If the "by count" mode is not selected,
operation jumps to step 14013 to begin the output of the data
! to the printer.
~owever, if the "by count" mode is selected, it is
desirable to replace all the digits in which a 0 appears with
a decimal point so that merely a series of dots are printed.
To do this, a loop formed by steps 14014 through 14018 looks
at each digit and if the digit is a 0 it is replaced with a
13 so that it will cause a decimal point to be printed. After
all digits are examined, then in step 1401~ a 0 is loaded to
the output register factor digit and the printer output is
~5 beyun.
To do this, step 14020 switches the printer clock and
printer reset lines illustrated in Fig. 6 to a low state
and the printer enable line to its high state.
Then, an output loop is formed in steps 14021 through
14P7 in which each digit to be ou~put and its appropriate
parity bit is output in se~uence. In step 14021 the integra~ox
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~lZ8~79
reset signal is written into the X register of the CPU to
maintain the analog to digital integrator circuit in its
reset condition. Then, in step 14021 the first digit from
the output RAM re~isters 14070 through 1407F is loaded into
the accumulator and in step 1402~ the output instruction,
with mnemonic DOA, is output to the GPKD and the digit is
thereby sent to the printer.
In step 14Pl, the output digit is used to address the
parity table and select the correct parity bit so that in
step 14P2 the parity bit is output to the printer. Then at
step 14P3 the printer clock line is strobed and held in the
strobe state for 0.4 milliseconds in step 14P4. The strobe
is removed in step 14P5. Then, after another 0.4 millisecond
delay in step 14P6 a determination is made in step 14P7
lS whether all of the digits have been output. If they have not,
operation loops back to state 021 to again pass through steps
14021 through 14P7 until all digits have finally been output
in this manner to the printer.
After all digits have been output, th~ printer enable
line o~ ~ig. 6 is switched to its low state in step 14P8 to
disable the printer and operation proceeds to st~p P9. ~t
s~tep 14P9 a determination is made whether a print command
exists. If it does not, operation jumps to step 14P15 in
which the printer is reset through the print reset line
illustrated in ~ig. 6.
However, if a print command is found to exist at step
; 14P9, the print command is output at step 14P10 on the print
command line illustrated in Fi~. 6. After a delay of 5
milliseconds in step 14Pll, the print complete line is input
to the CPU in step 14P12 and examined in step 14P13 to
determine whether the print is complete. If the print is
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l~Z8~79
incomplete, operation loops back to step 14P12 and continues
looping through steps 14Pl2 and 14P13 until the print is
found in step 14P13 to be complete. In step 14Pl4, the
print command is removed from the print command line and in
step 14P15 the printer is reset through its print reset line.
Keyboard
In the keyboard opexation XXIII, a determination is made
whether a key is entered and if so the entered key is
identified and stored in memory if conditions are appropriate.
For some of the operations called for by key depressions, the
operation also is performed.
Referrin~ to the diagram of the GPKD in Fig. ll, each
time a key is depressed, the code representing that key is
stored in the key buffer registers 1032. Then, whenever the
CPU outputs the proper instruction to the GPKD, the key codes
are input to the CPU.
The key codes comprise two parts as described in the
Rockwell literature. The first is a ~our bit word entitl~d
the strobe. The second is a four bit word entitled the return.
Returning to Fig. 14P, in step 14Pl6 the CPU 210 outputs
the mneumonic iCTS instruction which causes the GPKD to transfer
the strobe code to the CPU. Then, in step 14P17, the trans-
ferred strobe code can be examined to detel-mine whether a
key was entered. I a key was not entered, operation jumps
~2S to step 14Tl9 at the end of the keyboard operation. In
steps 14Tl9 aIld 14T~O, a determination is made whether the
verify key was the last key to have been depressed. If the
verify key was not the last key, operation loops back to
step 14A8. However, if the verify key was the last key to
have been depressed, operation proceeds to s~ep 14Pl8 in
which the keyboard strobe word is entered into register 0~7.
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1128~79
. ,
Then, in step 14Pl9 a mneumonic KTR instruction is output
from the CPU to the GP~D to cause the GPKD to return its
keyboard return data to the CPU.
As explained in the Rockwell literature, if the number
S of depressed keys exceeds the storage capacity of the GPKD,
then the most significant bit of the keyboard return word
will be switched from a 0 to a 1. Consequently, in step 14P20,
the keyboard return 4 bit word can be examined to determine
if such a keyboard error is present because all depressed ~eys
were ~ot stored in the GPKD. If such a keyboard error is
found, operation loops back to step 14A4 in which the CPU 210
outputs a KER instruction to the GPKD 410 which causes it to
be reset. If not keyboard error is present then the keyboard
return word is written into RAM memory 046.
Then in step 14P22, the keyboard strobe and return data
are examined. If a command key is found, operation jumps to
step 14Rll. However, if a command key is not found, the key
must have been a digit key and ther~fore operation proceeds to
step l~Rl.
In step 14Ri the digit timer is examined. If the digit
timer is still running, this means that the key was depressed
within the required time or accepting the depression of a
digit key. Therefore, operation may jump to step 14R3 in
~hich the digit is written into RAM memory. However, if
the digit timer is not running, then the entered digit must
be the first in a new series of digits so the price register
and the factor register are cleared in step 14R2. Then, in
step 14R3, a determination is made whether 5 digit pricing
is selected. If 5 digit pricing is selected, operation jumps
to step 14R6O If 5 digit pricing is not selected, ther 4
digit pricing must have been selec~edO Tnerefore, in step
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14R4, a determination is made whether the most significant
digit of the 4 digit price is a zero. If the most significant
digit is found in step 14R4 to be a non-zero digit, then all
th~ allowable digits have been entered and the digit just
input from the GPXD should be ignored. Therefore, operation
lvops back to the beginning of the keyboaxd operation XXIII
at step 14P16. ~owever, if the most significant digit of the
4 digit price is zero then operation jumps to step 14R7.
Similarly, if 5 digit pricing was found to have been selected
at step 14R3, then in step 14R6 the most significant digit of
the 5 digit price is examined to determine whether it is zero.
If this most significant digit is not zero, then the most
recently entered digit must be ignored and therefore operation
loops hac]c to step 14P16.
lf, however, operation advances to step 14R7, the most
recently entered digit is examined to determine whether it
is 0 to 9 inclusive. If it is not, one of these allowed
digits, it must be ignored and therefore operation loops back
to step 14P16. However, if it is an allowed digit, the new
digit is entered into the least significant digit of the price
register in step 14R8 and any other digits already entered
in the price register are shifted one position toward the
most significant digit. Then, in step 14R3 the digit timer
is set to its 11 state to set up a new time delay for
acceptance of another digit. Operation then jumps to step
14T17.
If in step 14P22 a command key rathex than a digit key
was found to have been depressed, then in step 14Rll the
stored key data is examined. If the verify key was not
depressed operation jumps to step 14~21 to determine whether
it was the per half key which was depressed.
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`` 1128~!7~
If, however, the verify key was depressed, then a KER
instruction is output from the CPU in step 14R12 in order
to reset the GPKD. Then, after a 50 millisecond time delay
in step 14R12, the verify test flag is examined. If the
verify test flag is set, then this detection of the verify
key should be ignored and operation loops back to step 14P16.
However, if the verify flag was not set, then in step 14R15
it is set and the contents of the verify mode flag is
~omplemented. Then, in step 14R16 the verify mode flag is
examined to determine whether it was clear.
If the verify mode flag was clear then a 15 is written
into the X register of the CPU 210 and the contents of X
register is unloaded into each 4 bit register at RAM addresses
070 through 07F. This is done so that upon the first depression
of the verify key all digits of the displays will be blanked.
However, if the verify mode flag was found not clear in step
14R16, an 8 is loaded into register X so that in step 14R17
all 8's will be loaded into the contents of RAM registers
070 through 07F. These 8's will then subsequently cause all
segments of the display registers to be illuminated.
In step 14Rl9, all the lamps are lo~ded with the register
X test digit and the digit timer is cleared. Then operation
loops back to step 14Ml9 so that the loaded digits can be
output for the verify test.
2S If, however, the` verify key was found in step 14Rll
not to have been depressed, then in step 14R21 determination
is made whether the per 1/2 key is depressed. If it is not,
operation jumps to step 14S5. However, if the per 1/2 key
is depressed, then in step 14R22 a determination is made
whether the "by count" mode has been selected. If it has
not been selected, operation jumps to step 14S3 in which a
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.
2 is loaded into the accumulator and operation jumps to
step 14S10.
If the "by count" mode was found selected in step 14R22,
then in step 14Sl the contents of the price register is moved
to the total price register and the price register is cleared.
Thereafter operation jumps to step 14T16.
If operation jumped to step 14S5 because the per 1/2
key was found in step 14R21 not to have been depressed, a
determination is made whether the per 1/4 key was depressed.
I~ it was not, operation jumps to step 14S13. However, if
the per 1/4 key was depressed, then in step 14S6 a determination
is made whether the "by count" mode was selected. If it was,
operation jumps to step 14T16. However, if the "by count"
mode was not selected, then in step 14S7 the find scale
capacity operation XXV is perormed.
In step 14S8 the returned data is examined to determine
whether a metric scale capacity has been selected. If it has,
operation ~umps to step 14T16. However, if a metric scale
has not been selected, a 4 is loaded into the accumulator in
step 14S9.
In step 14S10 the first bit o the factor flag is examined
to determine whether it is a 1 indicating that the ~actor
multiplication has already been done. If factoring is found
to have been done, operation jumps to step 14T16. However,
if factoring has not been done, the factor register is updated
with the 4 loaded in the accumulator in step 14S9 and the
setting of the first bit of the factor flag~
In step 14S13, a determination is made whether the print
key was depressed. If the print key was depressed, then in
3C step 14S14 the print command R~M register 027 is set and
operation continues to step 14S15. ~lowever, if the print
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. .
key was not selected, operation jumps directly to step
l~S15 in which a determination is made whether the tare
key was depressed. If the tare key was not depressed,
there are no more keys to check and therefore operation
~umps to step 14T16. ~owever, if the tare key was depressed,
then in step 14S16 a determination is made whether the
motion flag is set.
If the motion flag is found to be set, ~ndicating that
platte. motion exists, then a manual tare weight would be
erroneous and consequently should not be accepted. There-
ore, operation will jump to step 14T16. However, if the
motion flag is not set, the digit timer is checked to
determine if it was still running. If the di~it timer is
still running this indicates that the tare key was depressed
in sufficient time that it may be accepted as a keyboard
tare. Therefore, operation jumps to step 14S21 in which
the price register is eY~amined to det~rmine whether its
digits are all zeroes. If a non-zero di~it is found in the
price register then a keyboard tare nlust be intcndcd and
operation ~urnp~ to step l~Tl. ~lowev~r, if the price register
contains all zaroes, a det~rmination is madc in step l~S22
wheth~r the we.ight is cJr~at~r than or ec~ual to 10 incr~ments.
If the weicJht is greater than ox ecIual to 10 ~cale incrernents,
operation jumpC to step l~Tl~. Elo~ever, .if it is not c3reater
than 10 incrcrnents a tare entry is crroneolls ~ncl operation
loop-; back to step 1~5.
Referrillc3 back to step l~S17, if the di~it timer ~as not
still runnin~, an examination is made at step l~S18 of the
net flac~ to determine if th~ ~eighing scal~ is in the net
.,` rnoae. ~f it is alrcady in the net rnode, th~ tare ~ey
depr~csion should be i~noled ~nd o~eration jurnps to step l~T16.
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; - - llZ8~!79
However, if it is not in the net mode then the manual
tare flag is set at step 14Sl9 and operation jumps to
step 14T14.
Step 14Tl is entered from step 14S21 because it appears
that a keyboard tare was intended. The zero increment flag
is examined in step 14T1 to determine whether the scale is
within the auto zero increment. If it is not, operation
jumps to step 14T16. However, if it is an examination is
made to determine whether the weighing scale is in the net
mode at step 14T2. If it is already in the net mode no
further tare weight should be entered and operation jumps
to step 14T16. However, if it is not in the net mode, a
determination is made in step 14T2 whether a keyboard tare
is permitted.
If a keyboard tare is not permitted then operation jumps
to step 14T16. However, if keyboard tare is permitted then
operation advances to step 14T4 in which the find scale
capacity operation XXV is performed. The returned data is
then used to ch~ck the keyboard tare weight which is entered,
initially in the price register, to determine if it is in
a format acc~ptable as a tare weight. Therefore, i~ a 15
kilogram scale is selected, then in step 14T8 the least
significant digit of the price must be a 0 or a 5. If it is
not a 0 or a 5, the digits are merely left in the price re-
gister and operation jumps to step l~T16. If, however, the
; least significant digit is a 0 or a 5 and therefore is
acceptable operation advances to step l~Tll.
If the 30 lb. scale is selected then operation advancesdirectly from step 14T6 to step 14Tll in which the price
register is examined to determine whether there are 4 or
fewer digits. If there are more than 4 digits then there
'
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`~ - 1128~79
~ .
are too many and the data in the price register cannot
be accepted as tare weight data and therefore operation
jumps to step 14T16. However, if there are 4 or fewer
digits, then in step 14T12, the data in the price register
is examined to determine whether it is less than the scale
weight capacity. If it is not, it cannot be accepted as
a tare weight and therefore operation jumps to step 14T16.
~owever, if it is less than the scale capacity, operation
advances to step 14T13 in which the data in the price
register is moved to the tare register and the tare done
and net flags are set. Operation then advances to step
14T14 in which the price register, factor flag and digit
timer are cleared. Additionally, in step 14T14 the total
price is cleared if the weight is plus and blanked if
weight is minus. Then, .in step 14T15 the auto clear flag
is cleared.
In step 14T16, a 1 is loaded into the digit timer, in
step 14T17 the recompute flag is set and the verify mode
flag is cleared. Operation then loops back to step 14P16
to check for another key.
.` ~
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