Note: Descriptions are shown in the official language in which they were submitted.
This application is a Divisional of Canaciian application
- Serial Number 323,967, file~ March 22, 197g.
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The present lnvention relates to phase-sensltlve
detectlon apparatus and methods, belng more partlcularly
concerned wlth sampllng-type detectors.
Prlor sampling-type, phase sensitlve detectors
can be consldered as multipliers? providlng a dc output
corresponding to that obtainable from the product Or the
sampling signal and the signal to be detected. The rre-
quency response of such detectors ls the Fourier transrorm
of the sampling signal. An lmpulse sample gives an infinite
bandwidth because an impulse contalns all frequencies. A
pulse sample duration T gives a frequency response in the
form
sin x
x twhere x = r/rO and rO 2T )~
the same form as the ~ourier transform of such a pulse, which
is insensitive to even harmonics (~-21o, 4fo, etc.)~ a~d at-
tenuates the odd harmonics at, for example, a 20 db/decade
rate. A sine-wave sample, however, would give the best res
ponse, being immune to all harmon~cs; but it would require a -
multiplier circult which, for some applications, is beyond the
state Or the present art ln terms of required accuracy. Its
complexity would alsobe undersirable.
Approximations to sine-wave samplin~ have accord-
ing,l~ been proposed, in order to make a phase-sensitive
detector immune to 3rd, 5th and higher harmonlcs. One such
is clescribed, for example, ln ~nited States Letters Patent
No. 3,517,298, and in an artlcle by Peter Richman and Norm~n
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Walker cntltlcd "A New l~ast ~oupllng RMS-to-DC Converslon"
appearln~ ln the IEE~ Transactlons on Instrumentatlon and
Measurement, Vol. lM-20, No. 4, November, 1971, pp. 313-
319.
In accordance wlth the present lnventlon, however,
ln summary, the necesslty lor multlple swltches, wlth thelr
attendant complexity, is obviated through the concept of
maklng three (or more) successlve, half-wave measurements
(180 long) and adding thelr results ln a microprocessor
wlth appropriate welghlng factors. Instead of taklng the
analog sum of threee pulses 180 degrees in length and 46
apart, thls method uses three separate pulses ~or sets of
pulses) 180 in length which occur separately, one at a time,
but whose starting points in time (or phase), relative to
a continuous test signal, change by 45 increments; that is,
they mlght have starting polnts wlth respect to a fixed point
in tlme Or 0, 405 (or 360 + 45), and 810 (or 720 ~ 90).
The dlgltal results of measurements using such samples are
added digitally. Thus, this principle of using successive
pulses enables the obtaining of the same results as would be
obtained by adding pulses that overlap in time and, through
employing successive half-wave measurements, synthesize an
equlvalent of, or approximation to, a sine-wave sampling
waveform.
While Or more general utillty, as well, this
technique, when applied to systems such as impedance bridges
employing microprocessors in directly calculating impedance
values from measurements, has the particular rurther ad-
vantage Or lmprovlng the D-accuracy when slow measurement
rates are used. Such brldges are descrlbed, for example,
ln my artlcle entitled "Analog Tests: the microprocessor
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~cores", appearing in the IEEE Spectrum, April, 1977, pp.
36-40; in an article entitled "MPU-Based, Easy-To-Use, Lower
Cost RLC Component Test System, Evaluation Engineering, November/
December, 1976, p. 22; and in Canadian Patent 1,085,460 which
issued September 9, 1980.
An object of the present invention, accordingly, is
to provide a new and improved method of and apparatus for
sampling, phase-sensitive detection embodying approximations
to sine-wave sampling and obviating prior disadvantages,
including those above-described.
A further object is to provide such a novel phase-
sensitive detection technique and apparatus ~articularly adapted
for impedance bridges employing microprocessors for
calculating impedance values from measurements effected in the
circuits.
Other and further objects will be explained hereinafter
and are more particularly delineated in the appended claims.
In summary, the invention embracing a phase-sensitive
dual-slope detector apparatus having, in combination, dual-.slope
detection means responsive to an input AC signal, means for
generating in spaced successive time intervals groups of burst
pulses and for applying the same to the detection means to effect
forward-slope integration therein commencing with the start of
each such time interval; means for initiating the commencement
of the reverse slope operation of the dual slope detection means
during each of the spaced successive time intervals and for
thereupon counting impulses for the duration of such reverse
slope to digitize the analog voltage measurement represented
thereby, in order to provide a plurality of digitized quantities
representing measurements during the reverse slope of each of
csm/ ~
~25~
~he spaced sucoessive time intervals; means f~r storing t,he di,gitiæd
qu~ntities; and means for.adding the digitized quantities.
. . .
The invention also contemplates a
method of phase-sensitive dual-slope detection of an input AC
- signal, comprising the steps of providing in spaced successive
time intervals groups of burst pulses, applying the same to ~
detection means, in order to effect forward-slope integration
therein commencing with the start of each such time interval,
providing impuls`es to be counted, initiating the commencement
10 ~ of the reverse slope operation of. dual slope detection during'
each of the spaced successive time intervals and thereupon
. counting the impulses for the duration of each reverse slope
- thereby digitizing an analog voltage measurement of.the AC signal
in order'to provide plurality of digitized quantities representing
measurements of the input AC signal during the reverse slope
of each of spaced successive time intervals, storing the
. .
, digitized quantities and adding the digitized quantities. ~,
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s
,- 3a -
me invention will ncw be described with reference to the
accompanying drawings, Fig. l of which is a circuit diagram of a preferred
embodiment of the inventions employing the method thereof;
Figs. 2a through e are waveforms explanatory of the voltages at
different positions of the circuit of Fig. l; and
Figs. 3a through e are expanded waveforms of a part of the
sa~pling intervals shown in Figs. 2a through e.
While th~ method of dual-slope phase-sensitive detection, with
sucoe ssive measurement sine-wave sampling approximation herein disclosed
is m~re broadly applicable, it will be described for illustrative Purposed
in connection with a preferred application to impedan oe or similar
~easurement instruments embodying calc~ator apparatus, such as a
microprocessor, for the purpose of calculating impedance or other values
from a series of measurements obtained in the instrument as described,
for example, in my issued Canadian Patent 1,085,460 and in my previously
mentioned articles.
Referring to Fig. l, the invention has been illustrated as embodying
a dual-slope phase-sensitive detector the a~plifier 16 of which is shown
shunted by an integrating or averaging capacitor C which, in turn, is
schematically illustrated as shunted by a zeroing FET s~itch, labelled
"zero"
me input AC signal is applied through the input resistor RA
and a further ~T or similar switch BST (meaning a pulse burst control)
to one input terminal (-) of the a~plifier 16. The other input of the
amplifier 16 is shGwn grounded. A DC referen oe voltage EB is obtained across a
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~ener-dlode-shunted reslstor RD and ls applled through a
re~erence reslstor RB, under the control of a ~urther FET
or slmllar switchlng devlce MSR, to the (-) lnput termlnal
of the ampllfier 16 recelving the AC lnput signal. The
symbol MSR represents that this FET controls the measurlng
intervals that are to convert the analog slgnals lnto
dlgltal signals, correspondlng to successive measurements
to be effected ln the system. The digital conversion is
effected by having the MSR signal also applied to a gate,
labelled "AND GATE", into which consistent high-frequency
pulse traln signals fHF are applied.
This gate receiving the MSR and fHF pulses (such
as 25 MHz), is closed by the output Eo of the ampllfier
16 as applied through a comparator 17 that determines
whether the output is above or below ground. When the gate
is closed, the measurement period is terminated and this
stops the count in the COUNTER. After each measurement
period, the resulting count is, therefore, stored in a memory, so
labelled, which may be part of a microprocessor, for exam-
ple, with successive stored counts Nl, N2, N3, etc., cor-
respondlng to successive measurements, thereafter appro-
prlately added and displayed as lndicated. As hereinafter
explained, the display referred to ls the dlsplay Or but
one component o~ phase of the lnput voltage as thus far
illustrated.
In an actual appllcatlon ror impedance measure-
ment, ~or example, several components (at least 2 phase
components) would be requlred to obtain a calculated complex
lmpedance. Whlle only one such voltag,e measurement ls shown
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ln Fig. 1, thls ls ror lllustratlon, and lt ls deemed
surrlclent to explaln the prlnclples o~ the lnventlon ln
the most slmple rorm. Further lnformatlon on the addltlon-
al measurements ls contalned ln my sald artlcles and co-
pendlng appllcatlon, and ls not essentlal to the novel
reatures Or thls present lnvention.
~ eferrlng to Fig. 2, waveforms explanatory Or the
operation of the system of Fig. 1 are presented. Fig. 2a
represents the AC lnput signal; Fig. 2b, the burst pulses
(BST), shown as in pairs in this example; Fig. 2c, the measure-
ment gatlng pulses (MSR), which determine the measurement in-
tervals tl, t2 and t3 or counts Nl, N2, N3, etc.; Fig 2d,
the zeroing pulses to clear the integrator capacitor C; and
Flg. 2e, representing the dual-slope output voltage Eo
from the amplifler 16.
As shown in this example, two bursts of BST
pulses (Fig. 2b), each Or substantially 180 phase and
corresponding to the fundamentals of the AC input signal
Or Fig. 2a, are shown occuring during the first and second
posltive half cycles of the input signal. It is, of course,
to be understood that any other starting phase could be
used. The second set Or burst pulses BST is similarly
180 ln duration and is shown occuring in Fig. 2b commen-
clng with a polnt 45 delayed in phase from that Or the
rirst palr Or burst pulses; and the third set Or burst pulses
ls shown advanced another 45 wlth respect to the first
group Or burst pulses.
In Flg. 2c, the measurement periods are illustra-
ted by the counts Nl, N2, and N3, corresponding to the counter `
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accumulatlons during the reverse-slope perlods Rl, R2,and
X3 in the output waverorm E Or Flg. 2e. The leadlng edge
slopes Sl, S2, and S3 Or ~lg. 2e represent the analog re-
sultant voltages from the efrectlve sampllng o~ the AC
input signal o~ Flg. 2a by the sets,or groups, Or burst
pulses BST, ~lg. 2b.
Thus, when the rirst count Nl is fed from the
counter to the memory, following the completion Or the
measurement interval Nl Or Fig. 2c, it ls stored, and
the ~ero pulse Or Fig. 2d is thereupon apDlled to the coun-
ter. This same zeroing serves also to terminate the reverse
slopes Rl, R2, and R3.
By the three successive lntegrating measurement
samples, each occuring over measurement tlme intervals of
180 and each successively 45 phase-displaced,
the intergrator measurements of the input signal have been
converted into the respectlve digital numbers Nl, N2, and
N3. The numbers are added in the adder,and, with appro-
priate weighting factors,enable obtaining a measurement Or
the rundamental component Or voltage--in this case Or one
phase Or the input signal. Through the overall effective
approxlmate sine-wave sampling efrected by this procedure,
the advantage is attained that the displayed or otherwise
utillzed measurement Or such fundamental component Or the
voltaee Or the input slgnal will be lmmune at least to the
thlrd and flrth harmonics. The same process can be applied
to eliminate other harmonics, as well, which would require
more pulsesat di~ferent relative phase angles.
This operation is thus distin~ulshed from the
step-waverorm approxlmatlons to the sine-wave samplln~ Or the
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~Z91~6-
priGr art, such as the before-mentloned ~lchman technlque.
It does not employ the repetltlve generatlon Or step-
sampllng waveforms, as ln the prlor art multlpller swltch-
lng systems, and it embodles converslons of the successlve
lntegrated slgnal measurements lnto the dlgltal numbers
followlng each measurement. Additlonally, the present ln- -
ventlon ls partlcularly adapted for dual-slope phase-detec-
tlon, and further utlllzes a plurallty Or repetltive mea-
surement lntervals in successlve groups, with the measure-
ment periods Or each successlve groupp~ase-displaced; ln
the example glven, by 45 from the precedlng group. As
a result Or these marked dlfrerences, the number of re-
quired circuit components, particularly signal switches,
is slgnlricantly reduced; and the digltal conversion is
madein essentially one operation.
Turning, now, to a more detailed description of
the above-described measurements, reference may be made
to Fig. 3, wherein Fig. 3a illustrates a typical output
voltage Eo similar to the third measurement of Fig. 2e;
Flg. 3b, the AC input signal; Fig. 3c, the corresponding
BST waveforms; Flg. 3d, the MSR waveform; and Fig. 3e, the
CMP or comparator output.
The goi~g-posltlve Or the burst signals BST,
Flg. 2c, causes the BST-FET (Fig. 1) to open, starting
; the current rlow through the reslstor lnput RA which is
accumulated in integrator capacitor C, and changlng the
output voltage Eo to a negatlve lnput slgnal, thereby caus-
lng the lntegrator output to go posltlve, as shown. Thoup,h
the signal,Flg. 2b, ls delayed from the burst and starts
. ~ " .,
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as an lnltlal negatlve output,the lntcgratcd total be-
comes posltlve. The second BST pulse doubles the out~
put voltage Eo ~ts at S3, Flg. 2a, to thc total value Or
the volta~e given by the rormula ~o the rlght ln Fle.
2a. The MSR slgnal ls turned on,allowlng the DC current
to rlow through ~B and causlng the output voltage to de-
crease llnearly on the reverse slope R3 until it has
reached zero. Voltages o~ the operatlon are stopped, as
berore stated, by the output Or the comparator 17. Since
the voltage golng up must equal that going down, time in-
terval t3, durlng which the counter accumulates count N3,
Pig. 2d, is a measure Or the AC in phase with the burst
pulses. This time interval t3 ls converted into a digi- -
tal number, using the gate and counter as previously des- -
cribed.
In connection with the application of the tech-
t;tlque Or the present inventlon to impedance measurements
and the like, a system using elemental circuits Or the type
shown ln Flg. 1 may be employed with rour sets Or measure-
mentD; speclfically, two sets Or measurements with one sig-
nal proportional to the voltage and another unknown and
other sets Or measurements with voltages corresponding to
the current Or the unknown. The two measurements Or each
Or these signals give complements Or voltage 90 apart rrom
each other. From these four quantities, the complex value
lmpedance Or the unknown mav be calculated ir the phase
Or the current ls known, as discussed ln my said articles
and copending ~a~ent.
In such an appllcatlon, the system Or Fig. 1 has
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becn applled ror measurements wlth an AC lnput slgnal
Or 120 ~IZ usln~ two pulses ln each BST ~roup. The total
number Or tlmes ror two completecycles ls equal to 1/60
a second, thus maklng the measurement lmmune to plckup
at the 60 Hæ power llne rrequency. It was also applied
ror tests at 1020 Hz whlch used seventeen pulses ln each
pulse train (BST), so that, agaln, the total time was 1/60
second. Ir only one measurement ls made, lnstead Or three,
ror each Or the 90 rererences requlred, the even harmonlcs
are thus rejected completely, but the odd harmonics (thlrd,
rlrth, etc.) will only decrease by a factor equal to their
number; ror example, the thlrd harmonic has 1/3 the errect
upon the rundamental with the three measurements as shown
ln Fig. 2. The thlrd and rirth harmonlcs are subsequently
totally re~ected.
Appropriate weighting, as explained by Richman,
supra, ls requlred to get this re~ection. In connection
wlth the embodiments Or the present invention, as explained
in connection with Figs. 1 and 2, this would be ~ Nl + N2 +N3,
withthe appropriate common proportional factor both ways.
As before stated, Or course, the dual-slope phase
detection technique Or the invention is applicable in other
types Or systems, also, and rurther modifications will occur
to those skllled in this art, all such being considered to
rall wlthin the spirlt and scope Or the invention as derined
ln the appended claims.
What ls claimed is:
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