Note: Descriptions are shown in the official language in which they were submitted.
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The invention relates to digital instrumentation
industry, and more particularly to apparatus dealing with
digital-analog conversion of data.
The invention is suitable for use with analog-
digital converters, measuring information systems, and with
apparatus to display data on CRT's with digital scanning
of the beam.
Known in the art are digital-analog converters
for generating linearly varying magnitudes (cf. the book
by V. B. Smolow et al entitled "Semiconductor Encoding and
Decoding Converters", "Energya" Publishers, Leningrad, 1967).
These digital-analog converters are based on a device which
is operated to add the reference magnitudes proportional to
the weights of the digits of a conventional binary code
subject to digital-analog conversion, and a plurality of
switches which control the selection of respective reference
magnitudes and have their outputs coupled to respective
inputs of the reference magnitude adder. An input codeword
is delivered, for example, from a pulse counter having its
outputs coupled to the inputs of the switches. The pulse
counter may utiliæe a conventional binary code.
The described digital-analog converters are dis-
advantageous since they feature a low quality of transients
taking place at a point in time when adjacent code combina-
tions are changed (for example, a code combination OIl~
is replaced with a code combination 100,...,0) due to the
fact that many switches must be switched over for the purpose
at a time. These transients, therefore, result in a powerful
j surge of current of voltage at the output of such digital-
analog converter.
It is an object of the invention to provide for
better quality of a transient occurred in a digital-analog
converter during the changing of adjacent code combinations
by virtue of a synchronous control of the transient and by
diminishing the number of switches to be switched over
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simultaneously.
There is disclosed a digital-analog converter
comprising a reference value adder having its multidigit
input coupled to a multidigit output of a switch unit,
which digital-analog converter comprises, according to the
inv~ntion, a Fibonacci p-code convolution unit having its
multidigit output coupled to a multidigit input of the
switch unit, the Fibonacci p-code convolution unit being
provided with n stages, each such stage being related to
the ith bit position of a Fibonacci p-code lying between
the first and (n-2)th bit position of the Fibonacci p-code
and being provided with a flip-flop, an AND gate and an
OR gate, the stage corresponding to the low-order, zeroth,
bit position of the Fibonacci p-code being provided with a
flip~flop and an OR gate, the stage corresponding to the
high-order, (n - l)th, bit position of the Fibonacci p-code
being provided with a flip-flop and an AMD gate, the flip-
flop of the stage of the .ith bit position, lying between
the first and (n-2)th bit positions, having its set and
reset inputs coupled, respectively, to the output of a
respective A~D gate and to the output of a respective OR
gate, the flip-flop of the stage of the low-order, zeroth,
bit position having its reset input coupled to the output
of a respective OR gate, and having its set input used as
a counting input of the digital-analog converter, the flip-
flop of the stage of the high-order, (n - l)th, bit position
having its set input coupled to the output of a respective
AND gate, a plurality of the set outputs of the flip-flops
of all the stages being the multidigit output of the
Fibonacci p-code convolution unit, first and secGnd inputs
of the AND gate of the stage of the ith bit position, lying
between the æeroth and (n - 2)th bit positions, being
coupled, respectively, to the output of the AND gate of the
ti + 1)th stage and to the output of the AND gate of the
(i + p + 1)th stage, first and second inputs of the AND
,
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gate of the stage of the ith bit position, lying between
the first and (n - l)th bit positions, ~eing coupled,
respectively, to the reset output of the flip-flop of the
same stage and to the set output of the flip-flop of the
(i - 1)th stage, a third input of the AND gate of the ith
stage, beginning with the (p ~ l)th bit position, being
coupled to the set output of the flip-flop of the
(i - p - l)th stage, the remaining inputs o~ all the AND
gates being joined together to constitute a clock input of
the digital-analog converter, where n is the length of the
Fibonacci p-code and i = 0,1,2,...,n-1.
The advantage of the disclosed digital-analog
converter is that a transient occurred in it during pulse
counting is broken down into a n~ber of local transients
each having a lower power, said local transients being
related to at least three bit positions at a time. In the
digital-analog converter of the invention, it is possible
to control the duration of a transient and to obtain a more
simple procedure for functional check of the converter.
The invention will now be described, by way of
example, with reference to the accompanying drawing, which
shows a functional diagram of a digital-analog converter
used for generating linearly varying values, according to
the invention.
The digital-analog converter of the invention
comprises a reference value adder 1 having an output 2 used
as the output of the converter.
The reference values, for example, reference
currents, are chosen in a proportion to respective Fibonacci
p~numbers. This means that the weight of the ith bit posi-
tion is proportional to the ith Fibonacci p-number defined
according to a recurrence relationship as follows:
r at i ~ 0
yp(i) = ~ 1 at i = 0 (1)
p(i ~ p(i - p - 1) at i > 0
~r
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~'," '' ' '" ' ': ~
' ~ . ' ~' ' ' ' :
. ' '
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i ' ' ~; ' '~ ' :
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where p is the given number of natural numbers.
The digital-analog converter of the invention
further comprises a switch unit 3 (incorporating, for
example, transistor switches), said switches of the switch
unit 3 being equal in number to the bit positions of the
Fibonacci p-code. The outputs of the switches of the
switch unit 3 are used to constitute a multidigit output
of the switch unit 3 and are coupled to a multidigit input
of the reference value adder 1~ The digital-analog conver-
ter further comprises a Fibonacci p-code convolution unit 4
which is operated to perform a step-by-step conversion of
the original p-code of a number to other code combinations
representing the same number. The multidigit output of the
Fibonacci p-code convolution unit 4 is coupled to a multi-
digit input of the switch unit 3. A first input of the
Fibonacci p-code convolution unit 4 serves as a clock input
S of the digital-analog converter to synchronize transients,
whereas a second input of the Fibonacci p-code convolution
unit 4 is a counting input 6 of the digital-analog converter
to receive count pulses.
In the case of an arbitrary p, the Fibonacci
p-code convolution unit 4 comprises n stages 7 (with n = 6
in the embodiment) equal in number to the bit positions in
the Fibonacci p-code. Each ith stage 7 corresponds to the
ith bit position of the Fibonacci p-code and comprises a
flip-flop 8 whose set input 9 is coupled to the ith bit
position of the multidigit input of the switch unit 3. Note
that i = 0,1,2,... , n - 1. Each stage 7 related to the bit -
positions lying between the first and (n - l)th, fifth, bit
positions incorporates an AND ~ate 10 whose output is
coupled to a set input 11 of the flip-flop 8. A first input
of the ~D gate 10 coupled to a reset output 12 of the flip-
flop 8. In addition, each stage 7 correspondin~ to the bit
positions lying in a range from 0 to n - 2 comprises an OR
gate 13. The output of the OR gate 13 of each such stage 7
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is coupled to a reset input 14 of the flip-flop 8 of the
same stage 7. The following connections are established
between the stages 7. A first input of the OR gate 13 of
the stage 7 of the ith bit position (with i equal, for
example, to 2) is coupled to the output of the AND gate 10
o~ the stage 7 of the (i ~ l)th, third, bit position,
while a second input of the same gate 7 is coupled to the
output of the AND gate 10 of the stage 7 of the (i ~ p + l)th,
fourth, bit position since p = 1 in this case. A second
input of the AND gate 10 of the stage 7 of the ith, second,
bit position is coupled to the set output 9 of the flip-flop
8 of the stage 7 of the (i - l)th, first, bit position, the
next input of the A~D gate 10 of the stage 7 of the ith,
second, bit position is coupled to the set output 9 of the
flip-flop 8 of the stage 7 of the (i - p - l)th, zeroth, bit
position, and the remaining inputs of all the AMD gates 10
are joined together to constitute the clock input 5 of the
digital-analog converter which receives clock signals for
tr n t
a slen s.
The set input 11 of the flip-flop 8 of the stage 7
of the low-order, zeroth, bit position is the counting input
6 of the digital analog converter which receives count
pulses.
The operation of the digital-analog converter of :
the invention (with p=l) is as follows~ Count pulses are
applied to the counting input 6 of the digital-analog con-
verter. The Fibonacci p-code convolution unit 4 operates
to convert a train of count pulses to a respective Fibonacci
p-code which appears at the multidigit output of the
Fibonacci p-code convolution unit 4 and activates respective
switches of the switch unit 3. These switches, in turn,
select the reference elements in the reference value adder
1 having their values proportional to respective Fi~onacci
p-numbers. As a result, the outpùt 2 of the reference value
adder 1 provides an analog value proportional to the number
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of pulses, N, applied to the counting input 6.
Within a time interval between two consecutive,
for example, first and second, count pulses, clock pulses
are applied to the cloc~ input 5 to allow ~or a sequential
convexsion (convolution) of the original p-code of a natural
number to other code combinations of the same number. In
this case, the output 2 provides the same analog value
corresponding to the ori~inal p-code and selected previously
under the action of the initial count pulse.
Given below is a detailed description of the
Fibonacci p-code convolution unit 4. Before the operation
commences, the flip-flops 8 of all the stages 7 are kept
in the 0 state. As a result, enable signals (logic l's)
available from the reset outputs 12 of the flip-flops 8 are
applied to`the first inputs of the A~D gates 10 while disable
signals (logic O's) are applied to the second and third
inputs of the AND gates 10. The first count pulse coming to
the counting input 6 causes the flip-flop 8 of the stage 7
of the zeroth bit position to take up the 1 state, with -the
result that the following codeword is stored in the Fibonacci
p-code convolution unit 4:
5 4 3 2 1 0 - nos. of bit positions of Fibonacci l-code
N=l 0 0 0 0 0 1 - codeword.
In the reference value adder 1, the reference value
of the zeroth bit position is selected, ~p(0)=1, and the
output 2 provides the first component of a linearly varying
value proportional to N=l.
When a 1 is placed in the flip-flop 8 of the stage
7 of the zeroth bit position, an enable signal (logic 1)
produced at the set output of that flip-flop 8 is delivered
to the second input of the AND gate 10 of the stage 7 of the
first bit position.
A clock signal to synchronize a transient is a
train of short clock pulses having a duration equal to the
duration of the transient occurred in the AND gate 10. The
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time interval between the clock pulses equals the duration
of the transient occurred in the digital-analoy converter
during the switching-on/switching-off of any switch. Note
that the first clock pulse is applied to the clock input 5,
with a count pulse delivered to the counting input 6, after
a time interval equal to the duration of the transient in
the digital-analog converter occurred during the switching-
on of the switch of the zeroth b,it position. The first
clock pulse applied to the input of the AND gate 10 of the
stage 7 of the ~irst bit position causes the appearance of a
logic 1 at the output of this AND gate 10 with the result
that the flip-flop 8 of the stage 7 of the first bit posi-
tion takes up the 1 state. That logic 1 comes through the
OR gate 13 of the stage 7 of the zeroth bit position and
causes the flip-flop 8 of the stage 7 of the zeroth bit
position to take up the 0 state~ ~s a result, the codeword
in the Fibonacci p-code convolution unit 1 assumes the
following value:
5 4 3 2 1 0 ~ nos. of bit positions of Fibonacci l-code
0 0 0 0 1 0 - codeword.
This codeword also represents the,number 1. In
the digital-analog converter, a transient takes place due to
simultaneous switching-on of the flip-flop 8 of the stage 7
of the first bit position and switching off of the flip-
flop 8 of the stage 7 of the zeroth bit position. After the
transient has been tenminated, the output 2 produces again a
linearly varying value proportional to N=l.
The second count pulse causes the flip-flop 8 of
the stage 7 of the ~eroth bit position to take up the 1
state with the result that the following codeword is placed
in the Fibonacci p-code convolution unit 4: -
5 4 3 ~ 1 G - nos. of bit positions of Fibonacci l-code
0 0 0 0 1 1 - codeword.
In the reference value adder 1, the reference
value of the zeroth bit position is selected and the output
~L1372~8
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-- 8 --
2 produces the second component of a linearly varying value
proportional to N=2.
Enable signals therefore appear at the first,
second and third inputs of the AND gate 10 of the stage 7
of the second bit position. The appearance of a clock
pulse at the cloc]c input 5 causes the production of a logic
1 at the output of that AND gate 10. This logic 1 causes
the flip-flop 8 of the stage 7 of the second bit position
to take up the 1 state and also causes, via the OR gates 13
of the stages 7 of the first and zeroth bit positions, the
flip-flops 8 of these stages 7 to take up the O state,
thereby resulting in a codeword as follows:
5 4 3 2 1 0 - nos. of bit positions of Fibonacci l-code
O O O 1 0 0 - codeword.
This codeword represents the Fibonacci l-code of
the number ~ equal to 2. In the digital-analog converter,
a transient takes place due to simultaneous switching-on of
the flip flop 8 of the stage 7 of the second bit position
and switching-off of the flip-flops 8 of the stages 7 of the
first and zeroth bit positions. After this transient has
been terminated, a linearly varying value proportional to
~=2 appears at the output 2.
After the seventh count pulse and all the clock
pulses which follow it, a static state of the Fibonacci
p-code convolution unit 4 is as follows:
5 4 3 2 1 0 - nos. of bit positions
O 1 0 1 0 0 - codeword.
This condition corresponds to the Fibonacci l-code
of the number 7~ In this case, an analog value proportional
to the natural number 7 appears at the output 2.
With the eighth count pulse available, the first
intermediate state which the Fibonacci p-code convolution
unit 4 assumes is as follows:
5 4 3 2 1 0 - nos. of bit positions
O 1 0 1 0 1 - codeword.
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This condition corresponds to the Fibonacci l-code
of the natural number 8. With the first clock pulse avail-
able, the Fibonacci p-code convolution unit ~ assumes a new
intermediate state as follows:
5 4 3 2 1 0 - nos~ of bit positions
0 1 0 1 1 0 - codeword.
This condition corresponds to the second Fibonacci
l-code of t~e natural number 8. When subsequent count pulses
arrive, the operational steps are repeated.
The advantage of the digital-analog converter of
the invention is that a transient occurred during pulse
counting is broken down into a number of local transients
belonging to not more than three bit positions, ith, (i - l)th
and (i - p - l)th, at a time~ In addition, it is possible
to control the duration of the transient using clock pulses,
with the result that the quality of the transient is enhanced
and its power is decreased.
In the digital-analog converter of the invention,
the appearance of any count pulse causes the switching-on of
a single, zeroth, bit position only and the output of the
converter immediately produces a static value corresponding
to N, with a concurrent production of a transient. This
feature also tends to improve the transient quality and is
considered to be important in the case of analog-digital
converters with feedback as used in scanning-type digital
measuring systems wherein the digital-analog converter is
coupled to the input of a comparator which could produce a
false response to a transient.
- Moreover, functional check of the digital-analog
converter is a simple procedure as follows. After the
current count pulse has been delivered and an output
analog value corresponding to N has been selected, it is
sufficient to check the output value for constancy each
time a clock pulse is applied. A non~constancy of that
value may only be du~ to the fact that the weights of the
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individual bit positions in the digital-analog converter
do not obey the recurrence relationship (1)~ This means
that the latter is used as a specific "mathematical
checker". If a large deviation from the constancy takes
place, then trouble in the digital-analog converter is
likely to occur.
The implementation of the transient in which the
weights of bit positions are subject to a convolution
procedure (without changing the numerical equivalent of N)
as follows:
( O 1 0 1 0 1 0 1 1
) O 1 0 1 0 1 1~ 0 0
N = ~ O 1 ~0 1 1 0 0 0 0
0 1 1 0 0 0 0 0 0
~ . .
l O O O O O O O O
may be treated as an averaging of the output analog value,
which provides for a higher accuracy of the digital-analog
converter of the invention.
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