Note: Descriptions are shown in the official language in which they were submitted.
' . CROSS-REFERENCE TO RELATED PATENTS
- The present invention is closely related to U.S.
Patent 4,096,395 issued June 20, 1978 to George F. Bogel
and Robert M. Oates entitled "Automatic Transfer Control
Device And Yoltage Sensor" and U.S. Patent 4,090,090 issued
May 16, 1978 to Paul M. Johnston entitled "Automatic Tra~sfer
Control Device And Frequency Sensor". Both of the above-
mentioned U.S. patents are assigned to the assignee of the
present invention.
BACKGROUND OF THE INVENTION
Field of the Invention:
The invention relates in general to electrical
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113~564 46,672
apparatus and, more particularly, to automatic transfer
control devlces for selectively energizlng an electrical
distrlbution system from a plurallty of electrical power
sources.
Description of the Prior Art:
In supplying electrical power to lndustrlal and
commercial fac~lltles, lt is often desirable to provlde
alternate sources of electrical power to insure continulty
of service. So~etlmes these sources may comprlse separate
feeder clrcuits ~rom the electric utility company. In
other situations one or more dlesel generators may be pro-
vided as alternate sources. Means must be provlded to
switch the dlstribution system between the alternate sources,
and it is often desirable to provide thl~ switching capabl-
lity as an automatic functlon. Thus, lf the primary power
source should fail, the transfer control device will auto-
matically swltch the distributlon system from the primary
to the alternate source. In order to provide the deslred
features for each indlvidual ins~allation many options are
often specifled, including automatic retransfer when the
prlmary source once agaln returns to normal, tlme delay
before switching, lnterlocking to prevent the load from
being connected on a transient basis to both sources at the
same tlme, automatlc startup of diesel generators, dlvl~lon
of the load between the sources and others.
In provldlng an automat~c transfer control devlce
for a speciflc application, it was usually necessary to
engineer a custom design for each application, selecting
various relays and components to provide the desired features.
Prlor art automatlc transfer control devices have sometimes
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113~564 46,672
provided a certain degree of flexibility, but have often
requlred auxiliary relays and components. In addition,
prior art automatic control transfer devices employing
electromechanical logic components have required substan-
tial amounts of power. It would be desirable to provide
an automatic transfer control device having sufficient
flexiblity to handle a wide variety of transfer control
applications including both two-breaker schemes and three-
breaker schemes having two sources and two loads.
In addition, in prior art devices it was often
dlfficult to verify the operability of the devlce without
initlating a transfer. It would therefore be desirable to
provide an automatic transfer control device including means
for testing the device wlthout actually inltiating trans~er.
SUMMARY OF THE INVENTION
In accordance with the princlples of the present
invention, there i8 provided an automatic transfer control
- device for generating signals to cause associated clrcult
interrupters to selectively energize an electrical distrlbu-
tion network ~rom a plurality o~ electrical power sources.
The device includes means for sensing electrical condltlons
on each of the electrical power sources, a plurality of
means for generating output control signals to operate
associated circuit interrupters, and electronic dlgital
logic means for actlvating the signal generating means ln
response to electrical conditions detected by the sensing
means. Means are also provided for programmlng the logic
means to cause the signal generating means to selectlvely
produce any of a predetermined set of output control signal
comblnatlons in response to a predetermined set Or electrical
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conditlons upon the electrical power sources. Means are
also provlded for supplylng the status of associated clrcuit
interrupters to the logic means ln order to provide lockout
and interlocking functions.
Each of the control slgnal generatlng means
includes an indicator li~ht for contlnuously indlcating
the control signal belng supplied from the electronic dlgi-
tal logic means to the slgnal generating means. A mode
selector switch i8 provlded to energize the control device
in either manual, automatic, or live test mode. In the
live test mode, the output control signal generating means
are defeated, allowlng a test button to simulate a failure
upon elther of the electrical power ~ources, causing the
automatic transfer control device to inltiate a transfer
operation which i5 complete except for actually commandlng
the assoclated circult interrupters to transfer the dlstri-
bution system from one source to another. The logic slgnal~
provided to the output control slgnal generating means durlng
the test function are shown by the indlcator llght~, but
wlth a flashing rather than a contlnuous lndicatlon to show
that the control device is in ~he test mode.
BRIEF DESCRIPTION OF THE DRAWINGS
The novel and dlstinctlve features of the inven-
tion as set forth wi~h particularity in the appended clalms.
The invention, together with further obJects and advantages
thereof, may be best understood, however, by reference to
the following description and accompanying drawlngs, 1n
the several flgures of which llke reference characters iden-
tify llke elements, and in which:
Figure l is a block d~agram of an electrical dls-
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113~564 46,672
tribution system having two alternate sources of electrical
power and utilizing two circuit interrupters to supply a
slngle load;
Fig. 2 is a blcck dlagram of an electrical dis-
tribution system employing two alternate sources of elec-
trical power and three circuit interrupters to ~upply two
loads;
Fig. 3A is a schematic drawing showing external
connections to an automatic transfer control dev~ce employ-
ing the principles o~ the present lnvention;
Fig. 3B is a functional schematic drawing show-
ing signal flo~ through the devcie of Flg. 3A;
Fig. 3C is a detall functional schematic drawing
showing the signal flow through the voltage, frequency, and
timing logic o~ the devlce shown ln Figs. 3A and 3~;
Flg. 4 is a schematic diagram of the power supply
circultry of the automatlc transfer control device of
Flg. 3B;
Fig. 5 is a schematlc dlagram of the voltage sen-
sing loglc circuitry of the device of Fig. 3B;
Fig. 6 ls a phasor diagram of the voltages sen~ed
by the circuitry of Fig. 5;
Fig. 7 ls a schematlc dlagram of the frequency
sensing logic clrcultry;
Flg. 8 i9 a schema~lc diagram of the maln breaker
logic circuitry;
Fig. 9 is a schematlc diagram of the timing loglc
circuitry,
Fig. 10 ~s a schematic dlagram of the tie breaker
logic circuitry;
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1138564 46,670 4fi,671 46,672
Fig. 11 is a schematic diagram o~ the ATC control
logic c~rcuitry;
Flg. 12 is a schematic diagram of the interface
circuitry; and
Fig. 13 is a perspective view of the automatic trans-
fer control device.
DESCRIPTION OF THE PREFERRED EM~ODIMENT
1. General Description:
In Figure 1 there ls shown a multiphase electri-
cal distribution system 10 including an automatic transfer
control device 12 (hereinafter referred to as an ATC) embody-
ing the principles of the present invention. The system 10
includes a multiphase electrlcal load 14 which coul~ be a
single piece of apparatus such as a computer or a much
larger building such as a factory, hospital, or shopplng
center. The load 14 is supplied from either o~ two alter-
nate multiphase electrical sources 16 and 18, which could
be transformers or diesel-powered electrical generators. The
sources 16 and 18 are selectively connected to the load 14
through first and second main circuit breakers 52-1 and 52-2.
The circuit breakers 52-1 an~ 52-2 are operated by the auto-
matic transfer control (ATC) device 12 according to the
status of the sources 16 and 18. The automatic transfer
control 12 senses electrical conditions upon the sources 16
and 18 through connections 24 and 26. The parameters sensed
by the ATC include voltage on each phase, phase sequence,
and frequency. Logic circuitry wlthin the ATC acts to select
the highest quallty source to supply power to the load 14.
Figure 2 shows a multiphase electrical distribution
system 11 similar to the system 10 shown in Figure 1. In the
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113~564 46~670 46,671 46,672
system 11, however, there are two electrical loads 28 and
30 connected by a tie connection 32. A tie breaker 52-T
i~ provided to selectlvely lnterconnect the two load~ 28
and 30.
In the system 11 shown ln Figure 2 a variety of
conflgurations are posslble. With both maln breakers 52-1
and 52-2 closed and the tie breaker 52-T open, the first
load 28 will be connected to the flrst source 16 and the
second load 30 wlll be connected to the second source 18.
Alternatlvely, wlth the first maln breaker 52-1 open, and
the second main breaker 52-2 and the tie breaker 52-T clo~e~,
both of the loads 28 and 30 will be supplied through the
source 18. With main breaker 52-1 and tie breaker 52-T
clo~ed and main breaker 52-2 open, both loads 28 and 30
will be supplled through the source 16.
The ATC 12 comprises voltage and frequency sen~ors
~or each source, the sensors being connected to the as~o-
clated source through potential transformers. A plurality
o~ input and output terminals are provided to supply the
ATC wlth information concerning the status (open or closed)
of associated circuit breakers, the desired actlon to be
taken upon failure of the sources, the type of dlstribution
system being controlled, etc. Outputs from the ATC include
close and trip signals for each breaker, and generator start
signals. Each input signal is 120 volts A.C. ~or high nol~e
immunity and is converted by interface circuitry to 12 volts
D.C. compatibility with logic circuitry. Output signals are
also 120 volts A.C.
The ATC is connected through power transformers to
each source and contains logic to select the best source at
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113~564 46,670 46,671 46,672
any given time to supply control power to the ATC.
A plurality of timing functions are provided to
permit selection of a wide range of tlme delay transfer and
control actions. These timing functions are provided by a
plurality of oscillators, one oscillator associated wlth
each function, each being connected to a common digit~l
counter.
In Figures 3A, 3B, and 3C there is shown a sche-
matic functional diagram of the ATC 12 connected to a three-
breaker, four-wire electrical distribution network as shown
in Figure 2. The ATC 12 is connected through three-phase
potential transformers 40, 42 and phase and neutral conduc-
tors 44, 46 to the first and second electrlcal sources 16
and 18 (not shown in Fig. 3A). A mode selector switch 43
shown in the lower left of Figure 3A is provlded to selec-
tively switch the ATC 12 between automatic, manual, and live
test modes. The potential transformers 40 and 42 supply
voltage and frequency inputs from the respective sources to
provide a signal through input terminals A9 through A12, and
Bl through B4 ~o the ATC to determine if the source is at nor-
mal voltage and frequency and has proper phase rotation. Nor-
mal voltage is defined as the minimum operating voltage at
which the customer desires the system to operate, as selected
on the voltage pickup rheostats 44.
The ATC includes two identical sets of circultry
for voltageS frequency, and timlng loglc, control power logic,
control power output, auxiliary transfer input, and generator
start logic~ with one set of circuitry for each source. In
addition~ it contalns close and trip output signal capablllties
for each of two main breakers, and the tie breaker, even
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113~5~4 46,670 46,671 46,672
though the tie breaker capabilitles may not be used in each
appllcation. The means of adapting the ATC to operate from
either two-or-three-breaker systems will be described in
greater detall hereinafter.
2. Description of Operation:
2.1 Voltage and Phase Sensor Inputs
Each source input includes two programmlng ~witches
to specify the voltage and wiring configuratlon of being con-
nected thereto. The programming switches PS-9 and PS-10
select either three-wire (three phase conductors) or four-
wire (three phase conductors and one neutral conductor)
systems; the programming switches PS-ll and PS-12 select
either 120 volt or 69 volt input voltage levels. Thus, there
are four different ways to connect the voltage and frequency
inputs A9-A12 and Bl-B4: 1) For use wlth a sy~tem voltage Or
480/277V, using 3 potentlal transformers (PT's) wlth a 4-1
ratlo connected to Y-Y. The lnput from the secondary of the
PT's will be a 4-wire connection, with the voltage on the
secondary of the PT's being 69V, phase to ground. The pro-
gramming switches are then set for 4-wire, 69V operatlon.
2) For use with a system voltage of 480/277V, uslng 3-PT' 8
with a 2.4-1 ratio connected Y-Y. The input from the secon-
dary of the PT's will be a 4-wire connectlon wlth the voltage
of the PT's being 120V phase to ground. The programming
switches are then set for 4-wire3 120V operation.
3) For use with a system voltage of 208/120V wlth no PT's.
Connection from the sources w~ll be 4-wire, with the voltage
being 120V phase to neutral. The programming ~witches are
then set for 4 wire, 120V operation.
4) For use with a system voltage of 480V, using 2 PT's with
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11385~4 46,670 46,671 46,672
a 4-1 ratio connected open delta. The input from the secon-
dary of the PT's will be a 3-wire connection, wlth the vol-
tage on the secondary of the PT~ 9 being 120V phase to ground.
The programming swltches are then set for 3-wlre, 120V opera-
tlon.
Four L.E.D.'s (Light Emitting Diodes) are supplied
for each source. When lighted, one L.E.D. wlll lndlcate that
the phase sequencing is correct. The other three L.E.D.'s
are marked phase A, pha~e B and phase C; and are lighted when
their respective phase voltages are normal. For in~tance, lf
a voltage loss occurred on phase A, with phase B and phase C
still at normal voltage, the phase A L.E.D. would extinguish,
indicating that phase A was below normal. The phase ~ and
C L.L.D.'s would remain lighted.
Two volta~e ad~usting rheostats 44 and 46 are pro-
vlded for each source for voltage pick-up and voltage drop-
out, respectively. Voltage pick-up is the level to which a
phase voltage must rise for the ATC to recognize it as havlng
returned to normal. The voltage pick-up rheostat 46 is
ad~ustable from 90% to 98% of rated voltage. The voltage
drop-out rheostat is ad~ustable from 65% to 90% of rated
voltage.
2.2 Frequency Sen~in~ Logic
Input to the frequency sensing logic i8 obtalned
internally on the ATC from the voltage inputs A9-A12 and
Bl-B4. Like the voltage inputs, the frequency sensing loglc
will function at 120V, 60 Hz or 69V, 60 ~z. It detects both
underfrequency and overfrequency conditions, with a range of
50 to 70 Hz. Both the over and under drop-out points have
independent pick up differentials within the range of the
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46,670 46,671 46,672
1138564
drop-out points. The pick-up and drop-out points (under-
frequency and overfrequency) plus the differentials are
selected for the specific appllcations; and once selected,
cannot be changed.
The underfrequency drop-out point may be selected
anywhere within the range of 50 Hz - 59 Hz. The pick-up dif-
rerential must then be selected at a point higher than the
drop-out point and less than 61 Hz. For example: if the
underfrequency drop-out point selected is 54 Hz, the plck-up
differential selected must be between 54 Hz and 61 Hz.
The overfrequency drop-out may be selected anywhere
in the range of 61-70 Hz. The pick-up differential must then
be selected at a point less than the drop-out point and
higher than the 59 Hz. For example, i~ the overfrequency
drop-out puint selected ls 65 Hz, the pic~-up dlfferential
selected must be 59 Hz and 64 Hz.
An L.E.D~ ls supplied, whlch when llghted, indi-
cates that the frequency is within the predetermined limlts
of both the over and underfrequency drop-out points.
When frequency sensing ls not desired, this logic
can be omitted and the ATC will assume normal frequency.
The frequency loglc can perform two basic functions,
selected for each source by programming switchs PS-7 and PS-8,
respectively.
1. "Pre~ent Closing Only" - With the mode selector switch 43
in the automatic position, either two-or three breaker opera-
tion specified, and one source normally deenergized (for
example~ an emergency generator~, low voltage upon the normal
source will cause a slgnal to be sent to start the generator.
When the generator comes up to proper voltage but t~!e frequency
46, 670 46 ~ 671 46, 672
113B564
is not within the proper operating range as selected, the
generator source ~ain breaker will be prevented from auto-
matically closing until the ~requency has reached proper
operating range.
2. "Automatic Transfer Function" - With the mode selector
switch in automatic position, two-or three-breaker operation
specifled, and both sources or one source only normally
energized, if the frequency on a source that is ~eeding a
load falls or rises beyond the 11mlts of the normal operating
range and after a predetermlned time delay (as selected on
the off delay timer, described hereinafter) the maln breaker
on the faulted source will trip and a transfer operation to
the alternate source, as programmed, wlll occur.
2.3 Manual Breaker Closing (Inputs)
Terminals A2 - Breaker 52-1
B10 - Breaker 52-2
C3 - Breaker 52-T
These inputs provide for electrical closing of the
breakers by means of a control switch, pushbutton, or other
manually operated control device and are operatlve only with
the mode selector switch 43 in the manual position. When
120V A.C. appears upon any of these terminals, the ATC wlll
generate a 120V A.5. output signal at the corresponding CLOSE
output A6, ~7, or C5.
An L.E.D. is provided to indicate the logic signal
being supplied to the output slgnal generating circuitry.
The L.E.~. will be lighted when a "close breaker" logic sig-
nal is being supplled to the interface circuitry whlch gene-
rates the 120V '~close'~ command for the breaker. However~
there are times when the L.E.D. will be lit yet the breaker
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~13856~ 46,670 46,671 46,672
remains open. For example, if through a manual control
switch or an autotransfer s~gnal the ATC is being signalled
to close the breaker, and due to a malfunctlon, the breaker
does not close, the L.E.D. will be lit, indicating that the
ATC logic is calling for a closlng operation.
2.4 Manual Breaker TripPing (In~uts)
Terminal~ Al - Breaker 52-1
B9 - Breaker 52-2
Cl - Breaker 52-T
These inputs provide for electrical tripping of the
breakers by means of a control switch, pushbutton, or other
manually operated control devices, and are operative only
with the mode selector switch 43 in the manual po~ltlon. ~en
120V A.C. appears on any of these terminals, the ATC will
operate 120V A.C. output signal at the corre~pondine TRIP out-
put terminal A7, B8, or C6. An L.~.D. ls provided to lndl-
cate the loglc signal supplied to the output clrcuitry which
generates the 120V trip signal for the breaker trlpplng
relay or trip coil. When the breaker is tripped, the L.E.D.
will be lighted. Again, as described previously, it is pos-
sible for the L.E.D. to be llghted yet the breaker remalns
closed.
2.5 Aux. Automatic Transfer
A5 - Source #1 to Source #2
B9 - Source #2 to Source #l
These inputs are provided in the event that an
automatic transfer has to be initiated by mean~ other than
the ATC de~ice's built-in voltage and frequency sensors,
such as external relaying on a com~lex system.
A 120V A.C. signal to this input causes an imme-
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113~S64 46,670 46,671 46,672
diate transfer (time delay ls bypassed from one source to
the other when the mode selector switch 43 is in the auto-
matic mode and the other source is within normal limits.
Once this signal is removed from the lnput, an immediate
retransfer (time-delay is bypassed) will take place if:
1. The ATC device is programmed for automatic return to
normal, and
2. The sollrce is within the other limitat~ons of proper
voltage and frequency.
2.6 Auxiliary Lockout
A3 - Breaker 52-1
Bll - Breaker 52-2
C4 - Breaker 52-T
A 120V A.C. signal into this input can be from
any external device that requires that the breaker be blocked
from electrical clos~ng. This input will not trip the breaker
if it ls closed. It merely blocks electrlcal closing after
the breaker is tripped. These lockout inputs are not voided
by the selector switch 43 and will function in any mode.
2.7 _Breaker ,Status Indicator
A4 - Breaker 52-1
B12 - Breaker 52~2
C2 - Breaker 52-T
These inputs inform the ATC of the status (closed
or tripped) of the associated breakers, infor~ation which is
required for electronic interlocking and breaker st~tus indi-
cation. The signal to the input is supplied from a normally
closed (N.C.~ breaker auxiliary switch.
2.8 Bround Fault Lockout
C9
~13~564 46,670 46,671 46,672
The signal to this input is generated by a normally
open (N.O.) contact which is activated by a ground ~ault
detection system. When energized, this input will prevent
electrical closing of all breakers. If a breaker is already
closed, this input wlll not trip the breaker. Also, unllke
Auxiliary Lockout, a trip signal ls sent to all breakers that
are open. This signal will trip the breaker if the breaker
has been mechanically closed by the Manual Close button on
the front of the breaker. This is to prevent any open breaker
from being closed into a fault.
Removing the signal from the lnput will not vold
the lockout; once the lockout is activated, it must be reset
by lnput C8 (Latch Reset).
An L.E.D. is supplled to indlcate that ground fault
lockout has occurred.
2.9 Overcurrent l.ockout
C10
The signal to thls input wlll be from an N.O. con-
tact that is actlvated by an overcurrent trlpplng device as80-
ciated wlth the breaker. When energized, thls input w~ll
prevent closlng of all breakers (If the breaker ls closed,
thls wlll not trlp the breaker). Also, unlike Auxlliary
Lockout, a trlp slgnal is sent to all breakers that are open,
which slgnal will trip the breaker if lt has been mechanl-
cally closed by the Manual Close button on the front Or the
breaker.
Removing the signal from the input wlll not vold
the lockout; once the lockout is activated lt must be reset
by lnput C8 (Latch Reset).
An L.E~D. ls supplied to lndicate that overcurrent
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113BS64 46,670 46,671 46,672
lockout has occurred.
2.10 Latch Reset
C8
This input is used to reset the ATC logic after a
lockout has occurred from C9 or C10, and the fault has been
cleared.
The signal to the input will be from an N.O. push-
button or an N.C~ contact from an electric or hand reset
relay that was used to energize C9 or C10.
Note: Signal to C9 or C10 must be removed before
latch reset will function.
If for some reason all control voltage is lost,
the latch will automatically reset.
2.11 Control Power
Dl - D2 Source #1 D4 - D3 Source #2
Input is 120V, 60 Hz power from the secondary
of a control power transformer. The control power trans-
for~er primary is connected to phases A and C of each source.
2.12 Auto Disable
. _
Cll
The signal to this input is rrom a "Manual' (M)
contact of the mode selector switch 43. This input slgnals
the logic that all func~ions that are performed in the auto-
matic mode should now be voided, except ror the interlocking
and lockout.
2.13 T _ Input
~ 1~
The signal to this input is from a "I.~ve Test'~ (LT)
contact on the mode selector switch 43. This input signals
the logic to perform all operations in the same manner as the
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113~S64 46,670 46,671 46,672
automatic mode, except to disable the circuitry which gene-
rates the output signals to the breakers, thereby preventing
the breakers from being tripped or closed by the ATC.
2.14 Close Output
A6 - Breaker 52-1
B7 - Breaker 52-2
C5 - Breaker 52-T
When a signal is received from the ATC logic to
electrically close a breaker, the output from these terminals
is 120V, 60 Hz. It should be noted that output remains at
120V as long as a closing logic signal is present. (When
in the automatic mode, the closing signal is not removed
until a trip or lockout is called for.)
When these outputs are energized, the L.E.D.'s (as
described under Manual Breaker Closing) are lighted.
2.15 Trip Output
A7 - Breaker 52-1
B6 - Breaker 52- 2
C6 - Breaker 52-T
When a signal i8 received from the ATC logic to
electrically trip a breaker, the output from these terminals
is 120V, 60 Hæ. It should be noted that the output stays at
120V, as long as the tripping logic signal is pre~ent. When
in the automatic mode, the tripping signal is not removed
until a close is called for.
When these outputs are energized, the L.E.D.'s (as
descrlbed under Manual Breaker Tripping) are lighted.
2.16 Control Power Output
D5
This is the output from which control power is
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~3~}S64
46,670 46,671 46,672
obtained for the equipment remote from the device (indlcating
lights, misc. relays, etc.). This output is under the influ-
ence of the control power transfer scheme, which is a part
of the ATC. The output is 120V, 60 Hz.
2.17 Generator Start
A8 - Source #1 controls Gen #2
B5 - Source #2 controls Gen #l
These outputs are energized whenever their corre~-
ponding source voltage is within the normal limits. The
outputs are connected to auxiliary relays which, under normal
conditlons, will be energized. If a source fall~ below nor-
mal limlts and the ATC logic calls for an automatlc transfer,
the generator output will do one of the following:
1. If the voltage falls to less than 55% of rated voltage
(control power threshold which i~ described in 2.18), the
Generator Start output will be deenergized immediately, and
the auxlllary relay will drop out, thus sending a signal
starting the generator.
2. If programming switch (PS-6) is closed, the generator
starting operation will be delayed. Otherwise, the operation
is begun as soon as the voltage sensors call for a transfer.
a. With programming switch PS-6 set for no time
delay, as soon as the voltage sensors ask for a
transfer, the Generator Start output will drop out
(even lf control power is still available), deener-
glzing the auxiliary relay, thereby sending a signal
to start the generator.
b. With programming switch set for time delay, when
the voltage sensors ask for a transfer, the gene-
rator start output will be delayed 1/2 of the off
1~38564 46,670 46,671 4~,672
delay timer setting before being deenerglzed
provlded sufficient control power is still
available, i.e., > 55%).
The signal to shut down the generator ls accom-
plished by reenergizing the Generator Start ou~put. The out-
put is reenergized after the normal source has returned, a
retransfer has occurred (if programmed for automatic return
to normal), and the Generator Unloaded running timer has timed
out. The Generator Unloaded running timer is ad~ustable from
]-0 15 sec. to 30 mln. When the ATC is programmed for manual
return to normal, the Generator Unloaded running time beglns
to time out as soon as the mode selector switch 43 ls placed
in the manual positlon, and the tripped breaker ls reclosed.
An L.E.D. is supplied for each Generator Start out-
put. When the L.E.D. i5 llghted, this lndlcates that the
Generator Start output is energized and is not calling for a
generator start.
2.18 Control Power Selector Switch - Programming Switch ffl
(PS-l)
This switch is to deslgnate which power source 18
selected as the normal source of control power for the ATC
ltself. When programming switch PS-l i8 open, source #1 i8
selected as the normal control power source. When switch
PS-l is closed, source #2 i9 deslgnated a~ normal. The above
statements apply only when both sources are at normal voltage.
The control power trans~er logic will seek out the
higher voltage source, regardless of the programming swltch
PS-l se-tting, if the level of the designated source falls
below the drop-out setting of its associated voltage sensor.
33 Example: Progrz~ing switch PS-l set to select
-19-
113~}S64 46, 670 46, 671 46, 672
source ffl as normal control power supply source. If the vol-
tage source #l falls below the drop-out setting of the #l
voltage sensor and the #2 voltage sensor shows normal vol-
tage, the control power transfer loglc will signal for a
transfer to source #2. t~en the restored voltage on source
#l exceeds the plck-up level of its voltage sensor, a return
to source #l will occur, because the PS-l setting deslgnated
source #l as normal control power supply.
If both voltage sensors lndicate voltages below
their respective drop-out levels, the logic will then seek
to select the source with the higher voltage level, provided
that the source is higher than 55% of normal voltage.
The 55% criterion is chosen because a failùre of
a single phase results in a phase-to-phase voltage Or about
57% of normal phase-to-phase voltage. Although thls degree
o~ failure would seriously affect the main load belng sup-
plied and requires that the load be switched to an alternate
source, 57% of normal voltage is stlll satlsfactory for
control purposes. However, a voltage appreciably less than
this would result in unreliable control actlon. Therefore,
55% of normal voltage is selected as the polnt at which a con~
trol power transfer should occur.
If no control power is avalla~le at an input because
of a blown fuse or faulty control power transformer, regard-
less of the lndication of its associated voltage sensor, the
control logic (see 4.8~ will select the other source provided
that the source is hlgher t~lan 55% of normal voltage.
If the voltage on both sources falls below 55% Or
normal, all control power will be dlsabled until one of the
sources returns to a value greater rhan 55% of normal.
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113~3564
46,670 46,671 46,672
Two L.E.D.'s are supplied - one for source ~1, and
one for source #2. The one that is llghted indicates which
source i3 supplying the control power.
2.19 Tie Trip Inhibit
Programming Swltch #2 (PS-2)
This pro~ramming switch is to be used to select
manual or automatic return to normal, on a 3-breaker system
(2 main breakers and a tie breaker).
When the programmlng switch PS-2 is in the open
position and a transfer operation has taken place (1 main
breaker tripped and the tie breaker closed), and when the
failed source returns to normal, and after a predetermlned
tlme delay, the tie breaker will trip and the main breaker
reclose (automatic return).
When the proKrammlng switch PS-2 i8 ln the closed
posltion, a retransrer back to the restored source will not
occur, and the tie breaker will remaln clo~ed. Retransfer
back to the restored source can be accompllshed in either of
two ways:
1) If the failed source has returned to normal and failure
occurs on the source to which the load has been transferred,
then the main breaker on the failed source will trlp, and the
main breaker on the restored source will reclosed (the tle
breaker will remain closed during this operation).
2) After placlng the mode selector switch 43 ln the Manual
position, the breakers involved can be tripped and closed
using their respective manual control switches or pushbuttons.
2.20 Trip #2 if #1 i3 Normal
Trip #1 if #2 is Normal
Programming Switches #3 and #4 (PS-3, PS-4)
-21-
6~ ~
~13~564 46,670 46,671 46 J 672
These programming switches are to be used to select
manual or automatic return to normal on a two-breaker system
(2 main breakers and no tie breaker).
If both of these programming switches are left open,
the first source energized wlll be selected as the normal
source that feeds the load. If an automatlc transfer opera-
tion takes place and the failed source then returns to nor-
mal, a retransfer back to the restored source wlll not take
place as long as the source that is feeding the load remains
at normal.
Retransfer back to the restored source w~ll be per-
formed in either of two situations:
l) The failed source has returned to normal and a failure
occurs on the source to whlch the loa~ has been transferred.
2) Wlth the mode selector swltch 43 ln the Manual position
and the breakers are trlpped and closed uslng thelr respec-
tive manual control swltGhes or pushbuttons.
PS-3, when closed, deslgnates maln breaker 52-1 and
source #l as the normal power source that feeds the load.
When a transfer operatlon has occurred and trans~erred the
load to source #2, a retransfer back to source #1 will occur
as soon as source #l returns to normal and the timers have
timed out.
PS-4, when closed, performs the same function as
PS-3, except main breaker 52-2 and source #2 is deslgnated
as the normal power source for the load.
Either PS-3 or PS-4 may be closed, or nelther one;
they may not both be closed. Note that PS-3 and PS-4 desig-
nate normal power source for the load, while PS-l designates
the normal source of power for the ATC device and its control
-22-
1138S64
46,670 46,671 46,67
functlons.
2.21 Kee~ I.ast Source
Programming Switch #5 (PS-5)
~ his switch, when closed, inhibits automatic trip-
ping of a main breaker if it receives a transfer signal from
its source and t~e load has been prevlously transferred to
this source. This lnhibitlon is removed when the source from
w}llch the lo~(l ha~ been transierred returns to normal.
When this PS-5 is open and the load has been trans-
ferred to a source #2 due t~ a failure on source ffl, and ifsource #2 (now feeding the load) has a failure, the maln
breaker #2 of second failed source #2 will see an automatlc
transfer signal and will trip even though threre is no avail-
able source to transfer to. This will occur only lf the vol-
tage on the ~ailed source #2 has dropped below the drop-out
setting of the voltage sensor and is above 55%, thereby provl-
ding control power.
ln either case (both maln breakers tripped, or one
tripped and one closed), if both sources are subnormal and
one source returns to normal, the normal source breaker will
close and the other main breaker, if closed, wlll trip regard-
less of how the system was programmed (manual or automatlc
return to normal).
2.22 Delay enerator Start
Pro~ram~ing Swltch #6 (PS-6)
This programming switch, when cloaed, ~elays drop-
out of the Generator Start output approximately 1~2 of the
settlng of the off~delay timer when confrol power ls a~railable
(refer to enerator Start).
When PS--6 is open, the GeneratoI7 Start outpuf wlll
-~3-
113~564 46,670 46,671 46,672
drop out as soon as an automatic transfer slgnal is recei~ed.
2.23 Frequency Function Selector
Programmlng Swltch ~7 (PS-7) - Source #l
Programmlng Swltch #8 (PS-8) - Source ~2
These programmin~ switches are to select the fun-c-
tlon that is to be performed by the frequency sensors (as
described under Frequency Sensln~ Logic).
2.24 3-Wire 4-Wire
Programming Swltch #9 (PS-9) - Source #l
Programming Switch #10 (PS-10) - Source #2
These programming switches are to select the type
of connection to be applied to the voltage sensors, 3-wlre
(phase conductors only) or 4-wire (phase conductors plu9
neutral), as described in Voltage and Phase Sensor Inputs 2.1.
2.25 120V~ 69V
Programming Switch #11 (PS-ll)
Programming Switch #12 (PS-12)
These programming switches are to select the input
voltage to the voltage sensors (as described under Voltage and
Phase Sequenclng Inputs).
2.26 AdJustable Timers
A total of six ad~ustable timers are furnished,
three for source #l and three for source #2.
1) On-delay timing is supplied for both sources to ensure that
when a failed source returns to normal, the voltage i8 stabl-
lized before a retransfer will occur. The timing range 18
ad~ustable from 2 seconds to 10 minutes.
2) Off-delay timing is supplled for both sources to ensure
that momentary dips in ~oltage will not cause a transfer
operation. The timing range is ad~ustable from 2 seconds to
-24-
113~S64 46,670 46,671 46,672
10 minutes.
3) A Generator Unloaded running t~.mer is provlded for each
source. These tlmers have a range of 15 seconds to 30
minutes.
Two L.E.D.'s are supplied, one for each set of
on-and off-delay timers as described in 1) and 2) above.
The L.E.D. wlll indicate when the tlmers are timing and which
timer was last to operate.
L.E.D. Operation -
1. When either the on-or off-delay timer i8 timlng, the
L.E.D. will be flashing.
2. If the on-delay timer was the last to operate, the
L.E.D. will be continuously llghted.
3. If the off-delay timer was the last to operate, the
L.E.D. wlll not be llghted.
3. Sequence of Operation:
3.1 3-Breaker System
~El:~
IJnder these conditions, both source~ are at normal
voltage and are feeding their respective loads. That ls~
both maln breakers 52-1 and 52-2 are closed, and tle breaker
52-T is open.
3.1 2 Automatic Mode
-
1) Wlth a 108s of voltage on one o~ the source~, the rollowlng
will occur: Assumlng a failure o~ source #1~ the source #1
voltage sensors wlll generate a logic signal to start the off-
delay ~imer. When the off-delay timer expires, the pro~rammabl
logic will generate activating logic signals to the output
signal generators causing breaker 52-1 to ~rip and ~reaker 52-q
to close. The same operation occurs should source #2 have
-25-
113~564 46,670 46,671 46,672
failed, except breaker 52-2 would trip after a time delay and
the tle breaker (52-T) would close thereafter.
2) Should there be a simultaneous loss of voltage on both
sources, the following will occur:
a. If both source voltages fall below 55%, no control
power will be available. Thus, both maln breakers wlll
remain closed and the tie breaker open.
b. If one (or both) of the sources is below the accept-
able llmits of the voltage sensors, but greater than 55%,
control power wlll be avallable and the followlng wlll occur:
(1) If programming swltch PS-5 (Keep Last Source~
is open, both maln breakers wlll trlp after
their predetermined time delay. If one maln
breaker trips before the other due to a
shorter delay, the tie breaker will close,
whlch is acceptable at this point. This would
almost surely be the caæe since to set 2
timer~ (2 seconds - 10 minutes) at the exact
same time would be nearly impossible. Which-
ever source first returns to normal will cause
the corresponding main breaker to close, ~ol-
lowed by the tie breaker tif not already
closed).
(2) If programming switch PS-5 (Keep Last Source)
is closed, the first source for which the off-
delay time has explred will experience a main
breaker trip. Once that main breaker trips
it will be followed by tie breaker closure.
The other main breaker ls pre~ented from trlp-
3C plng (e~Jen though the correspondlng off-delay
-26-
113~3S64
46, 670 46, 671 46, 672
timer has explred). If the first source then
returns to normal arter a predetermined
time delay (on-delay) the main breaker on
the low source will trip, followed by clo-
sing of the main on the returned source
(tie breaker remaining closed).
3) Should there be a loss of voltage at one source and abnormal
voltage at the other, a transfer as described ln (1) above
would have already occurred. Therefore, the following se-
quence is also true should voltage be lost on the source to
which the load has been transferred:
a. T~hen the normal source fails and neither of the
sources is above 55%, no control power will be available.
Thus, there wlll be no change in breaker status (one maln
breaker and tie breaker closed, other main breaker open).
b. When the normal source fails and one or both Or the
sources are above 55~, control power will be available and
the following will occur:
(1) If programming PS-5 (Keep Last Source) is
open, after the predetermined time delay, the
main breaker of the source that was serving
the load will trlp resultlng ln a condition Or
both main breakers tripped and tie breaker
closed. Whichever source returns to normal
first, after a predetermined tlme delay (on-
delay) its main breaker wi l close, thus leavln~
the condition of one maln breaker and the tie
breaker closed (tie breaker had never been
trlpped) and the maln breaker open.
(2) I~ programmlng PS-5 (Keep Last Source) ls
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46,670 46,671 46,672
closed, the main breaker that ls feedlng th~
load will be blocked from tripplng. One
main breaker and the tie is now closed, wlth
one main breaker open and both sources at
subnormal voltage. If normal voltage is re-
stored to the source that was last feedlng
the load, there will be no change ln breaker
status. If voltage is restored to the Cource
from which the load was originally transferred
after a predetermined time delay (on-delay),
the maln breaker on the subnormal source wlll
trip, followed by closing of the main on the
restored source which yields the condition of
normal source main breaker and tie breaker
closed (tie breaker had never been trlpped)
and subnormal main breaker tripped.
4) Return to normal after a transfer operation ¢an be accom-
plished ln one of two wa~s.
a. When programming PS-2 (Tie Trip Inhibit) i~ ln the
open position and voltage on the soure from which the load
had been transferred returns to normal after a predetermlned
time delay (on-delay), the tie breaker wlll be tripped rol-
lowed by reclosing of the restored source's main breaker.
~Automatic return to normal~
b. When programming PS-2 (Tie Trip Inhlbit) ls ln the
closed positlon and the voltage on the source from whlch the
load had been transferred returns to normal, no retransfer
wlll occur.
The mode selector switch 43 must be placed in the
manual position and the tle breaker then tripped and ~he maln
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1 1 38S64
46,670 46,571 46,672
breaker reclosed by means of their respective ~anual control
swltches or pushbuttons.
3.1.3 Manual ~ode
With the mode selector switch 43 in the manual
position, control of the breakers ls placed in the hands of
the operator. Breakers may be clo~ed and tripped (as gov-
erned by interlocking and lockout) by means of their respec-
tive manual control switches or pushbuttons.
3.1.4 Live Test Mode
The purpose of the llve test mode is to test the
operation of the ATC w~thout changing the status of the
breakers. This is accomplished through the breaker status
indicating L.~.D.'s as described in 2.3 and 2.4.
1) There are two test pushbuttons provided, one for each
source, connected to terminals A9 and B4 to stimulate 108s
of incoming volta~e to the source. With the mode selector
switch 43 ln the "test" position and one of the pushbuttons
depressed and held, one of the phase indicating L.E.D.'s and
the CLOSE L.E.D. o~ the main breaker will go out. After the
off~delay timer has timed out, the main breaker TRIP L.E.D.
will begin flashing, followed by the tie breaker CLOSE L.E.D.
whi~h will also begln flashing. These flashing L.E.D. ~9 lndi
cate the operation that would ~ave occurre~ had there been a
voltage failure on the source (main breaker TRIP L.E.D.
flashing to indicate a logic signal calling for a trip and tl
breaker CLOSE L.E.D. flashing to indicate ~ logic signal call
ing for a c~ose). When the pushbutton is released and the
on-delay timer has timed out, the L.E D. will revert back to
the actual status of the system.
It should be noted that durlng the entire sequence
-2~-
1~38564 l~6,670 46,671 46,672
descrlbed above, all operations that the ATC performs to
initiate an automatic transfer are tested (voltage sensing,
timlng, interlocking, etc.) except that in the live test
mode the inputs to the final output triacs (normally used
to generate 120V signals to the breakers) are shorted, thereby
preventlng the breakers ~rom closing and tripping. Only the
tie breaker tripplng output is not disabled durlng this opera-
tion. This is to maintain a positive interlock in the e~ent
the mode selector switch 43 19 left unattended in the live
test posltion and unauthorized personnel try to manually close
the tle breaker, causing two sources to be simultaneously
connected to the system. As a result of this interlock, the
tie breaker TRIP L.E.D. will remain lighted during the test
operation.
3.1.5 Interlocking
-
The breakers are electronically interlocked to ~re-
vent all three ~rom being clo~ed at the same time, thereby
parallellng the two sources. The interlock is operative
regardless of the position of the mode selector switch.
3.2 Sequence of O~eration
Two-Breaker System
No modification of the ATC is requlred to change
from a three-breaker system to a two-breaker system. The
breaker status inputs are from N.C. breaker auxillary con-
tacts tcontacts having a status opposite that of the main
contacts). Thus, on a two-breaker system there will be no
input for a tie breaker and the ATC will interpret this as a
tie breaker belng closed. Therefore, only the two main breakers
w~ll react to the ATC's signals.
3.2.1 Automatic Mode
1) Assume source #1 and b-reaker 52-1 is the normal source and
-30-
~ ~ 3~ S ~ ~ 46,670 46,671 46,672
source #2 and breaker 52-2 is a generator source.
a. Upon voltage failure of source #l (but source #l
still has sufficient voltage to hold in control power, i.e.,
greater than 55%) a signal i8 sent to start source #2 generator
(slgnal is instantaneous or time delayed depending on selected
setting of programmlng switch PS-6, Delay Generator Start).
After the off-delay time has expired, breaker ~2-1 will trlp.
As soon as the generator is up to proper voltage and frequency
and the on-delay timer has expired, breaker 52-2 wlll close.
b. Should the same condl~lon occur but source ~1 does
not have sufflclent voltage to hold in control power, the
genera~or wlll recelve an instantaneous start slgnal. The
off-delay tlmer has enough capacltance to contlnue tlmlng
during the period of no control power (approxlmately 10 sec-
onds between loss of voltage and the tlme for the generator
to come up to 55~ of rated voltage). After the off-delay
tlmer has expired and generator control power ls avallable~
breaker 52-1 will trip. After generator has reached proper
voltage and frequency and the on-delay timer has explred,
?0 breaker 52-2 will close.
2) For a return to normal after a transfer operation refer
to Section 2.20. After the normal breaker has reclosed, the
generator output wlll contlnue to call for the generator to
run unloaded for a predetermined amount of time (as selected
on the unloaded running timer, ad~usta~le 15 seconds to 30
mlnutes).
3.2.2. Manual Mode
13 Same as 3-breaker operation, ~ee Section 3.1.
3 2.3 Interlocking
Breakers are interlocked to prevent both from being
-31-
~ 564 46,671 46,672
closed at the same time and paralleling the two sources.
The interlock is operative regardless of the position o~ the
mode selector swltch 43.
3.2.4 Lockout
Same as three-breaker operation.
4. Circuit Description:
Unless otherwise stated, the ATC device contalns
two of each clrcult, one for each source, and the description
will refer to the source #l clrcult. Items ln parentheses
re~er to the correspondlng ltem reference ~or sourc~ ~2.
4.1 Power SUPP1Y
The Power Supply circult, Flgure 4, contains iso-
lated bldlrectlonal thyristor (triac) switches for control
power trans~er and partially redundant low voltage DC sup-
plies. Flgure 4 shows the entlre power supply clrcuitry for
both sources. The secondarles of the two control power
transformers are connected between termlnals Dl and D2 and
between terminals D4 and D3. Terminal D5 carrles the switched
control power of 120 volts AC, nominal, with respect to
ground termlnals D2-D3. The power lnputs are protected
against high voltage translents by metal oxide varlstors
D47, 348. The Control Logic circuit (Flg. 11) determines
which transformer ls to be the source of control power and
sinks current at either terminal Co42 for source #1 or Co3
~or source #2. Current into Co42 turns on optlcally coupled
thyristor isolator A4. The thyristor of A4 short circults
dlode bridge DB4 to provlde AC gate current for triac Q42
from its snubber network R41, C43 and C44. The snubber
limits the voltage across the thyristor o~ isolator A4 to
less than hal~ that across triac Q42 ln addition to providing
- -32~
~i38564
46,671 46,672
dv/dt protectlon for both thyrlstors A4 and Q42.
Tran~formers T41 and T42 for low voltage DC supplles
are also connected to the control power input~. The center
tapped transformer T41 and diode bridge CB4 provide posltlve
and negative supplies smoothed by capacltors C47 and C49,
respectlvely. A redundant supply ls associated with T42
conslsting of brldge EB4 and capacltors C48 and C410. Both
unregulated negative supplles are connected at C18 and CilO
to Control Loglc lnputs in order to sense the presence of
control voltage from the transformers T41 and T42. Dlode~
D43 through D46 allow the greater magnltude DC voltages to
æupply the positive and negative regulators. The positlve
regulator which only ~upplies low current to the two Voltage
Sensor clrcults is simply Zener Diode D41. The negative 18
a series regulator uslng transistor Q41 and Zener dlode ~4
as a reference. The negative supply powers all the ATC
logic circultry with a Vss ~logic 0) of -12.4 volts. For
each of the loglc circults a separate dlode and capacltor
establlshes Vdd (loglc 1), a diode drop below ground. High
current loads sink current directly from ground to Vss ~
that a logic supply Vdd to Vss ls malntained durlng short
power outages.
4 2 Voltage Sensor
The Voltage Sensor circults contaln loglc for
lndependently measuring each of '~he three phase voltages,
checking the phase sequence, and monitoring the phase-to-
phase voltage that powers the control power transformer.
Two identical voltage sensor c~rcults are provlded, one for
each ~ource. The voltage sensing clrcuitry is described
more completely in the aforementloned copending U.S. Patent
-33-
Q ~
113l~5~i4
46,671 46,672
Application Serial No. , entitled "Automatic Transfer
Control and Voltage Sensor" (W.~. 46,670) filed
by George F. Rogel and Robert M. Oates.
The Voltage Sensors, one of whlch is shown ln
Flgure 5, use +12 volts for operatlonal ampllflers, but most
clrcuitry uses -12 volts to ground. The secondarles of the
input potential transformers are referenced to ground, and
voltage magnitude measurements are negative with respect to
ground. Fig. 5 shows the Voltage Sensor circuit configured
for three-wlre operatlon and connected to an open-delta
potential transformer. Connections to a four-wire Y-secondary
potentlal transformer are shown ln dashed llnes.
The reference voltage ls selected by swltch PS-ll
(PS-12) 5.1 volts or 8.0 volts for rated AC lnputs o~ 69 or
120 volts, respectlvely. The DROP OUT potentiometer R577
determlne~ the threshold voltage for the three input compar-
ator~, corresponding to 65~ - 90% of rated lnput voltage, lf
the sensor output lndicates normal voltages on the bus.
Translstor Q52 di~ables the PICK UP potentiometer R578 by
ralsing it to ground potentlal and reverse bia~ing diode
D514.
If switch PS-9 (PS-lO) is ln the 4 WIRE posltlon,
each of the phase-to-neutral voltages ~eeds ldentical clrcults.
The phase A voltage of the poten~ial transformer secondary
connected to terminal Va37 is divlded by reslstors R570 and
R556, with diode D55 clamping during the po~ltive hal~
cycle Ir the negative peak exceeds the magnitude of the
threshold voltage, comparator output 5A2 goes high to trlgger
monostable multivibrator 5B. Output 5B6 goes hlgh blocking
3~ diode D58 and output 5B7 goes low, turnlng on 0A NORMAL
-34-
~ 113~3S64
46,671 46,672
light-emlttlng diode D519. The 44 milllsecond pulse wldth
of the retriggerable monostable multivlbrator 5B require5
that two successlve llne cycles fall below the selected
threshold for a low voltage lndlcatlon. If any Or the phase
voltages (or the phase sequence) ls abnormal, comparator
lnput 5E6 is pulled below lts reference lnput 5E7 by dlodes
D58, D59, D510 (or D517). The VOLTAGE NORMAL, Vl, output at
terminal Vol4 goes low and its complement at termlnal Vol2
goes hlgh to slgnal abnormal bus voltage. Translstor Q51
turns on to dl~able the DROP OUT potentiometer R577. This
causes the comparator threshold voltage at 5A5, 5A9, and
5All to be raised (an increased negatlve magnitude) to that
determined by the PICK UP potentiometer R578, correspondlng
to an input Or 90% to 98% rated voltage.
Phase A and C potential trans~ormers are also con-
nected to voltage divlders conslsting of resistors R575 and
R562 or R576 and R560, respectively. A signal proportlonal
to the phase-to-phase voltage Vca(t) i9 present at opera-
tional ampllfier output 5C12. In a 3 WIRE system the two
open-delta potential transformers provlde Vabtt) and Vcb(t)
to the phase A and C voltage sensors at VA37 and VA33,
respectively. The operatlonal amplifier-generated value
proportional to Vca(t~ ls provided to the third sensor at
5A8 via reslstor R551 and swltch PS-9A (PS-lOA).
The Vca(t) signal has three other uses. Swltch
5S2B selects resistor R561 or R552 to connect Vca(t) to the
comparator input 5E8 in a circuit simllar to the three
above~ In thls case monostable multivibrator output 5D6
drives termlnal Vo20 high if phase-to-phase voltage Vca
powering the control power transformers ls above 55% of
-35-
1~3~564 46,671 46,672
rated (Pl - 1). The 55% threshold DC voltage is derived
from reslstors R563 and R567 in the reference circuit.
The Vca(t) signal ls rectlfled and smoothed by
diode D518 and capacltor C510 to ~eed comparator input 5A6.
An identlcal circuit on the second Voltage Sensor clrcu~t ls
cross-coupled vla external connectlon, with comparator
negative input cf Voltage Sensor Circuit #l connected to
comparator posltlve lnput of Voltage Sensor clrcult #2 and
conversely. These comparators determine which of the two
control power sources is greater ln magnltude. Comparator
output 5Al of Voltage Sensor #1 drives termlnal Vlo4 hlgh if
Vca of #1 is greater (Pl> P2 ~ 1). The double hysteresis
effect of the feedback reslstors R536 ln each comparator
ensures that a prevlously lower source must exceed the
selected control power source by several volts before causlng
a control power transfer.
The phase sequence checklng also uses the Vca(t)
signal with a 30 lag due to reslstor R566 and capacitor
C53. In 4 WIRE systems of proper sequence switch PS-9C (PS-
lOC) connects a Vc(t) signal to operatlonal ampllfler lnput5~7 equal in magnitude and phase wlth the Vca(t-30) slgnal
at amp lnput 5C6. In 3 WIRE systems switch 5S2c connects
Vcb(t) vla a 30 lead network (reslstor R573, R574, R568 ln
parallel wlth R569 and capacltor C51). Wlth proper sequence
the Vcb(t~30) slgnal is equal ln magnitude and phase wlth
the Vc~t-30) slgnal.
Flgure 6 shows a phasor diagram of the sequence
clrcuit operatlon. It can be seen that wlth normal sequence
on a 4-wire system the phase angle of phase to-ground voltage
Vc ~90~ ls equal to the phase angle of phase-to-phase ~ol-
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1~38S64 46,672
tage Vca (120) shifted 30 in a lagging dlrection. Siml-
larly, wlth normal sequence on a 3-wire system the angle of
voltage Vcb (60) shi~ted 30 ln a leadlng direction is
equal to the angle Or voltage Vca (120) shifted in a lagging
direction. Resistors R574, R573~ R568, and R566 are chosen to
provide proper proportionality constants to make the equa-
tions of Fig. 6 hold true. Thus, ln either 3 or 4 wire
positlons, the operational amplifler 5C10 output voltage ls
negligible and comparator positlve input 5Ell is near ground
potential due to resistor R528. Comparator output 5E13 is
high, blocking diode D517 and lightlng SEQUENCE CORRECT
light-emltting diode D522 via transistor Q53. For either 3
or 4 wire, reverse sequence is equivalent to 180 phase
reversal of Vca phasor. Thus, the large voltage present at
the operational amplifier output due to out-of-phase inputs
i5 rectifled and smoothed by dlode D515 and capacitor C59.
PositiYe input 5Ell is driven below the -8 volt reference
input and output 5E13 goes low. Transistor Q53 and L.E.D.
D522 are held off. Dlode D517 pulls comparator lnput 5E6
low to lndicate an abnormal source at the voltage sensor
output Vol4.
4.3 Freauency Sehsor
The over/under frequency measuring clrcult ls
deslgned to digitally determlne if an input voltage is
between present frequency llmlts. The frequency sensor is
described more completely in the aforementioned copending
U.S. Patent Application Serial No. entitled "Auto-
matlc Transfer Control Devlce With Programmable Frequency
Sensor" ~W.E. 46,671~ ~lled by Paul M. Johnston.
The circult, Figure 7, test~ the incomling slgnal during one
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1 ~ 3 8 S ~ 46~672
cycle to see that it is above a lower frequency limlt and
on the next cycle tests the input to see that it is below
an upper l~mit. The process continues on alternate cycles
unless one of the limits has been exceeded.
If the lower frequency limit is passed, the circuit
is programmed to test tlle inc~ming signal and compare it to
a preset return freqllenc~ higher t~lan the trip point. In
other ~ords, t,}le in~ut signal frequencv is required to return
to a fre~uency that is higher, s~y 2 H~ typically, than the
dropout condition before the fault indication is cleared.
A similar procedure occurs when the upper frequency limit
i5 passed, excep~ that the return point is set typically
2 Hæ lowcr than the trip point. The four values, that is,
the overfre~uency and underfrequenc,y trip values along with
the two return values, are stored as eight bit binary num-
bers in a read-only memor~, inte~,rated circuit 7D.
The read-only memory (ROM) 7D requires a 5V DC
power supply at relatively high current. Thus, the fre-
quency sensor logic operates on a VDD to ~SS supply of 5V
DC established by Zener diode D72, ~o conserve current the
ROM is turned on only briefly, just before a half cycle
measurement period, The four comparators of 7A use the 12V
DC supply Vcc to Vss at input and output.
Assume underfrequency testing is called for by a
logic 1 on pin 1 of flip-flop 7J. If no alarm condition had
been sensed before, the ROM is addressed with logic 0's on
pins 7D13 and 7D34. If the input vo3tage (69 or 120 volts
nominal) is in the negative half cycle, input sensing pins 8
and 11 of the 7A comparator are more negative than the refe-
rence voltage established by resis~,ors ~77 and R79. Thus,
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~138564 46,~72
the memory power supply switch Q71 is off as 7A13 is low,
and the clock oscillator 7C is held off via inverter output
7B6 and 7A14 is high. At the positive zero crossing of the
line, 7A13 goes high, turnin~ on Q71 to energize the memory
7D. Inverter Oll~put 7B15 resets counter 7H and loads latches
7F and 7G with the binary representation of the underfre-
quency trip ].evel stored in the ROM. The input signal at
7A8 lags that at 7All due to capacitor C72. This allows the
just-mentioned initializing by 7A13 before 7A14 ~oes low
to start a measurement.
When 7A14 goes low at the delayed zero crossing,
7A13 is pulled low through diode D73 removing the reset on
counter 7H, latching 7F and 7G and turning off Q71. Capa-
citor C73 maintalns power to memory 7D during the latching
of 7F and 7G. The clock oscillator 7C runs while 7A14 is
low. At the delayed negatlve zero crossing, 7A14 goes high
to shut off the clock and to toggle flip-flop 7J. The num-
ber of clock pulses counted by the 8-bit counter 7H repre-
sents the period of the input line voltage. This ls compared
with the 8-bit binary representation of the underfrequency
trip level period from latches 7F and 7G. The underfrequerlcy
output 7M12 of the 8-bi.t magnitude comparator consisting of
7E and 7M is high if the period counted is greater than the
trip level period stored in the ROM (TinpUt > Tu~ trip implies
input ~ fu~ trip~ The state of output 7M12 is latched by
flip-flop 7L at the end of the measurement half cycle when
flip-flop output 7J2 is toggled to a logic 1. The output
circuit translates the state of latch 7L to the 12 volt logic
level used by the other logic modules~ If the frequency is
within normal limits, the output of the sensor is high and
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~138564 46,672
a light-emitting diode ~71 is on.
The toggling of flip-flop 7J addresses the over-
frequency trip level in the memory 7D for the next positive
half cyc]e. When a limit is exceeded, the ROM addressing is
modified by feedin~ baclc the fault condition stored on latch
7L. The ~AND gate~ 71~ select the return condition durlng
its appropriate cycle whle the other normal limit is examined
durin~ its alternate cycle.
4.4 ROM Progra m~, Procedure
Four locations out of the 32 locations available
in the P/ROM are utilized in this circuit. The information
stored and the particular addresses used are summarized in
the following table.
Location Stored Data
7 Underfrequency Trip Point
Underfrequency Alarm Reset
23 Overfrequency Trip Point
31 Overfrequency Alarm Reset
For example, assume that the underfrequency trip
is desired to occur if the input frequency should go below
58 Hz, and it should not reset the alarm until the input had
returned to a frequency of 60 Hz. Similarly, assume the
overfrequency trip to be set at 62 Hz with return at 60 Hz
also. Since the circuit is set up to divide a half cycle of
60 Hz inputs into 130 parts, this sets the binary number
required for locations 15 and 31 in the ROM at 1301o or
100000102. The under and overfrequency trip points are
calculated according to the following equation:
2 x frequency x 54 1023~sec = 130 x f 60
-4Q-
1 ~ 3 ~ ~ ~ 4 46,672
where frequency is the upper or lower ~requencg limit in Hz.
In ac~ual practlce, the number arrived at for count wlll not
be an integer and should be rounded to the closest lnteger
number.
Using the above equatlon, the limits arrived at
for 58 Hz and 62 Hz are as follows:
count ~62] = 126.0lo - 011111102
and
count [58] = 134.48 z 1341o = 100001102
These numbers are then programmed into the ROM at locations
31 and 7, respectively.
4.5 Main Breaker Logic
- Two identical Main Breaker Loglc Circuit~ are
provided, one of which is shown in Figure 8. Each clrcult
contalns bldirection thyristor (~riac) swltches for the
shunt tripping (Q84) and closing (Q83) o~ the corresponding
maln breaker and another for auxiliary generator engine
starting (Q85). These triacs remain gated on after breaker
operation for as long as the condltion lnitlating turn on
remains.
There are four rnodes of shunt tripplng: manual,
interlock to prevent paralleling sources~ lockout from a
faulted ~ource, and automatic transfer. The manual trlp
input Mi41 directly causes a trip upon receipt of a loglc 0
signal from its associated AC interface circuit. When the
interlock input Mil9 from the Control Logic circult goes
low, breaker closure is immediately inhibited; and after an
approximately 20 m~ec delay ~rom R~14~C~4, the trlp output
is actlvated. The ground fault or overcurrent lockout lnput
M129 also inhiblts closure when low; and lf the breaker i5
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~13~5~4 46,672
open (such as by a ground fault or overcurrent trip~, the
trip triac Q84 will be energlzed to override a mechanical
closure until the lockout latch is reset. The automatlc
transfer loglc has three trip request inputs and two in-
hibiting conditions. A logic 0 input from the off-delay
timer at Mi33, from the auxiliary transfer interface circuit
at M127, or from the retransfer to normal source logic at
Mi31 calls for an automatic trip (Mo7 goes hlgh). Input
M1131 is driven from the other Main Logic circuit's output
M2o6 which causes return to the designated normal source #2
of a two-breaker system (M2il7 = 1 via programmlng switch
PS-4) when its on-delay has timed out (M2ill = 1). The
automatic transfer by any of the three inputs ls inhibited
i~ automatic enable is off (Mil5 c O) or if the Keep Last
Source switch PS-5 is closed and the other main breaker
shows an automatic trip (M137 Mi39 = 1). Mi37 of one
circuit is cross-coupled to the other circuit's automatlc
trip output Mo7. The automatic transfer output Mol3 goes to
the Tle Logic circuit requesting a tie breaker closure to
2Q complete the three-breaker transfer.
There are two modes of closing a main breaker:
manual and automatic. Each has several inhiblting conditions.
For a manual CLOSE attempt the output of the associated AC
interface clrcuit drives Mi23 low. In the automatic mode
(M 15 high) a closure is attempted lf the normal voltage on
i
delay has timed out IMill is high) and the frequency sensor
indicates normal (Mi9 high). The closure is inhibited if
there is a trip output present, a source paralleling inter-
lock (Mil9 low), an auxiliary lockout (Mi25 low), or a
latched lockout from ground fault or overcurrent (Mi29
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`~ `3
113~564 l~6,672
low). T~ne automatic trans~er signal M 13 provides a redundant
inhibit of closure at pin 11 of 8F during transfer conditions.
In the test mode (Mi21 = 0) the gates of the trip
and close triacs are short-circuited by saturated PNP tran-
sistors Q81 and Q82. Thus, the triacs are held off, and no
breaker transfer operation occurs while testing the system.
The trip triac is allowed to operate, however, for an inter-
lock or lockout trip. A logic 0 applied to pin 13 or pin
11, respectively, of 8E turns of Q82 to allow the breaker to
trip. ~lso in the test mode the automatic enable Mil5 is
pulsed by the Control Logic circuit to flash the trip or
close L.E.D. in the simulated automatic operation.
4.6 Delay Timer
The three independently ad~ustable timers: on-
delay, off-delay, and generator shutdown, utilize a common
14 stage digital counter. This is device 91~ on Figure 9.
The oscillator associated with a particular timer is gated
on during its timing interval. If either input from the
Voltage Sensor Di5 or the Frequency Sensor Di9 shows an
abnormal condition (logic 0), the off delay oscillator is
gated on at 9E12. The transition to off-delay tlming causes
a counter reset pulse at EXCLUSIVE - OR output 9Fll via
R93/C91. The on-delay output latch NAND 9C is reset and
disabled which allows t~e timing status ~.E.D. to go off and
removes the set signal at pin 9A6 of the generator shutdown
latch. If programming switch PS-6, Delay Generator Start,
is open or lf the generator is already the source of control
power (Dil5 low), the latch is reset. Otherw1se NAND output
9A10 must decode 211 off-delay oscillator periods before the
latch is reset which delays the generator by one-half of the
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1138564 46,672
off-de]a~ time. After 212 oscillator periods (2 seconds to
10 minutes depending on the setting of potentiometer R914
pin All goes low to turn off the oscillator and drive the
off-delay output Do41 low. During timing the status L.E.D.
flashes at a rate of fOff T 64 in response to counter stage
six, pin 9H4. At off-delay time out 9H4 stays low and the
L.E.D. is held off.
On-dela~ timing commences when both frequency and
voltage inputs become normal. The transition to normal
resets the counter via 9Fll. The off-delay and generator
start decoders are disabled, the on-delay oscillator and
latch are enabled. Uuring timlng the L.E.~. flashes at
fon ~ 64 si~ilar to above. After 212 on-delay oscillator
periods (2 seconds to 10 minutes depending on R913) NAND
output 9C3 sets the on-delay latch. Pin 9C10 goes low to
turn off' the oscil]ator, drive the on-delay output Do26
high, and hold the timing status L.F,.D. on continuously.
When the on-delay latch is set at time out, a
logic O on 9Gl enables the generator shutdown decoder and
the logic 1 on pin 9B3 enables the generator osci,llator.
The oscillator is held off until the position circuit Di31
senses that the normal source breaker has closed in resoonse
to the on-delay time out signal. At this time the counter
9H reads 212 or 010 ... O. It requires 212 ~ 1213 periods
of the generator oscillator (15 seconds to 30 minutes depend-
ing on R915) to reach the turnover to all zeroes at which
time 9G9 goes high. This causes output ~o24 to sink current
and turn on a triac on the Main Logic circuit for generator
shutdown. Thus, a maximum generator unloaded cool-down time
three times longer than the maximum on/off delay time is
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113BS64 46~672
possible using the same value capacitors and potentiometers
in the oscillators.
4.7 Tie Breaker Logic
The Tie ~oglc circuit, Figure 10, controls the
shunt tripping and closing of the tie breaker in three
breaker transfer schemes. It may be deleted in two breaker
schemes.
There are four modes of shunt tripping: manual,
interloclc to prevent paralleling sources, lockout from a
faulted bus, and automatic retransfer. The manual trip
input Ti21 directly causes a trip on a logic 0 signal from
its associated AC interface circuit. When the interlock
trip input Ti23 from the Control Logic clrcuit goes low,
breaker closure is immediatel~ inhibited; and after approxi-
mately 20 msec delay from R1010/C103, the TRIP output triac
Q104 is activated. The ground fault or overcurrent lockout
input Ti33 also inhibits closure when low; and if the breaker
ls open (possibly a ground fault or overcurrent trlp), the
TRIP triac Q109 will be energized to override a mechanical
closure until the lockout latch is reset. The automatic
retransfer occurs if both on-delay timers indicate that the
sources are normal (Til5 and Til7 = 1~ and no automatic
transfer closures are requested (Ti9 and Till = 1). The
retransfer is inhibited if the automatic enable is off (Til9
- 0) or if the ~Itie trip inhibit" programming switch PS-2 is
closed (Ti~9 = 1).
In addition to the tie breaker closure to complete
an automatic transfer (Ti9 or Till low~, a manual CLOS~ via
an interface circuit is possible (Til3 low). An~ closure is
inhibited if there is a trip output present, a source paral-
~5-
113~S64 46,672
leling interlock (Ti23 low), an auxiliary lockout (Ti31
low), or a latched lockout from ground fault or overcurrent
(Ti33 low).
In the test mode (Ti25 = 0) the gates of the TRIP
and CLOSE triacs Q104 and Q103 are short-circuited by satu-
rated PNP translstors Q101 and Q102, respectively. No
breaker transfer operation occurs while testing the system.
The TRIP triac Q104 is allowed to operate, however, for an
interlock or lockout trip. A logic 0 applied to pin 2 or
pin 1, respectively, of 10E turns of Q102 to allow the
breaker to trip. Also in the live test mode, the automatlc
enable Til9 is pulsed by the Control Logic circuit to flash
the TRIP or CLOSE L.E.D.'s D102 or D103 in the simulated
automatic operatlon.
4.8 Control Logic
The Control Logic circuit, Figure 11, contains
the control power transfer logic, the interlock circuits,
and the lockout latches. The control power transfer is
based on inputs from the Voltage Sensor circuits indicating
source voltage normal (Vl at Ci4, V2 at C1i7) or source
voltage above 55% (P1 at Ci7, P2 at Cil3) and source #1
greater than source #2 (Pl ~ P2 at Cill). Inputs from the
unregulated DC supplies (Sl at Ci8, S2 at Cil0) are propor-
tlonal to the control power transformer voltage and over-
ride the voltage sensor signals if no control power is pre-
sent because of a blown fuse or a faulty transformer. There
are three conditions for which control power transformer #l
is elected as source of control power.
1) Source ~1 and control power #1 voltages are normal and
either programming switch PS-l is open designating #1 as
-46~
113~S64 46,672
normal source or source #2 voltage is abnormal.
2) Source #2 voltage is abnormal, and source #1 voltage is
greater than 55%, and source #1 voltage is greater than
source #2, and control power #1 voltage is adequate.
3) Control power #2 voltage is off (blown fuse, etc.) and
source #l voltage is greater than 55%.
Source #l if
~Vl Sl (PSl- + V2)~ + [V2 Pl (Pl > P2) Sl]
+ tS2 Pl] = CPl
When any of these conditions becomes true, capacitor Clll is
rapidly discharged by NAND llF3 through Dllll to turn off
transistor Q112 and the triac Q43 (Fig. 4) for control power
source #2. Capacitor C112 is charged to a logic 1 by NAND
llG3 through Rll9 ln not less than one-half cycle of the
llne to allow commutation of source #2 triac Q43 before
translstor Qlll turns on to flre source #1 triac Q43
(Flg. 4). For condition 3 the unregulated DC supply con-
nected to Cil0 becomes less negative than Vss upon the
failure of lts associated control power source. Transistor
Q114 turns on and overrides the source #2 normal signal.
For control power transfer purposes V2 = 0. Similarly
NOR llC13, then inverter llA10, goes to logic 1 with resistor
R1120 providing positive feedback. This enables NAND llE10
to cause a turn-on of source #l triac if source #l voltage
is above 55%, Pl = 1.
The three conditions for which control power
transformer #2 i5 elected as source of control power are
slmilar to above.
1) Source #2 and control power #2 voltages are normal and
either programming switch PS-l is closed designating #2 as
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~13~56~ 46,672
normal source or source #l voltage is a~normal.
2) Source #1 voltage is abnormal and source #2 voltage is
greater than 55~ and source #2 voltage greater than-~ource
#1 and control power #2 is adequate.
3) Control power #l voltage is off, blown fuse, etc., and
source #2 voltage i8 greater than 55~1 and control power ~2
voltage ls adequate.
Source #2 lf
[V2 ~ S2 ~ (PSl + Vl~] + [Vl ~ P2 (Pl ~P2~ S2~ + Sl -
P2 S2] = CP2
If the control power is on either CPl or CP2 islow and NAND output llGll enables the interlock circuit NAND
llB. A low output to a Main or Tie Logic circuit causes an
lnterlock trip of the associated breaker if the other two
breakers are closed. The inputs Ci27, Ci25, and Ci23 of llB
are drlven by AC interface circuits using 120 volt control
power to sense the status of a normally closed auxiliary
contact of the tie breaker, main breaker #1, and main breaker
#2, respectively. With the breaker main contacts open~ the
AC lnterface is energized and a logic 0 is fed to the inputs
of the interlock NAND llB.
Ground fault Ci36 and overcurrent Ci38 lockout
inputs set the latches of llD on a logic 0 from interface
circults. The high output from a set latch drives Co40 low
via NOR llC10 and drives a buffer inverter to light the
ground fault or overcurrent L.E.D.'s D1113 or D1114. The
lockout reset AC input Ca35 is similar to the AC interface
circuit but has a longer tlme constant R116~C115 to insure a
reset condition on power-up.
The automatic enable output Co9 goes low to disable
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~138S64 4~,672
automatic operation on a low input from the interface circuit
connected to the MANUAL terminal of the mode selector switch
Ci31 or is pulsed low by the oscillator consisting of resistor
Rllll, capacitor C113, and a half of NOR llC. The oscillator
is gated on by a low input Ci41 from the live test mode
interface circuit. This pulsed enable signal causes the
TRIP and CLOSE L.E.D.'s of the Main and Tie circuits to
flash when the system is in the live test mode.
4.9 AC Inter~ace Circuits
All connections to remote switches or breaker
auxillary contacts are made through interface circuits
operating on the 120V, AC control power. There are nine
circuits on each module, each using one-third of a hex
bu~fer. The description refers to the first circuit in
Figure 12. When AC input Ia5 is not energized, caPacitor
C121 1B charged through resistor R129 to a logical 1.
Hysteresls ls provided by R121 and R1228. Output Io4 is
low~ and Iol3 is high.
When 120V, AC control power is applied to Ia5 with
respect to ground, C1210 charges negatively through diode
D1210. Voltage divider R1237 and R129 pulls C121 down to
logic 0. Diode D121 clamps the signal at Vss Output Io4
goes high~ and output Iol3 goes low. Resistor R1210 provides
su~ficient loading to prevent pilot contact leakage from
appearing as a closed contact. A delay in output switching
Or greater than 50 milliseconds is seen when the AC input is
removed,
5. Mechanlcal
As seen in Figure 13 the complete Automatic Transfer
Control 12 consists of a power supply circuit board 102, a
-49-
1138S64 46,672
rack 104 holding twelve plug-in printed circuit modules 106,
four barrler terminal strips 108 (only two of which are
shown), a programming switch array (not shown), and the
interconnecting wiring. Two of the modules, the Tie Breaker
Loglc and the Control Logic, are used singly. The Frequency
Sensor, Voltage Sensor, Main Breaker Logic, Delay Timer, and
the AC Interface Circuit modules are used in pairs, one
associated with each of the main circuit breal{er. Figure 13
shows the ATC with the full complement of modules. The
faceplate lenses wlth descrlptive text are back-lighted by
previously described light-emitting diodes to indicate the
operating state of the ATC. For two-breaker transfer schemes,
the Tle Breaker Logic module is simply omltted or replaced
by a dummy module for front panel appearance. One or both
Frequency Sensor modules may be similarly omitted. The less
llkely omisslon of other modules requires that the logic
outputs of the omitted module be replaced by Jumpers on the
backplane wirlng or on a dummy module.
6. Summary
With the versatility offered by programming switches,
auxlliary lnputs, and a wide range of frequency, voltage,
and time delay settings, the Automatic Transfer Control is
useful in a wide variety of transfer schemes. Sales personnel
can lead customers and their consulting engineers through
the "deslgn" of transfer schemes by selection of the various
optlons available. More accurate estimates of the cost of
transfer schemes are possible, especially in the complex
transfer schemes, and considerable savings in engineering,
drafting, and wiring costs are obtained.
Speclfically, by providing programmable electronic
-5o-
113~564 46,672
digital logic means the invention provides a single device
applicable to a wide variety of transfer strategies while using
a minimum of power. Two- and three-breaker schemes are easily
implemented since breaker status information is sensed from
auxiliary contacts having a status opposite that of the main
contacts. A plurality of timing functions are economically
provided through the use of a plurality of oscillators coopera-
tlng with a single digital counter. The use of 120V AC interface
clrcuitry provides high noise immunity while simplifylng instal-
lation. Additional flexibility is provided through the use ofseparate voltage sensors to determine which source to draw upon
for control power and by employing a control power criterion of
55% of rated normal voltage. The provision for auxiliary trans-
fer lockout, overcurrent lockout, ground fault iockout, automatic
or manual return to either source, a "Keep Last Source" mode,
and a live test mode in the present invention combine to provide
a signific~nt increase in performance and versatility over prior
art automatic transfer control devices in an efficient and econo-
mic manner.
