Note: Descriptions are shown in the official language in which they were submitted.
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This application is a division of our Canadian Patent Application
Serial No. 322,004 filed ~ebruary 21, 1979.
This invention relates to analyzing electrical circuit boards, e.g.,
to identify an integrated circuit which has failed.
In testing circuit boards it is desirable to be able to identify
individual elements which have failed without having to disconnect the elements
from the circuit. Circuit faults can be detected by voltage and waveform
measurements, but when several elements are connected to a point it is difficult
to identify, e.g., which element has short circuited to ground. Current tracing
and measurement methods may locate the failed element but generally require
successive measurements to be made at various points between elements, which
can be difficult when conductive paths between the elements are short.
It is also desirable to be able to test individual elements by making
the necessary contacts with the circuit at positions on the board which are
readily located by unskilled operators, e.g., on a lead of an element rather
than at specified positions on the lands when the elements are closely spaced or
the lands occupy both sides of the board.
According to a broad aspect of the invention there is provided, in
electrical circuitry for measurement of low level ac signals during testing of
an electrical element, comprising a three tip probe, and measurement circuitry
connected to said probe to make successive voltage measurements between selected
pairs of said tips while during each said measurement an ac test signal is
injected into said element through the tip not in the then-selected pair, that
improvement wherein the output cable from said probe to said measurement circuit-
ry comprises four wires arranged in two twisted pairs, one said tip is connected
to a said wire in each said twisted pair, and the other two said tips are
respectively connected to the remaining two said wires.
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In a preferred embodiment, the spaced contact tlps span a total
distance of no greater than 0.08 inch, so as to reliably fit on the straight
portion of a mounted IC lead. The test current is separate from the normal
operating current of the board and is in~ected directly into the lead through
a third probe tip, which may contact a point on the lead electrically in
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common with that contacted by one of the other tips. The third tip contacts
the lead at a point farther from the IC than the othcr two tips, so that the
measured test current is Mowing into the ICo Circuitry is provided to
monitor the electrical contacts between the probe tips and the lead.
An embodiment features providing a probe with at least two tips
spaced generally as above set forth, injecting a test signal directly into
the lead via the probe, measuring the voltage drop across a lead segment
produced by test current flowing into the IC, also measuring the voltage
drop across a lead segment produced by test current flowing away from the IC,
and determining the ratio between the internal resistance Rl of the IC on
the lead and the parallel resistance R2 of the remaining IC's on the node,
which ratio is independent of the resistance of the lead segment. This is
also useful for measurements made on circuit board lands.
~ mbodiments feature~ in another aspect, providing a probe having
at least three equally spaced tips arranged to simultaneously contact the
straight portion of a mounted IC lead, injecting a test signal through the
tip nearest the IC and measuring the voltage drop between the other two
tips due to the current component flowing away from the IC through a first
lead segment, injecting a test signal through the tip farthest from the IC
and measuring the voltage drop between the tips closest to the IC due to the
current component flowing into the IC through a second lead segment equal
in length to the first. The ratio Rl/R2 is thus easily and efficiently
determined. In preferred embodiments each tip is a single element tip,
and thc three tips span a total distance of no more than 0.08 inchO
In yet another apsect, the invention features determining the total
parallel resistance Rt at the node by injccting a test signal into the lcad
and making at least one voltage measuremcnt thereon~ detcrmining the ratio
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~/R2 by injecting at least one additional test signal into the lead and meas-
uring the voltage drops due to test current components flowing in opposite
directions through the lead, whereby the absolute values of Rl and R2 may
then be determined. In preferred embodiments, with the circuit board
powered up, and using the three tip probe, a four step procedure is carried
out with a single placement of the probe: first, using one probe tip, node
~ ~ voltage is measured without injecting a test signal; second, using the
s same tip, a dc test signal of known current is injected and node voltage is
again measured, the voltage difference between the first two steps being the
resu~t of the test current flowing through the combined parallel resistance
' Rt and enabling determination thereof, and third and fourth, injecting ac
test signals and measuring the voltage drops across equal length lead segments
due to test current components flowing in opposite directions, to determine
Rl/R2 as described aboveO Highly sophisticated diagnosis of circuit board
faults is thus made possible.
; In yet another aspect the invention features using injected test
signals in the below 10 milliampere range (the range preferably including
currents as low as O.I ,ua) to produce measured voltages in the microvolt
range and below (the range preferably including voltages as low as 30 nv),
¦ 20 all so as not to interfere with normal operation of the powered up board and
thus to expose faults not otherwise easily detected. Preferred embodiments
of the signal processing circuitry capable of accurately handling such low
signal levels feature, for the ac signals, coupling the probe to a synchro-
; nous detector through a transformer.
In yet another aspect the invention features monitoring the contact
between the probe tips and the lead during thc testing by comparing the signal
outputs of selcctcd pairs of tips and indicating whetllcr the comparison is
as expcctcd~ In prefcrred embodiments a special ac signal, differing sub-
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stantially in frequency from the ac test si~nal, is injected in 180 phase
shifted versions into two tips, so as to cancel in the probe output if both
tips are in good contact with the lead.
Aspects of the invention can also be useful for measurement made on
circuit board lands.
In still another aspect, the invention features estimating whether
there is an active driving IC on the node by determining Rl for at least one
IC on the node, and the R2 corresponding to that ~, and comparing Rl or
R2 (preferably the smaller) to a value K selected to be no smaller than the
expected driver resistance Rd for the type of IC being tested.
In another aspect of the invention, after determining that an
active driver is most likely present on the node, an Rl larger than R2 is
selected as faulty if node voltage is too high, and an Rl smaller than R2
if node voltage is too low.
In yet another aspect of the invention, the possibility of a short-
ing resistance is evaluated by determining whether the ratio Rl/R2 is outside
a range bounded at one end by the ratio Rs/Rd (and preferably at the other
end by Rd/RS), where Rs is a selected limit for the expected value of short-
ing resistance being investigated. In preferred embodiments for TTL and
ECL logic ICs, a range of 0.2 to 5 is used to test for a shorting resistance
between an input IC and the internal supply voltage of the IC, and a range
of 006 to 1.6 is used to test for intermediate value shorting resistances
causing a node voltage that should be low but is held higho In the former
case, if Rl/R2 is outside the range 0.2 to 5, Rl is selected as fa~ty if
smallcr than R2. In the latter case (iOe., the test for intcrmediate value
shorting resistances), which is inyestivated after dctermining that the
fault probably is not in thc driver and is not a shorting resistance between
an input circuit and internal supply voltage, an Rl larger than R2 is selected
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:li442;~7
as fa-~ty if Rl~'R2 is ~iithin the range 0.6 to 1,6, and an ~ smaller than R2
is selected if Rl/R2 is outsidethat rangeO Finally~ if none of the above tests
are positive, an Rl larger than R2 is selected as faulty if node voltage is
intermediate but should be low, and an Rl smaller than ~ is selected if node
voltage is low or intermediate but should be high.
In a preferred embodiment~ the signal to noise ratio is improved
in a transformer coupled circuit by inserting, between the transformer and the
synchronous detector, a wide band amplifier for amplifying both the informa-
tion signal and noise present in the transformer output, without substantial
band limiting, followed by a filter having a passband of width intermediate
those of the amplifier and the synchronous detector and centered on the
, clock frequency of the detector, preferably the amplifier has a gain-band-
i width product of at least 5MHz~ the filter passband is no wider than 10% of
said clock frequency, and the synchronous detector has a bandwidth no greater
than 15 Hz.
In preferred embodiments the signal to noise ratio in transformer
coupled systems is improved by using coaxial cable for the transformer
primary with the outer shield grounded to provide an electrostatic shield,
and using an output cable from the probe in which four wires are arranged
in two twisted pairs, one tip is connected to a wire in each pair, and the
other two tips are respectively connected to the remaining two wires; pre-
ferably, the twisted pairs are individually shielded, and a switch is pro-
vided to selectively connect either of the wire pairs (and hence two tips)
across the transformer primary, while an ac test signal is injected into an
IC lead through the third tip~ -
In preferred embodiments, the probe features a contact elementresiliently biased in a rest position with a portion of itself spaced from
a support and movable to an operating position against the support, the
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element tips beinO coplanar in thc opcrating position; the probe features
contact elements having end portions oblique to an axis of the support and
having peripheral edges at their ends for contacting the lead with the
axis parallel to the lead; and two L_shaped torsion spring contact elements
and one beam spring contact element are mounted in grooves in the support.
~ e turn now to a description of the circuitry and operation of a
preferred embodiment of the invention, in conjunction with the accompanying
~; drawings, in which:
Figure 1 is an isometric view, broken away, with a portion
enlarged, of the probe.
Figure 2 is an enlarged view, partly in section, of the front end
of the probe pressed against an integrated circuit lead part of which is
broken away
Figure 3 is a block diagram showing the probe in conjunctiqn with
signal processing circuitry.
Figures 4-6 are schematics of detailed circuitry used in the
embodiment of Figure 3, Conventional electrical symbols are used, and points
electrically in common are indicated by letters enclosed in circles.
Figure 7 is a schematic of the circuit used to drive the relays
of Figures 3-6.
Figure 8 is a schematic of the power supply filter circuitry.
Figure 9 is a diagrammatic view illustrating how the internal
resistance of an integrated circuit may be determinedO
Figure 10 is a flow diagram illustrating the operation of a pre-
ferred circuit analysis systcm including the embodiment of Figllre 3
Figurc 11 is a block diagram of another embodiment.
Figure 12 is a block diagram of anothcr embodimcnt.
Figure 13 is a diagrammatic view of an alternate probeO
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Probe
Referring to Figures 1 and ~, probe 10 has Lexan (trade mark)
support 12 forming handle 14 and tapering along axis 15 to portiOn 16 which
is 0.13 inch wide and 0.25 inch long. Portion 16 has reinforcing ridge 18
on its back, which may be cut off if necessary (e.g., to fit between
i~t adjacent integrated circuits) and standoffs 20 and 22 extending O.OlO inch
from its end. Support 12 has L shaped grooves 24 and 26 and straight groove
28 extending from sockets 30, 32, and 34 to portion 16, with groove 24
extending to and across the end of the support. The short leg of groove 26
is spaced 0.030 inch from the short leg of groove 24 and the end of groove
28 is spaced 0.030 from the short leg of groove 26. The grooves are 0.015
inch wide and 0.015 inch deep over most of their length with rounded bottoms,
and decrease in depth across the short legs of grooves 24 and 26, and over the
last 0.17 inch of groove 28, to zero at their ends. The grooves are inter-
rupted, between the sockets and portion 16, by rectangular recess 290
I Lexan retainer 36, which has recess 37 identical to and opposite recess 29,
s and lexan cover 38, are screwed to support 12.
Torsion springs 40 and 42 and beam spring 44 (each of 0.015 inch
cupro-nickel wire~ are mounted in block 45, which in turn is fitted into
recesses 29 and 37, so that the springs lie in grooves 24, 26, and 28. The
springs are bent at 90 to fit into sockets 30, 32, and 34, which are
standard lead sockets (e.g., AMP, Inc. No. 331810~. Wiring cable 52 (contain-
- ing cables 102 and 104 and wires 45, 48, and 51 shown more particularly in
Figure 3) is connected to the soclcets and thc wires pass between support 12
and cover 38 to external circuitry, being anchored in place by conventional
strain relicf mcasures (e.g., tie-straps passing throuoh holes in support
12 and around the wires). Thc springs, as shown in Figure 2, are longer
than thc grooves so that ends of the springs cannot be pressed below the
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i
surface of portion 16 and contact tips 54, 56, and 58, formed by the circum-
ferential edges of the springs, will in use (as explained below~ contact
integrated circuit lead 60. Tlle tips are equally spaced 0~030 inch apart
and, when the tips are fully depressed by the lead 60 (Figure ~)~ are
coplanar and in a straight line. Ends 62, 64, and 66 of the springs form
30 angles with the face of portion 16 when not depressed. Ends 62 and
64 are each 0.06 inch long (centerline distance), end 66 is 0.17 inch longO
Shafts 68, 70, and 72 generally extend along axis 15. Shafts 68 and 7~ are
0.75 inch long, and shaft 72 is 0.64 inch long. Thus, all three springs
have conductive paths of equal length and resistance. The overall probe
is 5" long.
Circuitry
t
i Referring to Figure 3, inputs are provided to probe 10 by test
signal generator 73 and 10 KHz generator 74, whose + output 76 is connected
directly to tip 5G through wire 48 and whose - output 78 is connected, as is
output 80 of generator 73, to tip 54 through wire 45 or to tip 58 through
wire 51, by DPDT switch 840
Generator 73 has selectable, positive and negative, 1 KHz square
wave, and dc, current outputs at 0.1, 1.0, and lOma. Referring also to
Figure 4, output 80 of generator 73 is provided by positive and negative
current gates 86 and 88, which receive inputs from positive and negative
current generators 90 and 92, and 1 KHz oscillator 96 and from computer 98
inputs 142.
Test outputs from probe 10 are provided to computer 98 through
SPDT switch 100 along onc path consisting of cables lO~ and 104, DPDT
mcasuremcnt select switcll 106, transformer 108, amplifier 110, filter 11~,
and synchronous detcctor 114; and along another path comprising input 115
of switch 84 and amplificr 116.
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237
Cables lO~'f and 104 are twisted, individually shielded pairs with,
' as sho~m, tips 54 and 56 connected to switch 106 by, respectively, wires 46
f and 47 of cable 102, and tips 56 and 58 by, respectively, wires 49 and 50
of cable 104. ~lus wires 47 and 49, which connect tip 56 and switch 106,
are carried separately as one of the wires in the twisted pair in each cable.
f This cable construction reduces cross talk and noise pickup.
I Switches 84, 100, and 106 are shielded relays. The coil of switch
ff ~f
Rf - 106 is connected to ground to reduce coil noise in the relay. Transformer
f'f 108 is individually Mu metal shielded, and has a turns ratio of 6:3000;
input winding 118 is made of coaxial cable with the outer shield grounded
f to provide an electrostatic shield. Further shielding is provided by placing
~ elements 106, 108, 110, 112, 134, and 136 together in a Mu metal box, and by
¦ filtering the supply voltages to this circuitry.
I Amplfifier 110 is a high speed impedance matching buffer having an
¦ input impedance of greater than 10 Meg ohms and a gainband with product of
ff 6 M~z. Filter 112 is a bandpass filter centered on 1 KHz and having a
bandwidth of 100 Hz.
~ Detector 114, which functions as a phase sensitive bandpass filter
! eentered on 1 KHz ~ith a bandpass of 4 Hz, has one signal path from buffer
amplifier 120 directly to swnming point 122 and another through inverter
124 and chopper 126, which is clocked by the test signal through level
shifter 128. The signal then goes through averager 130 to switch 100.
Level shifter 128 shifts output 80 from a floating test signal to a ground
referenced cloclc.
Amplifier 116 is a dc amplifier with a gain of 1/2.
Probe placement signals are provided to indicator 131 and, through
latch 132, to comp~lter 98 (to confirm that the three contact tips are malcing
electrical contact with the lead) by gate 133, which has inputs from ampli-
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4237
fier 110 throu,,h 10 KH- detector 134 ancl 1 l~lz compar~tor 136 which, in turn,
receives inputs from winding 118 and generator 73.
Outputs 138, 140, 142, 144, and 146 from computer 98 control the
circuitry sho~n in Figure 3.
The follo~Ying table contains the circuit components used in the
circuitry shown in Figures 4-8, except for resistors and capacitors, whose
values are given in Figures 4-8. All resistors are 5%, 1/4 watt carbon
resistors unless otherwise noted. All capacitors are standard, commercial
capacitors; those with values between 1.6nf and lOnf are film capacitors,
10 those with values between 33pf and 200pf are mica capacitors, those with
values between .Oluf and .22uf are ceramic capacitors, and those with
values between 15uf and 390uf are tantalum capacitors.
Coml~onent Table
Ul oscillator, Motorola, Inc. K1114A lO~lz
U2-U5 SN74LS192
U6, U7 SN74LS74
U8-U14, U22-U24 SN74LS02
Ul~-U20 SN74LS04
U21, U25, U26 SN74LS38
Al-A10~ A12, A14-A18 operational amplifier, L~1201A
All operational amplifier, LM311
A13 operational amplifier, LM218
Dl-D5, D7, D9-D24, D27 Fairchild, Inc. FDH6626
D6, D8, D25, D26 IN5060
Zl-Z3 602v Zellcr, IN828A
Xl, X2 stabistor, General Electric CorpO STB7 '2
Ql-Q3, Q13, Q18, Fairchild, IncO S39395
Q19,
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Q10-Q12, Q15, Q17, Fairchild, Inc. S39394
Q20
Q7-Q9, Q14, Q27 Motorola, Inc. SS557
Q4-Q6, Q16, Q23-Q25 General Electric Corp. X32D6880
Q21 4 ampere Darlington, 2N6036
Q22 4 ampere Darlington, 2N6039
Q26 FET, 2N4416
TRl-TR4 Selected resistors, 50K-lSOK
Kl-K3 Relay, General Electric Corp. 3SCV5004Dl
Tl~ T2 Custom Choke, 350UH
Transformer 108 6:3000 Transformer, Arnold, IncO
#6T-5651-Hl ferrite tape core; primary
made of 6 turns 50 Qcoaxial cable with
shield grounded~
In the embodiment of Figure 11, probe 300 has two measuring tips
302 and 304, each having a Kelvin-related forcing tip 306~ 308, making con-
tact with lead 310 of IC 311 on both sides of lead segment resistance 303.
Tips 306 and 308 are connected to the output of ac test signal generator 31
through switch 314 which is controlled by the output of switching generator
316. Tips 302 and 304 are connected to the input of synchronous detector
318, which receives a clock input from generator 312, and the output of
detector 318 is applied to synchronous detector 320 which receives a clock
input from generator 316, to provide dc output 3220
- In the embodiment of Figure 12, probe 400 has three tips 402, 404
and 406, equally spaced 0.050 inch apart. Eacll tip is a resilient, canti-
lever spring, bent through a 45 angle, and sharpened to contact lead 408
of IC 410 Witll their points. The tips are, in the rest position, coplanar
with their points lyin~ in a straight line. Test current source 412, which
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provides a 2001na dc test current, is selectively connected to tip 402 or 406
through switch 414. Measurement circuitry 416, for measuring the voltage
between tips, and monitoring circuitry 418, for monitoring the electrical
contacts between the tips and lead 408, are connected through switch 414 to,
respectively, tips 404 and 406 or tips 402 and 404. Circuitry 416 includes
sampling relay 420, transformer 422, and voltage measuring circuit 424, and
circuitry 418 includes pulse generator 426 and pulse detector 428, all of which
are controlled by timing generator 4300
Figure 13 shows an alternate probe with two measuring tips 502 and
504, spaced 0.050 inch apart and a current forcing tip 506 spaced 0.010 inch
outboard of tip 504, Each tip is a rigid needle, and the tips are coplanar
, with their points lying in a straight lineO If used in the system of Figure
12 (eliminating switch 414~, this probe will contact the straight portion of
the IC lead with all three tips simultaneously.
Operation
Referring to Figures 1-3, with normal operating voltages applied
to the board being analy~ed, probe tips 54, 56, and 58 are placed against
lead 60 of integrated circuit 148 to be tested, with standoffs 20 and 22
resting against the board and straddling the meniscus of the solder joint
between the lead and the board land. The tips are thus positioned along the
straight lead portion between the meniscus and the curve of the lead into the
integrated circuit. Probe 10 is then moved toward the lead until the springs
bottom out against support 12, bringing the tips into a straight line equally
spaced 0.030 inch apart, so the resistances of lead segments 147 and 149
between the tips are equal. In being pressed down, the tips dig into and
slide along the lead surface, scraping corrosion from the lead and insurillc$
good electrical contact. The deviation of tip 54 toward tips 56 and 58, as
the probe is pressed against thc lead, is n~glicsible (particularly as a very
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slight amount of upward play is provided between shaft 72 and retainer 36, and
thc shaft thus bends up sli~htly to accomodate any tendency of tip 54 to move
~ towards the other tips), and tips 56 and 58 rotate in planes parallel to tip
t 54, thereby maintaining the tips at the desired equal spacing even as the
tips wear and increase their contact areas during repeated use. Grooves 24,
26, and 28 positively maintain the lateral position of the tips, contributing
~ to accurate tip spacing.
i,t In the presently preferred embodiment, four testing steps are
then carried out under the control of computer 98 acting through control
inputs 138-146, without physically moving the probe.
In the first step, the voltage normally appearing at tip 58 is
measured, with no test current being injected into the lead, by connecting
~, the input of amplifier 116 to tip 58 through switch 84 and the output of
,?j the amplifier to computer 98 through switch lOOo The voltage measured
is converted into a digital number within the computer by an analog to digi-
tal converter (not shown)0
In the second step, a dc test current is injected into the lead
through tip 58 by generator 73, and, again through amplifier 116, a measure-
ment is made of the resulting voltage appearing at tip 580 Referring to
Figure 4, the polarity (i.e., into or out of tip 58) and magnitude (i.eO,
10, 1, or OOl~a) of the test current is selected by control inputs 142.
The polarity and magnitude of the current are selected, depending upon the
type of element bcing analyzed, thc signal normally present on the lead,
and the total resistance appearing on thc node, to not disturb the normal
operation of the circuit. E.go7 if 5400 scrics logic circuits are being
tcsted, thc currcnt would typically be lma or lOma.
In the third step, the probe outputs from tips 54 and 56 are
connectcd, through switch 106, to windina 118, and the output of detcctor 114
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1:~44237
¦ is colmected through switch loo, to computer 980 An ac test current is
injected into the lead through tip 58 by generator 73 (again selected (10, 1,
or 0.~na) not to disturb the operation cf the circuit), and the voltage
; appearing between tips 54 and 56 due to test current flowing into the inte-
grated circuit through the resistance of lead segment 147 is measured.
The ac voltages appearing between the tips in step 3 (as well
as in step 4 described below) typically range from 30 nv to 10 uv, and the
noise protection features previously discussed, iOeO, the shielding of the
relays and the circuitry, the twisting and shielding of the cabling, and
the construction of transformer 108, together with the circuitry filtering
the supply voltages and the grounding of one end of the switch 106 coil,
allow these voltages to be accurately measured. Accuracy of the ac measure-
ment is also enhanced by the use of an ac test signal and the specific
sequence of transformer 108 as a high gain, low noise amplifier providing
, common mode noise rejection; high speed amplifier 110 to amplify both the
test signal and noise, without substantial band limiting, to useful levels
without distortion which would confuse the characteristics of each; filter
112 to reduce noise in preparation for synchronous detection; and
synchronous detector 114, which effectively eliminates from the measurement
signal all components not identical in frequency and phase witll the injected
test signal. Averager 130 converts the measurement signal into an integra-
ted dc voltage proportional to the 1 KHz component of the measurement
signal. The gain-bandwidth product of amplifier 110 is preferably greater
than 5 ~ Thc bandwidth of filter 112 is selected to be as narrow as
possible, prefcrably no morc than 10% of the center frequcncy, insuring
that the 1 KHz test signal falls witllin the 3 db pcints of thc passband as
the passband drifts with age and tempcrature. ~le bandwidth of detector 114,
which is dctcrmined by averager 130, is selected to be as narrow as possible
_ 14 -
li44Z37
while not req~uring an excessive waiting period for tho measurement, and i9
preferably less than 15 Hz.
In the fourth step, the probe outputs from tips 56 and 58 are
connected, through switch 106, to winding 118, and tip 54 is connected, through
switch 84, to generator 73. The ac test current is injected into the lead
through tip 54, and the voltage appearing bet~een tips 56 and 58 due to the
test current flowing away from the integrated circuit through the resistance
of lead segment 149 is measured.
In each of the four test steps, the placement of probe 10 against
the lead is monitored by two independently operating circuits (described
below) to insure proper electrical contacts (iOe., with resistances less
than 0.10 ohms) between the three tips and the lead.
In the first monitoring circuit, output 76 of 10 KHz generator
74 is connected directly to contact tip 56 while output 78, which is phase
~ shifted 180 with respect to output 76, is connected through switch 84 to
j tip 54 during steps 1-3 and to tip 58 during step 4. If, during each test
¦ step~ the two tips connected to generator 74 are both making proper elec-
trical contact with the lead, both outputswill be present in the lead and
will cancel each other, if one of the tips is not making proper contact,
,,
only one output will be present and, being uncancelled, will pass through
the probe output to 10 KHz detector 134, which will trigger latch 132,
through ORing gate 133, to generate an alarm output to computer 980 The
; latch stores the fact of a probe placement error until released by ackno~
edgement output 146 from the computcr. The output of gate 133 is provided
- directly to indicator 131, located on probe 10, without being stored.
In the second monitoring circuit, one input of comparator 136 is
connectcd through switch 84, to tip 58 durinT steps 1-3 and to tip 54 during
stcp 4, whilc the other input is conncctcd, throuall switch 106, to tip 5G
_ 15 -
Z~7
during steps 1-3 and to tip 58 during step 4. If, during each test step,
the tips connected to the comparator inputs are both making proper electrical
contact with the lead, the same signal will be present on both inputs (i.e.,
A the signal due to normal operation of the circuit, the test signal, if any,
and any uncancelled output from generator 74); if either tip is not
making proper contact, the inputs to the comparator will differ and, if they
~ differ by more than 0.10 volts, comparator 136 will trigger the latch through
!.' gate 133, again pro~iding an indication at the probe.
During test steps 1-3, therefore, the first monitoring circuit
checks tips 54 and~56 and the second circuit checks tips 56 and 58, while,
t, during step 4, the first checks tips 56 and 58 and the second checks tips
54 and 56.
The measurements made in the fourthtest stepsyieldinformation,
relating to the internal resistance of integrated circuit 148, which, as
, described below, is useful in diagnosing and locating faults in the circuit
board. Because the tests do not disturb the normal operation of the board,
faults which are best detected (and in some cases can only be detected) under
normal operation conditions (i.e., with normal operating power applied to
~ the board) can be identified: eOgO, resistors and capacitors whose values
'~ 20 change, capacitors which leak, relays and switches which have excessive
contact resistance under normal operating voltages, transistors or integrated
circuits having insufficicnt gain or excessive leakage currents, and
failed transistors, internal to an integrated circuit, which cause the
input or output transistors of the integrated circuit to appear to be open
or short circuitcdO
Fi~lrc 9 illustratcs onc gcneral approach to determining the intcr-
nal resistancc of integratcd circuit 148~ Resistance Rl rcprcsents that
internal rcsistance whilc R2 represents the combined, parallel internal
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1~4423~7
resistances of all other ICs connected to the same node (i.e., a point
within a circuit co~mon to two or more IC inputs and outputs) as lead 60.
When test current I is injected into lead 60 through contact tip 58,
component Il will flow into Rl and component I2 into R2, causing voltage
Vx to appear at tip 58~ where Vx ~ Il x Rl~I~ x R2, and Rl can be deter-
mined if Vx and Il are known. Where a voltage is normally present on lead
60, e.g., the normal operating voltage of the circuit, Vx is found by first
measuring the voltage at tip 58 without injecting the test current and then
measuring the voltage while inJecting the test current, iOe., the first and
second test described above; Vx is the difference between the two measure-
ments (i.e., the voltage due to the injected test current). Il is deter-
mined from the equation Il = Vl/R147 where Vl is the voltage appearing
between tips 54 and 56 due to Il flowing into Rl through R147, the resistance
of lead segment 147. Vl is determined from the change in the voltage between
tips 54 and 56 due to the injection of the test current, as in the first and
second test steps, or by injecting an ac current at a known frequency (e.g.,
as in step 3) and detecting the voltage appearing between tips 54 and 56
at that frequency. If R147 is known Vl may be calculatedO
However, by using information from all four test steps, one can
avoid having to know the resistances of lead segments 147 and 149 (which
may vary over a range of ten to one, depending upon the lead material)O ~le
total resistance appearing at probe 10 (iOe., the parallel combination of Rl
and R2) is determined from the information gained in the first and second test
steps by solving the equation Rt = Vx/I; where I is the test current
(i.e., I = Il + I2); Vx is~ again, the difference between the voltages
appearing at ~ip 58 duc to the injection of the test current, and Rt = (Rl
x R2)/(N ~ R2). ~ecause R147 and N49 are equal, due to the geometry of
contact tips 54, 56, and 58, the equations Vl = Il x R147 and V2 = I2 x R149
_ 17 -
-` liA~237
may be solved to give Il/I~ = Vl/V2. Vl is determined during the third test
step by measuring the voltage appcaring between tips 54 and 56 due to Il
with the test current injected through tip 58, and V2 is determined during
the fourth test step by measuring the voltage appearing between tips 56 and
58 due to I2, with the test current injected through tip 54. Applying the
law of current division through parallel resistances ~i.e., I dividin~
to become Il through Rl and I2 through R2)~ Il and I2 are expressed as Il -
(I) (R2)/Rt and I2 ~ (I) (Rl)/Rt, which gives the relationship Il/I2 =
R2/Rl, and, applying the relationship Vl/V2 = Il/I2, R2/Rl = Vl/V2.
Therefore, by finding Vl, V2, and Vx, and knowing I, the equations Rl/R2 =
V2/n and Rt =(Rl x R2)/(Rl ~ R2) may be solved to find Rl and R2 without
requiring that the resistances of lead segments 147 and 149 be known.
In the most preferred approach, illustrated in Figure 10, the
value of the total parallel resistance present at the probe (Rt), the ratio
between the internal resistance of the integrated circuit (Rl) and the total
parallel resistances of all other ICs connected to the node (R2), and the
values of Rl and R2, are used to located faults in the board.
If a circuit node is suspected of having a failed integrated
circuit connected to it, the operator places probe 10 on the lead of the IC
selected as most probably being failed, usually the lead connected to the
IC circuit driving (i.e., providing a signal to) the node, if that output
is known, and normal operating voltages are applied to the circuit board.
The first stage in the circuit analysis determines whether there
is at least one effective, active driving circuit connected to the nodeO
The majority of circuit nodes have one or morc driving circuits comlected
to them and one or more load, or input, circuits. The internal resistance
Rd of a driving circuit is typicall~ much lcss than that of an input circuit
(e.g., for TTL or ECL logic circuits a driving resistancc is 130 ohms while
- 18 -
~14423~7
a load resistance is 1.3K ohms), so that driving and input circuits can be
distinguished through their internal resistancesO
In the first stage, computer 98 directs the circuitry of Figure 3
in carrying out all four test steps described earlier to determine the
total parallel resistance (Rt) appearing at the lead and the ratio between
Rl and R2 and, from these, solves for Rl and R2. The computer then selects
the smaller of Rl or R2 and compares that value to a number K which is
selected to be equal to or slightly greater (to allow for tolerance in the
resistance) than the driving resistance (e.g., K = 200 ohms for TTL or ECL
logic). Since R2 is the total parallel resistance of all other ICs con-
nected to the node, it may or may not include an active driving circuit; e.g.,
if R2 consists of N or more load resistances, where N is equal to the ratio
between a load and a driving resistance (e.g., N = 10 for TTL and ~CL logic),
then R2 may be less than Ko This case is not considered, however, as good
design practice requires that no driving circuit be loaded with such an
extreme number of input loads.
If neither Rl nor R2 is less than K, the f~ult most probably lies
with the IC containing the driving circuit for the node, i.e., there is no
active driving circuit present on the node. The computer indicates that this
is the fault and the IC containing the driving circuit must then be located,
e.g., by referring to circuit diagramsO If an active driving circuit is
found (i.e., either Rl or R2 is less than K), the fault is most probably not
a failure ~f the driving circuit (e.gO, an open circuit) but is a failure
in an input circuit, and it is necessary to apply more sophisticated cri-
teria to determine the probable location of the fault, by proceeding to the
second analysis stage.
Thc second stage of thc analysis determines whetllcr the fault is a
shorting resistance between an IC input circuit and the intcrnal supply voltage
- 19 -
.
44237
of the IC (e.g., in TTL and ~CL logic circuits7 a shorting resistance to theinternal 102 volt threshold voltage of the ICs holding the voltage appearing
on the node below 1~8 volts, the logic 0 to logic 1 threshold voltage) by
determining whether the ratio Rl/R2 is outside a range bounded by the ratio
of Rs (as defined below) to Rd, and the reciprocal Rd/Rs. For TTL and ECL
logic~ the preferred bo~mds are 0.2 and 5OOo Rs is selected by deter~ining,
for each possible configuration of shorting resistance, the maximum value
that this resistance could assume and still effectively cause the fault
symptom to appear. In general, a ~ 20% range around each bound for the
range will give useful resultsO
It was determined in the first stage that there is an active driv-
ing circuit present on the node, so that, e.g., for TTL and ECL logic, the
maximum value of shorting resistance is less than 1/5 of the driving resist-
ance ¦1/5 of 130 ohms, or 26 ohms) if the node voltage is being held below
108 volts. If the fault is located at Rl, the driving resistance will be
part of R2 and R2 will be equal to or less than the driving resistance
(e,g. 130 ohms) so that the ratio Rl/R2 (26/130) will be less than 0.20
If the fault is located within R2, R2 will be equal to or less than the
value of the shorting resistance (26 ohms) and Rl will be greater than or
equal to a driving resistance (130 ohms), so that the ratio Rl/R2 (130/26)
will be greater than 5Ø
Rs is preferably determincd by applying conventional circuit
analysis teclmiques~ iOe., deternnining the actual input and driving circuits
in the type of ICs of interest (cOgO~ by refercnce to a manufacturer's product
catalog); assuming a circuit having one driving circuit driving thc maxim~
allowable number of input circuits; assumil), a shorting resistor of unknown
value conncctcd betwccn the input and the intcrnal supply voltage in one
driving IC; applying ~levenin~s and Norton's cquivalcnt circuit analysis to
_ ~O --
.
li44237
obtain a set of equations relatin~ Rs to the characteristics of the assumed
fault; and solving the equations to find Rs .
In the shortened, appro~imation approach typically applied in the
engineering field, such an analysis would appear as follows:
Referring, e.g., to the circuit of an SN5400 two input NAND gate
shown on pages 3-6 of the Texas Instruments, Inc. TTL Data Book for Desi~n
En~ineers, Second Edtion, it is assumed that the multi-emitter input transis-
tor has failed so that there appears to be a shorting resistor (Rs) connected
between, e.g., input A, and the collector of that transistor. Because this
collector is held at two diode forward voltage drops above ground (through
the base-emitter diodes of the transistor whose base is connected to the
collector of the input transistor, and the transistor whose base is connected
to the emitter of that second transistor), this shorting resistor appears to
be connected between input A and a 102 volt internal supply voltageO The
output of the gate appears as a 130 ohm resistor (Rd) and a diode in series
connected to the 5 volt external supply voltage to the gate when the gate
output is trying to raise the node voltage to a logic "1" (iOe~, 1.8 volts).
The equivalent circuit thus appears as a series connection of a 130 ohm
resistor and an unkno~m shorting resistor (Rs), connected between a 4.4 volt
level (5.0 volts minus a o6 volt diode drop) and a 102 volt level. The
voltage Vn at the junction between the resistors (iOe., the node) is thus
given by the equations below, where Rs is the value of the shorting
resistance,
Vn = 102v + Rs x (404v - 102v)
(130 Q + Us)
The equation is solved to find Rs for a Vn of 1.8 volts, and Rs is found
to be 26 ~ or 0~2 times the 130 ~Idriving rcsistance Rd.
If, therefore, thc computrr finds that the ratio Rl/R2 is less
_ 21 -
1~4237
than 0.~ or greater than 5.0, the fault is most proboably located in the
smaller of Rl and R2, which smaller value contains the shorting resist~nce
(e.gO~ 26 ohms). mus, if Rl is smaller than R2, the computer indicates
that the fault has been located. But if R2 is greater than Rl, the operator
goes to the ne~t lead on the node (unless he is already at the last lead,
in which event the computer indicateS that all ICs are good), and repeats
stage two.
If the ratio Rl/R~ lies within the limits 0.2 to 5O0~ all of the
internal resistances (Rl) on the node are large enough, compared to the
driving resistance, that the fault is most probably not an internal
shorting resistance between the IC input and the internal supply voltage and
further criteria must be applied.
me criteria used in the third stage of the analysis are based
upon the difference between the voltage actually present on the node and
a known voltage expected to be present if there were no fault If the volt-
age present is some inter mediate level (e.gO, between a logic ~0" and a
logic "1") and should be low (e.g., a logic "0"), i~eO, the driving circuit
is attempting to pull the node voltage down to logic "0" but cannot, then
the fault most probably appears as a shorting resistance higher than the
driving resistance between an IC input and the supply voltage to the IC
- (e.g., ~5 volts for TTL and ECL logic). If Rl is this shorting resistance,
Rl will be greater than R2, which contains the driving resistance, and the
computer will so find and indicate the fault has been located. If Rl is
not greater than R2, the operator gocs to the next lead on the node and the
tcst proccdure bcgins again witll the second stage, exccpt that the computer
will indicatc that all IC s on thc node are good if the probe is on the last
lead to be tcstcdo
If thc voltage present is at a low or intermediate level (eOg~, at
~ _ _
1~44~37
lo_ic "0" or betwcen logic "0" and a logic "1") and should be high (e.g., at
a logic "1"), i.e., the driving circuit cannot pull the node voltage up to a
logic "1", then the fault appears as a low valued shorting resistance (com-
pared to a driving resistance) between an IC input and ground. Thus, if Rl
is less than R2, which again contains the driving resistance, the computer
will so find and indicate the fault has been located. If Rl is not less
L~ than R2, the operator goes to the next lead and the test begins agaln with
the second stage, except that the computer will indicate that all IC's in
the node are good if the probe is on the last lead to be tested.
If, however, the voltage present on the node is high and should
be low (e.g., a logic "1" and should be a logic "0"), the fault is not a
high resistance short to the IC supply voltage or a low resistance short to
ground, but some intermediate value of resistance and it is necessary to
apply an Rl/R2 ratio criterion, as was applied in the second stage of the
analysis. The criterion was determined in the same manner as in the second
stage; assuming some configuration of shorting resistance, determining the
range of allowable values of resistance for each configuration that would
cause this fault to appear and, from this, determining the corresponding
ranges for the ratio N/R2. I.eO, the shorting resistance can be part of
either Rl or R2, and the other of Rl or R2 will be equal to or less than
the driving resistance, as discussed in the second stage, so that the short-
ing resistance is limited to be less than 6U% of the driving resistance,
i.e., the ratio N/R2 will be between 0.6 and 1060 If the ratio lies in
the range of o.G to 1.6, the fault is most probably a shorting resistance
larger than a driving resistance and, if the ratio lies outside the rangc
006 to 1.6, the fault is most probably a shortinr- resistance s~aller than a
driving resistallce. The computcr respectively detcrmines whether N is
grcater or lcss than R2 and, if this test is positive, indicates the fault
- 23 _
~44Z37
located. If the test is negative., then, as. described above, the
operator either goes to the next lead or the computer inaicates
that all IC's on the node are good.
Conventional programming techniques. can be used to
adapt the flow chart of Figure 10 to an available computer. The
preferred embodiment, usi.ng the Teradyne M365C computer,
incorporates circuit path tracing and other features found in the
Teradyne Li25 Ci.rcui.t Diagnostic S~stem, for locating a faulty
node prior to practice of the pres~ent ~nvention.
In the em~odiment of Figure 11, ac test current at
frequency fl from test signal generator 312 îs injected into
lead 310 through.switch 314 and tips 306 and 308 alternately.
The alternation between the forcing tips is at a rate f2, less
than fl and controlled by th.e output of switching generator 316.
Voltages mutually phase shifted by 180 thus appear alternately
between tips 302 and 304 due to the components of test current
flowing alternately from tip 308 into resistance Rl of IC 311
and from tip 306 away from Rl and into R2, the combined parallel
resistance of the other ICs on the node. The voltages are
applied to the inputs of synchronous detector
-24- .
~4Z37
31~, to provide a square wave output at frequency f2, wherein the magnitudes
of the positive and negative swings of the square wave represent the voltages
due to the test current components flowing into and away from Rl~ The output
of detector 31S is then synchronously detected by detector 320 to provide dc
output 322 whose magnitude represents the ratio RljR2 and whose sign
indicates which is the larger, e.g., a positive output indicating Rl is
greater than R2 and a negative output indicating Rl is less than R2. The
embodiment sho-rn in Fi~lre 11 thereby determines the ratio Rl/R2 in one co~-
bined measurement step, wherein the measurements are made across a single
segment of lead 310, and without having to know the value of resistance
303.
In the embodiment of Figure 12, probe 400 is placed against the
lead of the IC with the cantilever springs of the probe tips allowing tips
404 and 406 to contact the straight portion of the lead and tip 402 to go
around the bend on the leadO (In some ICs, the straight portion of the lead
may be long enough to accommodate all three tips. But, unlike the case for
the embodiments of Figures 1-10, in this embodiment the inequality in lead
segment length resulting from having the lead bend in one segment while the
other segment is straight does not affect test accuracy because only orders
of magnitude, not specific values, are being measured.) Tip 406 is selected
as an injection tip and connectcd, through switch 414, to source 412, and a
200 ma dc test current is injected into the lead. The voltage appearing
between tips 402 and 404 due to test current flowing into the internal
resistance of the IC i5 applicd to measurement circ~utry 424 tllrough relay
420 and transformer 422, with the relay alternately revcrsing tlle polarity
of this voltage at thc input to the transformcr, so that the voltage at the
transformer input appears as a squarc wave signal. Measuring circuitry 424
t~kes a measuremcnt during cach half-cycle of this square wave (thus cancel-
_ 25 -
11~4Z3~
ling any internal offset in the measuring circuitry), and generates output
432 to provide a general indication of the current flowing into the IC. The
presence of a substantial current flow where none was expected ~lould
indicate a short (i.e.~ too low an internal resistance) in the IC.
Alternatively, tip 402 can be selected as the injection tip and tips 404 and
406 as the measuring tips to provide a general indication of whether there
is a short on the side of the probe away from the IC.
me placement of the probe tips is monitored, during alternate
half cycles, by injecting a pulse from generator 426 into the measurement
tips at the start of the half cycles; if the measurement tips are effective-
ly shorted together through the lead, the pulse is reflected and detector
428 detects the reflected pulse to provide an indication that the tips are
making proper contactO
The two measuring tips and measuring circuitry 416 may be used
alone to gain useful information relating to the condition of IC 410 by
applying operating voltages to the circuit board and exercising the IC (i.e.,
by applying changing input signals to cause a change in the output at lead
408). The change in voltage between the measuring tips due to the change
in the normal operating current flowing in lead 408 can be compared to that
known to appear if IC 410 is not faulty.
If the probe of Figure 13 is used, any injected test current must
go through tip 506, which is too close to tip 504 to serve as a measuring
tip.
Othcr embodiments are witl~n the following claimsO F.g., contact
springs 208, 210, and ~12 of the probc might preferably be made from wire
having a square cross-section, with the contact tips formed at a corner of
the cross-section rather than by a curved edge as appcars in the present
embodiment, possibly further reducing the rate at which tip contact area
- ~6 -
237
increases with welr, and pro~iding a sharpcr tip to dig into the lead.
Further by way of example, in connection with the three stage
diagnostic procedure, useful information can be obtained by carrying out
stage three directly after determining whether an active drive is present,
and even by omittin~ the ratio comparison branch of stage three, although
such a procedure yields a less reliable dia~nosis.
.
,
