Note: Descriptions are shown in the official language in which they were submitted.
Hartman- 1 6
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HIGH VOLTAGE SOLID--STATE SWITCH
Technical Field
This invention relates to solid-state structures
and, in particular, to high voltage solid-state structures
useful in telephone switching systems and many other
applications.
Background of the Invention
In an article entitled "Development of Integrated
Semiconductor Crosspoint Switches and a Fully Electronic
Switching System" by Michio Tokunaga et al, International
Switching Symposium, October 26, 1976, at Kyoto, Japan,
~aper 221-4, there is il~ustrated a dielectrically isolated
all solid-state high voltage switch having an n type bulk
semiconductor body. A p+ type conductivity anode region is
separated from a p+ type conductivity first gate region
only by portions of the bulk of the body. The first gate
region surrounds and contacts an n+ type conductivity
cathode region. A second p~ type conductivity gate region
exists in the semiconductor body and is located in a
portion of the semiconductor body other than between the
anode and first gate regions. ~'he switch is turned on by
injecting or extracting current from one of the gate
regions. Once current flow between anode and cathode
ceases, then the switch reverts to its normally off
blocking state. One deficiency of this structure is that
it is unable conveniently to interrupt existing substantial
current flow between anode and cathode (the output
terminals).
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It is desirable to have an all solid-state switch
much like the one described hereinabove, but in which it
is possible readily to interrupt (cut off) existing sub-
stantial current flow between the output terminals thereof.
Summary of the Invention
In accordance with an aspect of the invention
there is provided a switching device comprising a semi-
conductor body, a bulk portion of which is of a first
conductivity type, a first region located within the body
of a second conductivity type that is opposite that of the
first conductivity type, a second region located within
the body and being of the first conductivity type, a third
region of the second conductivity type the third region
surrounds and contacts the second region, a gate region
lS located within the body and being of the first conductivity
type; the first, third, and gate regions being mutually
separated by portions of the bulk of the semiconductor
body and being contained on a first major surface of the
body, the resistivity of the bulk of the body being higher
than the resistivity of the first, second, third and gate
regions, the parameters of the device being such that,
with a first voltage applied to the gate region, depletion
regions are formed in the body and the potential of the
portion of the bulk below the gate region and above the
dielectric layer is more positive than that of the first,
second, and third regions such that current flow between
the first and second regions is substantially inhibited,
and that, with a second voltage applied to the gate region
` and with appropriate voltages applied to the first and
second regions, a relatively low resistance current path
is established between the first and second regions by
dual carrier injection, characterized in that the gate
region is located essentially directly between the first
region and the third region.
A high voltage solid-state switch in accordance
with an illustrative embodiment of the invention utilizes a
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A high voltage solid-state switch in accordance
with an illustrative embodiment of the invention utilizes a
lightly doped n type bulk monocrystalline semiconductor
body with a heavily doped p+ type anode region, a heavily
doped n~ type first gate region, a moderately doped p type
second yate region, and a heavily doped n+ type region.
The second gate region surrounds the cathode region~ The
first gate region is located directly between the anode
region and the second gate region. In a preferred
embodiment, the semiconductor body is dielectrically
isolated from a polycrystalline semiconductor support
member. In a preferred embodiment the semiconductor body
is dielectrically isolated from a semiconductor support
member which is of n or ~ type conductivity.
In one embodiment the switch is designed to be ~N
and conducting with the anode positively biased with
respect to the cathode. Conduction from anode to cathode
$~ is inhibited or interrupted by raising the potential of the
first gate region to a value which causes depletion regions
to be formed in the semiconductor body and the potential of
the portion of the bulk of the semiconductor body below the
gate region and above the dielectric layer to be more
positive than that of the anode, cathode, and/or second
gate region.
The location of the first gate region between the
anode and cathode regions is a primary factor which
facilitates the current break characteristic of the present
solid-state switch.
The invention is better understood from a
consideration of the following detailed description taken
in conjunction with the accompanying drawing.
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Brief Description of the Drawing
The single ~igure illustrates a high voltage
switch in accordance with the preferred embodiment of the
invention.
S Detailed Description
Referring now to the Figure, there is illustrated
a perspective view of a structure 10 having a planar
surface 11 and comprising a polycrystalline semiconductive
member 12 supporting a monocrystalline semiconductor
bod~ 16 whose bulk is of n type conductivity, and which is
separated from support member 12 by a dielectric layer 14.
A localized first anode region 18, which is of
the p+ type conductivity, is included in body 16 and has a
portion thereof that forms a part of surface 11. A
localized gate region 20, which is of n+ type conductivity,
is also included in body 16 and has a portion thereof which
forms a part of surface 11. A localized third cathode
region 24, which is of the n+ type conductivity, is
included in body 16 and has a portion which forms a part of
surface 11. A region 22, which is of p type conductivity
closely surrounds region 24 and acts as a depletion layer
punch-through shield. In addition it acts to inhibit
inversion of the portions of body 16 at or near surface 11
between regions 20 and 24. Gate region 20 is located
between anode region 18 and region 22 and is separated from
both by n- type bulk portions of body 16. The
resistivities of regions 18, 20, and 24 are low compared to
that of the bulk portions of body 16. The resistivity of
region 22 is intermediate between that of cathode region 24
and that of the bulk portions of body 16.
Electrodes 28, 30, and 32 are conductors which
make low resistance contact to the surface portions of
regions 18, 20, and 24, respectively. An apertured
dielectric covers major surface 11 so as to isolate
electrodes 28, 30, and 32 from all regions other than those
intended to be electrically contacted. An electrode 36
provides a low resistance contact to support 12 by way of a
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highly doped region 34 which i5 of the same n type
conductivity type as support 12.
Advantageously, the support 12 and the body 16
are each of silicon with the support 12 either of n or of p
type conductivity. As shown, electrodes 28, 30, and 32
advantageously overlap the semiconductor regions to which
they make low resistance contact although electrically
isolated therefrom by portions of layer 26. Electrode 32
also completely overlaps region 22. This overlapping,
which is known as field plating, facilitates high voltage
operation because it increases the voltage at which
breakdown occurs.
In the illustrative embodiment, support 12 and
body 16 and regions 18, 20, 22, 24, and 34 are all silicon
and are of n-, n-, p+, n+, p, n+, and n+ type conductivity,
respectively, where the "+" designates relatively low
resistivity and "-" designates relatively high resistivity.
Dielectric layer 14 is silicon dioxide and electrodes 28,
30, 32, and 36 are all aluminum layers.
A plurality of separate bodies 16 can be formed
in a common support 12 to provide in one integrated
structure a plurality of switches.
Structure 10 is typically operated as a switch
which is characterized by a low impedance path between
anode region 18 and cathode region 24 when in the ON
(conducting) state and as a high impedance between these
two regions when in the OFF (blocking) state. The
potential applied to the gate region 20 determines the
state of the switch when appropriate operating voltages are
maintained on the other electrodes. Conduction between
anode region 18 and cathode region 24 occurs if the
potential of anode region 18 is sufficiently greater than
that of cathode region 24 and if ~he potential of gate
region 20 is below that of the potential of anode
region 18. During the ON state holes are injected into
body 16 from anode region 18 and electrons are injected
into body 16 from cathode region 24. These holes and
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electrons are made to be in sufficient numbers to form a
plasma which conductivity modulates body 16. This
effectively lowers the resis-tance of body 16 such that the
resistance between anode region 18 and cathode region 24 is
relatively low when structure 10 is operating in the ON
state. This type of opera-tion is denoted as dual carrier
injection.
Region 22 helps limit the punch-through of a
depletion layer formed during operation between gate
region 20 and cathode region 24 and helps inhibit formation
of a surface inversion layer between these two regions. In
addition, it facilitates gate region 20 and cathode
region 24 bein~ relatively closely spaced apart. This
facilitates relatively low resistance between anode
region 18 and cathode region 24 during the ON state.
Support 12 is typically held at the most positive
potential level available. Conduction between anode
region 18 and cathode region 24 is inhibited or cut off if
the potential of gate region 20 is sufficiently more
positive than that of anode region 18, cathode region 24
and region 22. The amount of excess positive potential
needed to inhibit or cut off conduction is a function of
the geometry and impurity concentration (doping) levels of
structure 10. I'his positive gate potential causes a
cross-sectional portion of body 16 between gate region 20
and the dielectric layer 14 to be more positive in
potential than of anode region 18, cathode region 24 and/or
region 22. This positive potential barrier inhibits the
conduction of holes from anode region 18 to cathode
region 24. In addition, depletion regions are Eormed at
the junctions of anode regions 18 and body 1~ and at
region 22 and body 16. The electric field wi-thin the
formed depletion regions serves to retain holes within
anode region 18 and region 22 and thus limits current flow
between the anode and cathode regions (18 and 24). Gate
region 20 collects electrons emitted at cathode region 24
before they can reach anode region 18.
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During the ON state of structure 10, the junction
diode comprising anode region 18 and serniconductor body 16
becomes forward-biased. Current limiting means such as a
load (not illustrated) are normally included to limit the
conduction through the forward-biased diode. While
structure 10 is in the ON state the potential of the gate
region 20 can be raised above the anode region 18 potential
and current flow will continue between anode region 18 and
cathode region 24 until the portion of semiconductor
body 16 below gate region 20 and down to dielectric
layer 14 is more positive in potential than that of anode
region 18, cathode region 24, and region 22.
One typical embodiment could have the following
design. Support member 12 is an n type silicon substrate,
lS 18 to 22 mils thick to provide mechanical support, with an
impurity concentration of approximately
2 x 1013 impurities/cm3 corresponding to a resistivity
greater than 100 ohm-centimeters. The other dimensions are
dictated by the size and number of bodies 16 to be
included. Dielectric layer 14 is a silicon dioxide layer
that is 2 to 4 microns thick. Body 16 is typically 30 to
55 microns thick, approximately 430 microns long,
300 microns wide, and is of n- type conductivity with an
impurity concentration in the range of approximately 5-
9 x 10 3 impurities/cm3. Anode region 18 is of p+ typeconductivity, is typically 2 to 4 microns thick, 44 microns
wide, 52 microns long, and has an impurity concentration of
approximately 1019 impurities/cm3 or larger. Electrode 28
is typically aluminum, with a thickness of 12 microns, a
width of 84 microns, and a length of 105 microns.
Region 20 is of n~ type conductivity and is typically 2 to
20 microns thick, 15 microns wide, 300 microns long, and
has an impurity concentration of approximately
impurities/cm or larger. Electrode 30 is aluminum,
12 microns thick, 50 microns wide, and 340 microns long.
The spacing between adjacent edges of electrodes 28 and 30
and between adjacent edges of electrodes 30 and 32 is
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typically 40 microns in both cases. Region 22 is _ type
conductivity and is typically 3-6 microns thick, 64 microns
wide, 60 microns long, and has an impurity concentration of
approximately 1017 to 1018 impurities/cm3. Cathode
region 24 is n+ type conductivity and is typically
2 microns thick, 48 microns wide, 44 microns long, and has
an impurity concentration of approximately
impurities/cm3 or larger. Electrode 32 is aluminum,
1 1/2 microns thick, 104 microns wide, and 104 microns long.
The spacing between the ends of regions 18 and 22 and the
respective ends of body 16 is typically 55 microns. The
spacing between anode regions 18 and gate region 20 is
typically 74 microns as is the spacing between gate
region 20 and region 22. Region 34 is n+ type conductivity
and is typically 2 microns thick, 26 microns wide,
26 microns long, and has an impurity concentration of
10 impurities/cm3 or larger. Electrode 36 is aluminum
which is 1 1/2 microns thick, 26 microns wide, and 26 microns
long.
The embodiments described herein are intended to
be illustrative of the general principles of the invention.
Various modifications are possible consistent with the
spirit of the invention. For example, support member 12
can alternatively be p type conductivity silicon, gallium
arsenide, sapphire, a conductor, or an electrically
inactive material. If region 12 is an electrically
inactive material, then dielectric layer 14 can be
eliminated. Still further, body 16 can be fabricated as an
air isolated type structure. This allows for the
elimination of support member 12. Further, the electrodes
can be doped polysilicon, gold, titanium, or other types of
conductors. Still further, the impurity concentration
levels, spacings between different regions, and other
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dimensions of the regions can be adjusted to allow
significantly different operating voltages and currents
than are described. Additionally, other types of
dielectric materials, such as silicon nitride, can be
substituted for silicon dioxide. Still further, the
conductivity type of all regions within the dielectric
layer can be reversed provided the voltage polarities are
appropriately changed in the manner well known in the art.
Still further, an electrical contact can be made to
region 22. Dependent on the resistivity of region 22, the
electrical contact thereto could be made direc-tly to
region 22 or through a p+ type semiconductor contact region
added into a portion of region 22. Region 22 could then be
used as a second gate region of structure 10. It is to be
appreciated that the use of two of the structures of the
present invention with the cathode of one coupled to the
anode of the other and the first gates 20 being common
provides a bidirectional switch which allows alternating or
direct current operation.
