DELTA MODULATION DETECTOR

DETECTEUR DE MODULATION EN DELTA

English Abstract

-77750
A DELTA MODULATION DETECTOR
ABSTRACT
A detector for detecting a delta modulated signal
includes a timing circuit, a counter and a decoder arranged
to detect a delta modulated signal in electrically noisy
environment. The timing circuit is used to provide a timing
signal of a predetermined time interval over which the
counter counts the transitions present in the delta modu-
lated signal. The counter is used for counting the digital
bit occurrences of the delta modulated signal within the
predetermined time interval. The decoder responds to the
timing signal and receives the count signals from the
counter and provides a binary signal of first state when the
count signal indicates the number of bit occurrences of the
delta modulated signal is above a predetermined high level
of count or below a predetermined number of low count and
provides a binary signal of a second state when the count
signal indicates that the number of the digital bit oc-
currences occur between the predetermined high level of
count and the predetermined low level of count. The de-
tector is further provided with a latch circuit which
responds to the output of the decoder and a code detect
signal representing detection of a predetermined code signal
in delta modulated signal. The latch circuit is used to
provide an output signal in response to the binary signal of
the first state from the decoder and the code detect signal
to signify proper reception of delta modulated signal. The
above described detector may be advantageously used in a
receiver for receiving a scrambled or unscrambled incoming
delta modulated digital data signal.

Claims

The embodiments of the invention in which an exclusive
property or privilege is claimed are defined as follows:
1. A receiver for receiving a scrambled or unscrambled
incoming digital data signal, comprising:
a clock signal source for providing a train of clock
pulses at a rate substantially twice the rate of the highest
frequency of the incoming digital data,
a signal form detector responsive to the clock pulses
and the incoming digital data for determining the character-
istics of the data as to whether it is scrambled or unscrambled
data and providing unscrambled signal detect signal and
scrambled signal detect signal,
first switch means responsive to the unscrambled signal
detect signal for passing the incoming digital data to an
output utilization means,
descrambler responsive to the clock pulses for
descrambling the incoming digital data
a second detector responsive to the clock pulses and
scrambled signal detect signal for providing descrambled
digital data detect signal, and
second switch means responsive to the descrambled
digital data detect signal for passing the descrambled
digital data to the output utilization means from the
descrambler.
2. The receiver according to claim 1, wherein said
second detector includes a detector for detecting a delta
modulated descrambled digital data signal, comprising:
a timing circuit responsive to the clock signal source
for providing a timing signal having a predetermined time
interval,
a counter responsive to the timing signal for counting
the digital bit occurrences of the delta modulated descrambled
18

signal during the time interval and providing a count signal
giving the count of the digital bit occurrences of the delta
modulated descrambled signal within a given time period, and
a decoder responsive to the timing signal and
receiving the count signal from the counter and providing a
binary signal of first state when a count signal indicates
number of bit occurrences of the delta modulated signal
above a predetermined high level of count or below a pre-
determined number of low counts and providing a binary signal
of a second state when the count signal indicates the number
of digital bit occurrences fall between the predetermined
high level count and the low level count, and
a latch circuit responsive to the output of the
decoder and the signal form detector detecting the presence
of scrambled digital data for providing an output signal in
the presence of the binary signal of the first state from the
decoder and the signal form detector output representing the
presence of the scrambled data.
3. The receiver according to claim 1, wherein said
second detector includes a detector for detecting a delta
modulated descrambler delta modulation digital data signal,
comprising:
a timing circuit responsive to the clock signal
source for providing a timing signal having a predetermined
time interval,
a counter responsive to the timing signal for
counting the digital bit occurrences of the delta modulated
descrambled signal during the time interval and providing
a count signal giving the count of the digital bit occurrences
of the delta modulated descrambled signal within a given
time period, and
a decoder responsive to the timing signal and
19

receiving the count signal from the counter and providing
a binary signal of first state when a count signal indicates
that number of bit occurrences of the delta modulated signal
above a predetermined high level of count or below a predeter-
mined number of low counts and providing a binary signal of
a second state when the count signal indicates the number
of digital bit occurrences fall between the predetermined
high level count and the low level count, and
a latch circuit adapted to receive the output of the
decoder and a code detect signal representing detection of a
predetermined code signal and said latch circuit adapted to
provide a binary output signal of first or second state in
response to the two inputs from the decoder and the detect signal
as in the following table
<IMG>
wherein
row A represents code detect signal wherein its
absence is noted in the form of logical 0 and its presence
in the form of logical 1,
row B represents decoder output wherein its output
is represented in logical 1 for the binary signal of the
first state and logical 0 for the binary signal of the second
state,
and row C represents the output of the latch circuit
wherein its output is in the form of logical 0 or 1 as
indicated when the two binary input from the decoder and code
detect signal occur and in the form of row C in response to the
sequence as shown in columns I, II, III, IV and V in which the
two inputs A and B take place in sets in succession.

Description

C -, ``\50 ~6~3Z ~`
Field of the Invention
This invention relates to an improved delta modulated
digital signal detector and use of such a detector in a
receiver adapted to receive either delta modulated digital ~r
and analog signal.
Background of the Invention
Increasingly, in recent years communications need is
met by dlgital transmission. This is manifested in the form~~
of delta modulation of input analog signal into a digital
form and then the signal in the digital form is frequency
modulated and transmitted. At the receiving end the fre-
quency modulated received signal is frequency demodulated
and the frequency demodulated signal is received in a proper
manner. If the received signal is in the form of delta
modulated signal, the delta modulated signal is then con-
verted into analog signal by use of a digital to analog
converter.
It is generally known to provide a receiver that can
receive demodulated signal, that is, a demodulated signal in
the analog form or in the digital form. If it is in the ~
digital form, the digital signal is first converted into an~;
analog signal by a digital to analog converter and then the
analog signal is utilized to drive the output means which
may be in the form of audio output.
Typically, the detector for detecting the delta mod-
ulated signal according to prior art includes means for
detecting a predetermined code signal to ~ense the presence
of an incoming delta modulated signal. Upon detection of
such a signal, the incoming delta modulated signal is
converted into analog signal and received.
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~1~6;~,3~ ~.
C~- 750 ~'
Such a prior art detector is often susceptible to t -
failure in that it is not capable of discriminating and _
detecting incoming data in the presence of high level of
noise and tends to detect incoming noise signal as if it is
a valid digital data. Various attempts have been made to
overcome such a shortcoming and usually the attempts have
-
been made in the form of rather elaborate filtering circuit
arrangement to filter out the noise content of the incoming E~
digital data for avoiding false detection. It has been
found, however, that none of the prior art detectors de~
signed t`o detect delta modulated signal in a noisy envi-
xonment is completely satisfactory and require still further
improvements.
Summary of the Invention
?
It is an object of the present invention to overcome
the aforementioned and other shortcomings found in the prior
art delta modulated signal detector.
It is yet another object of the present invention to
provide an improved delta modulated signal detector.
It is yet another object of the present invention to ~v~r
utili~e, in an advantageous manner, an inventive delta
modulated signal detector in a receiver.
The aforegoing and other objects of the present in~
F~
vention is obtained by providing a detector for detecting a
delta modulated signal that includes a timing signal source,
a counter, a decoder and a latch circuit operatively adapted i
to detect the presence of a delta modulated signal in a r
noisy environment in such a way that false detection of
incoming delta modulated signal due to noise is virtually ~
~ar
eliminated. More specifically, in the detector, the timing ' !
signal source is used to provide a timing signal of ,-
~.
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C~~-~ `50 ~6~
a predetermined time interval. The counter is used to
respond to this timing signal and provides a count signal
indicative of the count of the digital bit occurrences of _
the delta modulated signal within the predetermined time , ,-
interval. The decoder is used to respond to the timing
signal and receive the count signal from the counter. The
decoder provides a binary signal of a first state when the
count signal indicates the number of bit occurrences of the
delta modulated signal above a predetermined high level of ~,
count or below a predetermined number of a low level of i
count and provide a binary signal of a second state when the ~,
count signal falls in between the predetermined high level
and low level count. If either of the condition is met,
that is, if the count exceeds the predetermined high level ~-
or falls below the predetermined low level then the decoder
is used to provide an outer signal indicating proper re-
ception of delta modulated signal. The output of the decoder
is used then as a latch signal for operating a latch circuit
to permit reception of the incoming delta modulated signal.
In accordance with still another aspect of the present
invention, the afore described delta modulated signal
detector can be utilized in a receiver in an advantageous
manner to permit the receiver to receive whether it is
frequency demodulated analog signal or frequency demodulated
descrambled digital signal.
The aforegoing and other advantageous features of the
present invention will become more clearly understood from
the following detailed description of illustrative embodi-
ents in conjunction with the accompanying drawings.r~
F
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~6~32
More particularly, there is provided:
A detector for detecting a delta modulated signal
comprising:
a timing circuit for providing a timing signal having
a predetermined time interval,
a counter responsive to the timing signal for counting
the digital bit occurrences of the delta modulated signal
within the predetermined time interval and providing a count
signal giving the count of the digital bit occurrences of
the delta modulated signal within the given time interval,
' a decodex responsive to the timing signal and receiving
the count signal from the counter and providing a binary signal
of a first state when a count signal indicates number of bit
occurrences of the delta modulated signal above a predetermined
high level of count or below a predetermined low level of low
count and providing a binary signal of a second state when the
count signal indicates the number of digital bit occurrences
fall between the predetermined high level count and the low
level count,
a latch circuit responsive to the output of the decoder,
and
a code detect signal representing detection of a pre-
deter~ined code signal, the latch circuit providing an output
signal in response to the binary signal of the first state from
the decoder and the code detect signal.
There is also provided:
A receiver for receiving a scrambled or unscrambled
incoming digital data signal, comprising:
a clock signal source for providing a train of clock
pulses at a rate substantially twice the rate of the highest
frequency of the incoming digital data,
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a code detector responsive to the clock pulses and the
incoming digital data for determining the characteristics
of the data as to whether it is scrambled or unscrambled data
and providing unscrambled signal detect signal and scrambled
signal detect signal,
first switch means responsive to the unscrambled signal
detect signal for passing the incoming digital data to an out-
put utilization means,
descrambler responsive to the clock pulses for
0 descram~ling the incoming digital data,
detector responsive to the clock pulses and scrambled
signal detect signal for providing descrambled digital data
and
second switch means responsive to the descrambled
digital data detect signal for passing the descrambled digital
data to the output utilization means from the descrambler.
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C~-~750 ~ ~ ~ ~ ~
Brief Description of the Drawings ~-
Fig. 1 illustrates a prior art transmitter that pro-
vides delta modulated signal.
Fig. 2 shows, in a block diagram form, a receiver that .
illustrates an inventive use of the delta modulated signal ~?
detector of the present invention. ~æ~
Fig. 3 illustrates, in a block diagram form, the delta
modulated signal detector of the present invention.
Fig. 4 illustrates probability curves of counts
corresponding to the frequency distribution of the delta
modulated signal in the audio band.
Fig. 5 illustrates a truth table helpful in the under-
standing of the operation of the delta modulated signal
detector of the present invention.
Detailed Description
~`
Referring to Fig. 1, there is shown a transmitter that
provides a delta modulated signal. Such a transmitter may
include a delta modulator 11 of a conventional design which
modulates incoming audio signal applied to its input 12 in
response to a clock signal from a clock source 13. The ~:
delta modulated signal may be applied to a scrambler 15.
The scrambler 15 receives the delta modulated digital signal
~rom the delta modulated 11 in response to the clock pulses
from the clock source 13 and provides a delta modulated
scrambled digital signal to the modulator 17. In a typical
situation, the modulator 17 modulates the output of the
scrambler into a frequency modulated signal using a carrier
frequency from a carrier frequency source 19. The frequency
modulated signal is then transmitted via a suitable antenna r
21. The modulation of the input audio signal into delta
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CM-77750 ~ 3~
modulated scrambler 15 and then into FM modulated signal and
then transmission via a antenna as described above is
generally known.
While the transmitter described above is shown to
include use of a scrambler, such a use is optional. Where
security of the transmitted signal is necessary the scram-
bler is generally used. Howevex, in many applications,
where security of the information is not necessary, the
scrambler is not used.
Fig. 2 illustrates a receiver of the present invention.
It includes a receiving antenna 31 which receives the fre-
quency modulated signal from the transmitter. The received
signal is frequency demodulated by a frequency demodulator
33 in a conventional manner. If the incoming signal is
merely frequency modulated signal, upon demodulation by an F.M.
demodulator 33, the output thereof is applied to a suitable
audio output means 35. Typically the audio means may be a
speaker that provides audio output to the listener.
In accordance with the present invention, the receiver
is arranged not only to receive the FM modulated analog
signal but also to receive FM modulated, delta modulated
signal. As illustrated in Fig. 2 the receiver includes a
signal form detector 37 of a conventional design, such as that described in
U.S. Patent 3,995,225 to Paul Henry Horn that determines whether or not the
incoming signal is analog or digital, a clock signal source 38, a descr ~ ler
39, a delta modulated signal detector ~1, a digital to
analog converter 43, switching circuity 45 and 47 opera-
tively connected to provide the detection function, as will
be described hereinbelow. But before the receiver of the
present invention is described further in detail, first the
delta modulated signal detector of the present invention
will be described with reference to Fig. 3.
Fig. 3 illustrates the present inventive delta modu-
lated signal detector in a functional block diagram form.

CM-77750 ~46~3~
As shown in Fig. 3, delta modulated signal detector includes
a counter 51, a decoder 53, a latch 54, a timing circuit 55
operatively connected in the manner shown. The counter 51
receives a delta modulated signal which is in the form of
train of square wave pulses wherein the train of square wave
transitions represent tha incremental delta changes in the
analog signal. The delta modulation may take place at a
predetermined frequency sampling rate such as twice the
bandwith of the analog signal. For example, in the case of
voice signal the sampling frequency at which the input
analog voice signal is delta modulated is set at 6 kHz or
twice the 3 kHz bandwith of the voice signal.
The delta modulated signal that has been transmitted
and received has different energy spectrum characteristics
as shown in Fig. 4 which illustrates the probability of
counts corresponding to the frequency distribution of the
delta modulated signal. It has been found that, in the
absence of voice signal, the delta modulated signal has a
rather high level of energy that is content, at above 4.5
kHz. Theoretically, the spectrum would appear at 6 kllz with
clock frequency of 12 kHz. In real situations, however,
because of the noise, the spectrum shifts downward as
illustrated in wave form 60. With voice signal present the
spectrum tends to spreadout betweèn 1.5 and 4.5 kHz as
illustrated in wave form 61. However, as the noise level
increases, it is found that the energy level tends to
concentrate in the center frequency around 3 kHz while the
energy at the lower and upper levels tends to decrease
as illustrated in wave form 62. Received delta modulated
signals generally tend to have some degree of noise, so it
is important to provide a detector that can detect
presence of incoming digital data in the delta
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3~ ~
C~- '50 t
modulated signal in the presence of some level of noise and ~_~
the detector must be able to discriminate between the noise
and the signal. ~owever, because of the fact that the noise _
is well embedded in the whole spectrum of signal band of the ~
r.`~
delta modulated signal, the discrimination is found to be ;
very difficult. Various attempts have been made according
to prior art to design a sophisticated filter circuitry to
filter out the noise. However, none has been found to be
very satisfactory. According tG yet another prior art, _
active filters have been utilized to eliminate the noise but ~;;
generally they tend to have low sensitivity and, moreover, ~D
require change in the filter, if new clock frequency is
utilized in the detector. Further attempt to refine the
sensitivity of the delta demodulator detector entailed use !`~
of more complex and rather expensive bandpass active ilter.
In accordance with the present invention, the afore-
mentioned shortcomings associated with the use of filters
are avoided. This is rendered possible by use of a network
designed to provide intended functions on a statistical
basis. This is accomplished by utilizing a timing signal
means that provides a timing signal with a predetermined
time period or interval in response to a clock signal pulse
train. ~uch a timing signal is then applied to the counter
51. This is shown in Fig. 3 in the orm of timing circuity
-
55 which applies a timing signal the predetermined time
period to the counter 51. In response, counter 51 will
count the bit occurrences of the delta modulated signal
applied to the input thereof within the given time interval.
The counter is a conventional design that is adapted to ~--
count positive transitions of the incoming delta modulated
digital signal which is in the form of square wave pulse ~w
train within a given time period. The output of the counter
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3~
~-77750
ind~cates the frequency distribution of the delta
modulated signal in the form of counts of the transitions of
the square wave pulse ~rain, and thus the number of bit
occurrences of the pulses in the delta modulated signal.
Statistically, it is found that if the incoming delta
modulated signal does not contain a voice signal, the count
signal will indicate a substantially high level of count of
the transitions, somewhere around 4.5 kHz or higher as illustrated
in wave form 60. But if the signal being received is a voice
or low frequency analog signal that has been delta
modulated, then the count signal is by and large distributed
between 1.5 kHz and 4.5 kHz with a quite bit of energy
present below 1.5 kHz and above 4.5 kHz as illustrated in
wave form 61. It has been found statistically also that, if
the incoming signal is a delta modulated signal that con-
tains a high level of noise, the counter output energy level
is found in the intermediate band around 3 kHz between the
low frequency 1.5 kHz and upper frequency 4.5 kHz, as
illustrated in wave form 62.
The~e statistical distribution of energy spectrum in
the received is advantageously utilized, according to the
present invention, to discriminate noise from signal in the
receiver. Thus, if the energy level in terms of the count
signal from the counter 51 is found to exist above the
predetermined high level spectrum of 4.5 kHz or above, or in
a predetermined low level spectrum of 1.5 kHz or below, then
the incoming signal is deemed noise free and is received as
delta modulated digital signal even though it may contain
some level of noise. On the other hand, if the noise level
is so significant that the energy level spectrum is entirely
between the upper and lower predetermined spectrum, as
evidenced by the count signal, then the incoming signal is
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3;~ ~-
-~7750
deemed to be either noise or data heavily laiden with noise
and not received.
The foregoing principle of the present invention is
embodied in a detector shown in Fig. 3. The detector
includes the decoder circuit 53 of a conventional type which
carries out the aforementioned logical decoding function on ir
the counter output signal from the counter 51 and pro~ides a
binary signal of a first or a second state, for example,
logical l or logical 0. Logical l is provided if the count
signal from the counter indicates presence of energy level
above the predetermined upper level or below the prede-
termined lower level to signify that the incoming signal is
either the carrier signal or the delta modulated signal with
an audio that has been delta modulated. The decoder provides
the binary signal of the opposite or logical O signal in
_
response to the counter signal that indicates that the
incoming signal is highly noisy. This condition is indicated _~
by the energy level of the incoming delta modulated signal
being in the midband between the predetermined upper level
and the predetermined lower level frequency.
Latch circuit 54 is of a conventional design and `rr
performs the following functions: a certain code may be
transmitted by the transmitter designed to signify the fact
that, the incoming signal is a scrambled delta modulated
digital signal. Upon detection of such a code, the code
signal is applied to the latch at the input designa~ed A.
Such a code signal is in the form of signal of either
logical O or logical l depending upon the absence or the
presence of the detected signal. Now the latch performs a c~
logical function in response to the code to the detect
signal and the signal in the form of binary l or O from the
-- 1 0 -- 9~

~6~3~ ~
C~-7-~50
output of decoder 53 designated B. The latch is designed to
1--
operate as a logical circuit element that operates in the
manner shown in a truth table Fig~ 5.
Initially, when no signal i~ present the code detect
signal status, A, and the output of the decoder, B, signify
logical 0, as indicated in Status State I. This is the case ¦ :
.'
when the decoder is yet to receive any incoming delta
modulated digital signal. At this stage, the output of the
latch C is logical O signifying that the delta detector has
not yet detected any delta modulated digital signal. Decoder
53 presents incoming delta modulated digital signal, in the
form of logical 1 or logical O to input B of latch 54
depending upon whether or not the incoming signal is highly
noisy. Suppose at that point the code signal is detected.
This is presented to input A of latch 54 as logical 1. But
suppose the noise content is high in the incoming signal, as
indicated by the count that represent the predetermined band
defined by the predetermined upper level and predetermined
lower level or some other malfunction; this will cause the
decoder to continue to provide logical O to input B of latch
54. Latch 54 will continue to provide logical O output
which signifies that incoming delta modulated signal is L
still unacceptable because of high noise level. This status
state is represented by the Status State II.
Now suppose incoming signal is a delta modulated signal
that is not contaminated by noise or has a level of noise
but not serious as determined according to the statistical ~"~
nature, i.e., incoming signal has energy spectrum above 4.5
kHz or below 1.5 kHz then the decoder provides logical 1,
signifying a proper reception of the delta modulated signal, ~_~
without undue interference of the noise, this logical 1
signal is applied to input B of the latch 54. In turn, the

6~32
latch 54 changes its output to logical 1. This is
illustrated in Status State III in Fig. 5.
As the incoming delta modulated signal is continuously
received, it is advantageous to permit the latch output to
remain logical 1, as illustrated in Status State IV even
though the output of the decoder goes to logical 0 sig-
nifying that the signal is now getting a high level of
noise, so long as the code detect signal from code detector
indicates reception of delta modulated signal. This permits
a built-in latitude in the delta modulated code detector to
continue to receive the incoming delta modulated signal,
once the reception of the delta modulated signal begins to
take place. However, once the code detect signal signifies
termination of the incoming signal delta modulated signal in
the form of change in its binary signal status of logical 1
to logical 0 as shown in Status State V, then the latch
signal changes its output to logical 0. This signifies
termination of the incoming delta modulated signal.
Advantageously, the aforedescribed delta modulator may
be utilized in a receiver designed to receive a delta
modulated signal that may have been scrambled at the trans-
mitter and therefore that may have to be descrambled at the
receiver as illustrated in Fig. 2. It is noted here that
the use of delta modulated signal detector, such as that
shown in Fig. 3, and described hereinabove, can be just as
well utilized in detecting delta modulated signal that has
not been subjected to the scrambling process. This simply
means that the scrambler 15 and the descrambler 39 shown in
Figs. 1 and 2 may be simply omitted. The use of the delta
modulated signal detector shown in Fig. 3 is represented in
the receiver shown in Fig. 2 in the form of detector 41.
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6~3~
The delta ~odulated signal detector of the presen~
invention is usable in a receiver designed to detect delta
modulated digital signal as well as analog signal, as will
be evident from the following description. As illustrated
in Fig. 2, suppose the incoming signal is in the form of
analog signal that has been frequency modulated, the antenna
31 will receive such a signal and will be fre~uency de-
modulated F.M. demodulator 33. The output of demodulator
33 at this point is in the form of analog signal that can be
applied to the audio output means 35 via a switch 47. S~ppose, on the
other hand, the incoming signal is in the form of delta
modulated digital signal that has been scrambled. This will
be received and fre~uency demodulated via antenna 31 and
demodulator 33. The output of demodulator 33, in this
instance, will be scrambled delta modulated signal. Ob-
viously such a signal is not ready for application to output
audio means 35. In accordance with the present invention, the
signal form detector 37 is provided to determine whether or not
the output of the demodulator 33 is in the form of digital signal
or analog signal. This is accomplished by the signal form
detector 37 which determine that the output of demodulator 33,
whether it is in the form of a digital signal or an analogue
signal. Upon detection of the digital nature of the output
of the demodulator, the code signal form detector 37 will
provide two outputs. One in the form of logical 1 output
and apply it to the input A of the latch 54 and the other in
the form of output which may be logical O and apply it to
input A of the switch 47.
In short, upon detection ofa digitalsignal, si~nal form
detector 37 provides the binary signal of logical 1 to the
input A of the latch 54 and an opposite or logical 0 to the
input A of the switch 47. The switch 47 is disposed between
the audio output 35 and the demodulator 33, and is subject

~62~2
M-77750
to control by the output of the code detector. If the signal form
detector 37 detects that the output of the demodulator is
an analog signal, then the code detector outputs is 0 and 1
and applied to terminals A and A. With A being 1, the
switch 47 stays closed. The closed switch 47 will permit
transmission of the audio signal from the output of the
demodulator to the audio application means 35.
~ hen signal form detector 37 detects that the output of the
demodulator 33 is a digital signal, the A output will
change to logical 0 and the other output namely, A will
change to logical 1. When A changes to logical 0, the
switch 47 opens. This opens the path to audio output 35
from demodulator 33 via switch 47. ~onsequently, no
direct application of the output of demodulator to the audio
output means 35 is possible. As noted in Fig. 2, the signal form
detector 37~is driven by the common clock 38. When output
of the demodulator 33 is a scrambled delta digital signal,
the descrambler 39 descrambles it and provides a descrambled
delta modulated signal to the detector 41. The descram-
bler output is in the form of a delta digital signal,
in other words, the output of the descrambler 39 is in the
form of a digital signal.
As illustrated in Fig. 2, the descrambler is driven by the
con~on clock 38 in providing its descrambling function. For
the detector 41, advantageously the delta modulated signal
detector of the present invention, as described with re-
ference to Fig. 3, can be utili~ed. The output of the
descrambler is applied to the counter 51 and the counter 51
is driven by the common clock 38 via a timing circuit 55.
The counter 51 provides its counting function of the tran-
sitions or the occurrences of the pulses found in the output
of the descrambler 39. The decoder in turn will decode the
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~6%3;~
-M-77750
pulse counts and apply logical 0 or logical 1 in its output.
Now in response to the output from the decoder 53 and the
signal form detector 37, latch 54 will operate and provide its
output. As described hereinabove with reference to Fig. 3
in detail, the latch 54 will provide either logical 0 or
logical 1 at its output C, in response to the changes in its
two inputs A and B in the sequence, as indicated in the
Status States I, II, III, IV and V. Restated the code
detector output A provides initiall~v logical 0 indicating
that the incoming delta modulated signal is not yet de-
tected. Ater the signal form detector 37 detects the presenoe of a
digital signal and provides a logical 1 to the latch 54 of
the detector 41 the detector 41 changes its output C to logical
1, as shown in Status State III, if the input sign~i-having energy
spectrum in the acceptable ~requency range, namely, above
the predetermined high frequency of 4.5 kHz or below the
predetermined lower frequency of 1.5 kHz, the detector 41
changes its output to logical 1, as shown in Status State
III.
This causes the logical output of the detector 41 to
apply logical 1 to the switch 45 via path 42. The switch 45
is of conventional design which will respond to logical
signal 1 and close its path. This will provide a path from
the output of the digital to analog converter 43 to the
audio output 35. When this takes place, the output of the
descrambler 39 will be allowed to be applied through the
digital to analog converter 43 and transmitted to the audio
output 35 ~ia the switch 45. So long as the switch 45 stays
closed, that is, as long as the output of the detector 41
remains in logical 1 state, the switch 45 will continue to
provide path for the output of the digital to analog con-
verter 43 so that it can be applied to the audio output 35.
- 15 -

3~ ~
C~-7 `50
Hereinabove a delta modulated signal detector of the
present invention has been described. Also use of such a
detector in a receiver that permits the detection of FM
modulated analog signal or in the alternative, delta modu- K.
lated digital signal, utilizing the detector of the present
invention in a very advantageous manner. Advantageously
with the present inven~ive delta modulated signal detector,
a substantial simplification of code detector, as well as
receiver, is made possible in that complex filter circuitry
is no longer required. Moreover, the present delta modu-
b~
lated signal detector is essentially based on a common clock
and a code detector; so it adjusts itself to any predetermined ~
clock frequency that may be utilized to generate the delta pn_
modulated signal.
Advantageously, the delta modulated code detector of
the present invention can be utilized to function as a i;~
proper code detector in a repeater or in a radio. This is
done by having the output of the detector supplied to an
input of the repeater or the radio. This is obtained
because of the fact that the present delta modulated signal
detector has the characteristics that permits the detector ~`L~` `
to detect initially the presence of incoming signal only ;~
when the signal has been properly decoded. The latch output
which is reset by a code detector or a squelch can be used
to squelch out any message which cannot be properly decoded.
Stated in other words, so long as the decoder 53 does not p~
change its logical output from logical O to logical 1,
thereby signifying the detection of proper reception in
incoming delta modulated code signal, the detector 41 will r--
not provide a logical 1 in its output. In other words, the
detector 41 will continue to provide logical O and this in ~w
turn will cause the logical O to be applied to the switch 45. i~
.
- 16 - ~

2~ ~ ¢
C~-7 750
So long as the logical O signal is applied to the switch 45,
F~
this will prevent the receiver from providing any audio
output at the output terminal 35. ~
Advantageously because of the ability of the delta g
modulated signal detector of the present invention to detect
signal in relatively noisy environment, the reception of
incoming delta modulated signal is improved and can squelch
out undecoded signals. This permits multi code and shared
channel coded/clear systems application of the decoder
attractive. Advantageously also the present delta modulated ~;
signal detector provides a faster recognition time in L
detecting the delta modulated signal than those possible
using the prior art delta modulated signal detectors that
rely on the active or passing filters. 1~
Various modifications and changes may be made to the
present invention by those of ordinary skill in the art
without departing from the spirit and the scope of the
present invention.
~;'`
'~'
r
r :;,
~ - 17 - ~r~