REFERENCE VOLTAGE GENERATOR DEVICE

GENERATEUR DE TENSION DE REFERENCE

English Abstract

Abstract of the Disclosure
The specification discloses a reference voltage
generator device which detects a voltage corresponding to
an energy gap of a semiconductor, or a voltage of a value
close thereto, or a voltage based on an energy level of a
semi-conductor, and generates the detected voltage as a
reference voltage. The reference voltage is generated by
detecting the difference of threshold voltages of first
and second insulated gate field-effect transistors
(IGFETs). Gate electrodes of the first and second IGFETs
are formed on gate insulating films which are formed on
different surface areas of an identical semiconductor
substrate under substantially the same conditions. The
gate electrodes of the first and second IGFETs are respec-
tively made of two semiconductors which are selected from
among a semiconductor of a first conductivity type, a
semiconductor of a second conductivity type and an
intrinsic semiconductor made of an identical semi-
conductor material, and which have Fermi energy levels
of values different from each other. The channels of
the first and second IGFETs have an identical conductivity
type. On the basis of a self-alignment structure, at
least those parts of first and second polycrystalline
semiconductor regions being the gate electrodes of the
first and second IGFETs which are proximiate to source and
drain regions are doped with the same impurity as that of
the source and drain regions, and a central part of one of
the first and second polycrystalline semiconductor regions
is doped with an impurity of a selected one of the first
conductivity type and the second conductivity type.
The reference voltage is applicable to a differential

amplifier circuit and operational amplifier of the offset
type, a voltage comparator, d constant-current circuit,
a voltage regulator, a Schmitt trigger circuit, an
oscillation circuit, a battery checker, and so on. In
particular, the reference voltage generator device is
relatively insensitive to changes of temperature.

Claims

The embodiments of the invention in which an exclusive
property or privilege is claimed are defined as follows:
1. A reference voltage generator device comprising first
and second insulated gate field-effect transistors which
have a difference of threshold voltages corresponding to a
difference of Fermi levels of gate electrodes thereof,
wherein both gate electrodes of said first and second
insulated gate field-effect transistors are made of a
substantially identical semiconductor material and
different from each other in the conductivity types of the
identical semiconductor material; and
means coupled to said first and second insulated gate
field-effect transistors for providing a reference voltage
based on the difference of said threshold voltages of said
first and second insulated gate field-effect transistors
to be utilized as a reference voltage.
2. A reference voltage generator device according to
claim 1, wherein the gate electrode of said first
insulated gate field-effect transistor has its central
part of semiconductor material of N-type while the gate
electrode of said second insulated gate field-effect
transistor has its central part of semiconductor material
of P-type or intrinsic-type.
3. A reference voltage generator device according to
claim 1, wherein the gate electrode of said first
insulated gate field-effect transistor has its central
part of semiconductor material of P-type while the gate
electrode of said second insulated gate field-effect
transistor has its central part of semiconductor material
of N-type or intrinsic-type.
4. A reference voltage generator device according to
claim 2 or 3, wherein the respective gate electrodes of
119

said first and second insulated gate field-effect trans-
istor are made of two semiconductor layers of different
conductivity types selected from a group consisting of a
semiconductor layer of N-type, a semiconductor layer of
P-type, a semiconductor layer whose central part is N-type
and whose both ends are P-type, a semiconductor layer
whose central part is P-type and whose both ends are
N-type, a semiconductor layer whose central part is
intrinsic and whose both ends are P-type, a semiconductor
layer whose central part is intrinsic and whose both ends
are N-type, a semiconductor layer whose central part and
whose both ends are P-type and whose intermediate parts
between said central part and said both ends are intrinsic
and a semiconductor layer whose central part is N-type,
whose both ends are P-type and whose intermediate parts
between said central part and said both ends are intrinsic.
5. A reference voltage generator device according to
claim 1, 2 or 3, wherein the gate electrodes of said first
and second insulated gate field-effect transistors are
made of polycrystalline silicon.
6. A reference voltage generator according to claim 1,
wherein said means coupled to said first and second
insulated gate field-effect transistors comprises current
applying means for applying currents to said first and
second insulated gate field-effect transistors
respectively; and
connection means for deriving the reference voltage
corresponding to the difference of said threshold voltages
of said first and second insulated gate field-effect
transistors.
120

7. A reference voltage generator according to claim 6,
wherein said current applying means comprises current
limiting elements which are connected in series with said
first and second insulated gate field-effect transistors
between a power supply and said first and second
transistors respectively.
8. A reference voltage generator according to claim 7,
wherein said connection means comprises a first connection
means for connecting the gate electrode of said first
insulated gate field-effect transistor to the drain
thereof; and
second connection means for connecting the gate
electrode and source of said first insulated gate field-
effect transistor to the gate and drain of said second
insulated gate field-effect transistor respectively,
whereby the reference voltage corresponding to the
difference of said threshold voltages of said first and
second insulated gate field-effect transistors is derived
from the drain of said second insulated gate field-effect
transistor.
9. A reference voltage generator according to claim 7,
wherein said connection means includes first connection
means for connecting the gate electrodes of said first and
second insulated gate field-effect transistors to the
drains thereof respectively.
10. A reference voltage generator according to claim 9,
wherein said connection means includes second connection
means having a capacitance connected between the gate
electrodes of said first and second insulated gate
field-effect transistors, whereby the reference voltage
corresponding to the difference of said threshold voltages
of said first and second insulated gate field-effect
121

transistors is derived from the drain of said second
insulated gate field-effect transistor.
11. A reference voltage generator according to claim 7,
wherein said means coupled to said first and second
insulated gate field-effect transistors further comprises
a third insulated gate field-effect transistor whose the
drain-source path is connected in parallel with the
drain-source path of said first insulated gate
field-effect transistor, the gate electrode of said third
insulated gate field-effect transistor being applied with
a first timing signal.
12. A reference voltage generator according to claim 11,
wherein said means coupled to said first and second
insulated gate field-effect transistors further comprises
fourth and fifth insulated gate field-effect transistors
whose the drain-source paths are connected in series with
said first and second insulated gate field-effect
transistors respectively, the gate electrodes of said
fourth and fifth insulated gate field-effect transistors
being applied with a second timing signal.
13. A reference voltage generator according to claim 6,
wherein said connection means comprises a first connection
to means for connecting the drain-source path of said
first insulated gate field-effect transistor to the
drain-source path of said second insulated gate
field-effect transistor in series; and
a second connection means for connecting the gate
electrodes of said first and second insulated gate
field-effect transistors to the drain of said first
insulated gate field-effect transistor commonly, and
wherein said current applying means comprises a current
limiting element which is connected in series with the
122

series connection of said first and second insulated gate
field-effect transistors, whereby the reference voltage
corresponding to the difference of said threshold voltages
of said first and second insulated gate field-effect
transistors is derived from the juncture of the series
connection of said first and second insulated gate
field-effect transistors,
123

Description

~1~9~118:a
This invention relates to a reference voltage gener-
ator device as well as applications thereof, and also to
a method of manufacturing the same.
In generating reference voltages in various semi-
conductor electronis circuits, it is necessary to utilize
a physical quantity having the dimension of the voltage.
As such physical quantities, there have until now been
solely utilized the forward voltage drop VF or reverse
breakdown voltage (Zener voltage) Vz of a PN-junction
diode, the threshold voltage Vth of an insulated gate
field-effect transistor (often represented by an IGFET or
MOSFET), etc.
These physical quantities do not indicate voltage
values which are absolutely fixed, since their voltage
values are subject to fluctuations due to various fac-
tors. In order to make use of these physical quantities
for reference voltage generator devices of various elec-
tronic circuits, accordingly, attention must be paid to
the factors which cause the fluctuations of the voltage
values and the allowable limits of the fluctuations.
First of all, the voltages VF and Vth usually
have a temperature-dependency of approximately
2 - 3 mV/C. The fluctuation of the reference voltage
attendant upon the temperature change reaches such a
magnitude that their application has to be given up in
some uses.
By way of example, when a battery checker for pro-
viding an alarm when the voltage of a battery has fallen
below a predetermined reference value is intended to be
realized in an electronic timepiece which employs a silver
oxide battery having a nominal vo~tage of 1.5 V, whether
the battery voltage is high or low needs to be judged with
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~Lg~
the boundary (detection level) or the detection reference
value at about 1.4 V.
When a reference voltage generator device is to be
constructed by exploiting the threshold voltage Vth of a
MOSFET or the forward drop voltage VF of a diode which
is about 0.6 V, the detection level aimed at 1.4 V has a
temperature-dependency of:
4 (V) x {2 ~ 3 (mV/C)} = 4.67 ~ 7.0 (mV/C).
Accordingly, even when the practical operating tem-
perature range is estimated to be as narrow as 0C to
50C, the detection level fluctuates as much as 1.23 V
to 1.57 V, and a satisfactory battery checker cannot be
obtained.
Furthermore, the physical quantities suffer from
dispersions or deviations in the manufacture. For
example, the threshold voltage Vth of a MOSFET has a
dispersion of about +0.2V, which is greater than the
temperature fluctuation. Accordingly, when the above-
stated battery checker is put into the form of an IC
(integrated circuit) by exploiting the voltage Vth,
not only is ~here the difficulty of providing the external
components and external connection pins (external connec-
tion terminals) necessary for adjusting the reference
voltage, but also additional labor is required to carry
out the adjustment after the fabrication of the IC.
The lower voltage limit of the Zener voltage Vz is
about 3 V, and it is impossible to generate a reference
voltage to be used in a low voltage range of 1 to 3 V or
so. When using the Zener voltage or the forward drop
voltage of a diode as a reference voltage, a current of
the order of several mA to several tens of mA needs to be

caused to flow, which is inappropriate from the point of
view of lowering the power dissipation of the reference
voltage generator device.
It is apparent from the above explanation, that
the conventional reference voltage generator devices
exploiting the voltages Vth, VF and Vz have not
alwa~s been suited to all the uses when the temperature
characteristics, the dispersions or deviations in manu-
facture, the power dissipation, the voltage level etc.
are taken into account. For uses requiring very severe
characteristics, it has often been the case that the
practical use or the mass production must be relinquished.
The inventors of this invention have thus appreciated
that improvements in the conventional reference voltage
generator devices are subject to physical limitations and
carried out research in order to develop a reference
voltage generator device based on a new idea or concept.
An object of this invention is to provide a reference
voltage generator circuit based on a new concept and to
~0 facilitate the designs and mass productions of electronic
circuits.
To this end the invention consists of a reference
voltage generator device comprising first and second
insulated gate field-effect transistors which have a
difference of threshold voltages corresponding to a
difference of Fermi levels of gate electrodes thereof,
wherein both gate electrodes o said first and second
insulated gate field-effect transistors are made of a
substantially identical semiconductor material and
different from each other in the conductivity types of the
identical semiconductor material; and means coupled to
i~

`
said first and second insulated gate field-effect transistors
for providing a reference voltage based on the difference of
said threshold voltages of said first and second insulated
gate field-effect transistors to be utilized as a reference
voltage.
Various preferred embodiments of this invention to be
described later and of inventions disclosed herein and
claimed in various divisional applications have the
following advantages:
ln (1) A reference voltage generator device having small
temperature variations can be provided.
(2) There can be provided a reference voltage gener-
ator device in which the fluctuations of the voltage value
to be obtained are small with respect to the fluctuations
in manufacturing conditions, for example, the manufac-
turing dispersions (deviations) among various lots are
quite small.
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r- :
(3) There can be provided a reference voltage
generator device in the form of an integrated circuit
which can diminish the manufacturing dispersions to
such an extent that no adjustment after manufacture is
necessary.
(4) There can be provided an electronic circuit
device in the form of an integrated circuit including
a reference voltage generator device which can be
manufactured with a large tolerance relative to a
specification aimed at.
(5) There can be provided an electronic circuit
device in the form o~ an integrated circuit including
a reference voltage generator device which has a high
manufacturing yield, i.e. a high efficiency percentage.
(6) A reference voltage generator device which is
suited to an IGFET integrated circuit can be provided.
(7) A reference voltage generator device and a
voltage comparator which are of low power dissipation
can be provided.
(8) There can be provided a reference voltage
generator device which can produce a low voltage (o~
or below 1.1 V) of very good precision.
(9) There can be provided a reference voltage
generator device which is suited to a power source of a
comparatively low voltage (approximately 1 to 3 V), for
example, a silver oxide battery of 1.5 V or a mercury
battery of 1.3 V.
(10) It is possible to provide a reference voltage
generato device which is suited to a semiconductor
integrated circuit.
(11) It is possible to provide a voltage comparator

a stabilized power supply device, a constant-current
circuit and a bat~ery checker which have high precision.
(12) It is possible to provide a semiconductor
integrated circuit device for an electronic timepiece
which contains a battery checker oE high precision therein
and which has a small number of external terminals.
(13) It is possible to provide an IGFET integrated
circuit in which the threshold voltage of an IGFET with a
back bias applied thereto can be maintained at a substan-
tially constant voltage independent of dispersions inmanufacture and changes in temperature, whereby the yield
of manufacture can be enhanced.
(14) It is possible to provide a reference voltage
generator device which is compatible with a complementary
type insulated gate field-effect transistor integrated
circuit (CMOS IC) or with an N-channel MOSIC or P-channel
MOSIC, and a method of manufacturing the same.
(15) It is possible to provide a constant-voltage
output circuit which is suitable for making the power
dissipation low. That is, there can be provided a
constant-voltage output circuit which produces a
stabilized voltage with a low absolute supply voltage,
such as the battery voltage, and which has a low power
dissipation.
(16) It is possible to provide a reference voltage
generator device which is compatible with the so-called
silicon gate insulated-gate field-effect transistor
integrated circuit employing silicon for the gate
electrodes, and a method of manufacturing the same.
(17) There can be provided a method of manufacturing a
reference voltage generator device without increasing the

number of fabricating steps in the fabrication of a
silicon gate P-channel IGFET integrated circuit.
(1~) There can be provided a reference voltage
generator circuit which exploits the difference of the
Fermi levels of aluminum and intrinsic silicon, which does
not employ P-type silicon containing a P~type impurity,
such as boron, liable to be introduced into a channel
portion through a gate insulating film and which undergoes
small dispersions in manufacture.
(19) It is possible to provide a method of manufac-
turing a reference voltage generator device which can
prevent an acceptor impurity forming a P-type silicon gate
such as B, AR and Ga from being introduced into a channel
portion through a gate oxide film to change the threshold
voltage of an IGFET whose gate electrode is made of the
P-type silicon.
(20) It is possible to provide a semiconductor memory
which has the function of preventing any erroneous writing
in a data retention mode. That is, when a supply voltage
has become below a set detection voltage, at least one of
control signals required for a writing operation can be
inhibited.
(21) It is possible to provide a Schmitt trigger
circuit which is constructed of MISFETs (insulated gate
field-effect transistors) and whose hysteresis curves have
a width which varies little due to the fluctuations of a
supply voltage, the manufacture dispersions of the
MISFETs, the changes of the temperature, etc.
This invention has been made by going back to the
starting point of the physics of semiconductors and taking
special notice of the energy gap Eg, the Fermi level
-- 8 --

Ef, etc.
It is well known that semiconductors have energy gaps
Eg and various levels such as donor, acceptor and Fermi
levels. However, until now there have been no proposals
to produce a reference voltage generator device utilizing
the physics of semiconductors, especially the energy gap
Eg and the Fermi level Ef, despi-te remarkable develop-
ments achieved in extensive fields since the discovery of
semiconductors.
Based upon actual results, the inventors thought of
utilizing the energy gap Eg~ the Fermi level Ef, etc.
for reference voltage sources and have succeeded in this
realization. It is not difficult in theory to use the
energy gap Eg~ the Fermi level Ef, etc. for reference
voltage sources, and the results will be readily under-
stood. However, the success achieved by the inventors is
believed to be unprecedented, particularly from the point
of view that the inventors have gone back to the starting
point of the material properties of semiconductors,
bearing in mind that the history of the semiconductor
industry is no longer short. This development is
therefore believed to be creative and epochal, and is
expected to contribute greatly to further advancements
of electronic circuits and the semiconductor industry in
- the future.
According to the invention there is provided a
reference voltage generator device comprising means for
detecting a voltage substantially equal to or smaller than
an energy gap of a semiconductor or a voltage based on an
energy level of a semiconductor, a voltage based on the
detected voltage being used as a reference voltage.
According to a preferred embodiment of this invention,

two IGFETs which have silicon gate electrodes of conduc-
tivity types opposite to each other are fabricated within
a silicon monolithic semiconductor integrated circuit
chip. Since these FETs are manufactured under substan-
tially the same conditions except for the conductivity
types of the gate electrodes, the difference of the
threshold voltages Vth of both the FETs becomes
approximately equal to the difference of the Fermi levels
of P-type silicon and N-type silicon. The gate electrodes
are doped with respective impurities in the vicinities of
the saturation densities, and the difference becomes
approximately equal to the energy gap Eg of silicon
(about 1.1 V), which is utilized as a reference voltage
source.
Since the reference voltage generator device based
on such a construction has low temperature-dependency
and small manufacture deviations, it can be used as a
reference voltage generator device in various electronic
circuits.
The invention, and in particular the preferred
embodiments thereof, are discussed in detail in the
following with reference to the accompanying drawings,
in which:-
Figure 1 is a diagram showing the band gaps Eg of
GaAs, Si and Ge and their temperature-dependencies;
Figures 2(a) to 2(d) are diagrams showing the band
structures and Fermi levels Ef of semiconductors, in
which Figures 2(a) and 2(b) illustrate an example of an
N-type semiconductor and Figures 2(c) and 2~d) illus-
trate an example o~ a P-type semiconductor;
Figure 3, which appears on the same sheet as Fig. 1,
-- 10 --

is a diagram showing the temperature characteristics of
the Fermi levels of N-type and P-type Si with the impurity
densities being a parameter;
Figures 4(a), 4(b) and 4(c) are diagrams showing the
distributions of energy levels possessed by Ge, Si and
GaAs semiconductors and various donor and acceptor
impurities, respectively;
Figures 5(a) and 5(b) are diagrams showing the energy
state and the states of charges of a P+-type semiconductor
-insulator - N-type semiconductor structure respectively,
while Figures 5(c) and 5(d) are diagrams showing the
energy state and the states of charges of an N+-type
semiconductor -

lnsulator - N-t~p semiconductor structure respectiYely,
Fl~ures 6(a) and 6(b) are a characteristLc di~gram
and a circuit dia3ram of a ;IOS diode circuil for deriving
the difference of Vth of two F_.s having unequal threshol~
voltages 'Jth respectively;
~igure 7 is a characteri~tic dia3ram showing the
situation in which a threshold voltage is changed by ion
implantation
Fi~ures 8 and 9 are diagram3 each showing an example
of a reference voltage generator circuit which exploits
the differe~ce of threshold Yoltage~ ~t~;
~igure lO(a) ls a clrcuit diagram of a re~erence voltage
gene. 2tor circuit showin~ ân embodi~ent of this invention,
while Figure lO(b) is an operating waveform dia~,ra~ of the
clrcuit in Fl~ure lO(a),
Flgure ll(a) s~ows a further exam~le of a reference
voltage generator circult, while Figure ll(b) shows timing
signal waveforms thereof;
Figure 12 shows a reference volta~e generator circuit
which i~ based on another embodiment 7
~igure 13 shows an operational ampl1Lier circuit which
has an of~set voltage in accordance with thi3 'nvention;
~3ure 14 show a reference volta~e generator circuit
which utilizes the operational amplifier circuit of Figure 13;
Figures 15, 16 and 17 show reference ~oltage generator
circuits which utilize oper~tisnal amplifier circuits accord-
ing to other embodiments;
~igures 18 and 1~ 3how ~oltage detectcr circuits each
of which ~mplo-~ a re~`erence ~olta~e produced from the
,~0 reference Yoltage ~enera~or circuit according to this ln~ention~
- 12 -
,, . . .~
" .;
~ i

,~ f~
- Fi~ure 20 shows a volta~e detector c~rcuit which
utilizes an o~eratlonal amplifier circuit havin~ an offset
voltage in accordance with this invention;
Fi,ure 21 shows a ~oltage ~om~arator ~h.ich is for~,ed by
connectinæ r~os~.S of une~ual ~hres~.old voltages `Jth in the
differential ty?e in accordance with this invention;
Fi~u.e 22 shows a diffe-ential amplifier clrcult wh~ch
e~ploys ,IOSr ~Ts of unequal threshold voltages Vth in accordance
with th~s invention;
~igure 23 shows the drain current - versus - ~ate voltage
characteristi^s of the differential pair ~.OS transistors of
the differential am~lifier circuit shol~n in ?l~ure G2;
Fi~ure 24 sr.ows an o~fse~ type vo'tage co~arator
circuit which is cor.st~ucted of a volta~e com arator clrcuit
and so~rce Lollower circuits employing two ~CSF~Ts of threshold
~oltages different fro~ eacn other in accordance wit~ thls
inventlon;
Figure 25 shows an offset type volta~e co~parator
circuit which is constructed o~ a voltage comparator circuit
and ~rounded-source clrcuits e~ploying two ~IOSFETs of threshold
volta~es dlfferent from each other in accordance with this
lnven~ion;
Fi~ure 25 shows an example of a constant-current circult
which is used in the offset type voltage comparator circuit
f Fl~ure 24;
Figure 27 show3 2 reLerence voltage ~nerator circult
whic`.. er.,ploys the differential amplLfier c~rcuit shown in
Fi~ure 22;
~l~u.e 2~ sho~s the detalls of the offset typ~ volta~e
co~pa~2to. cir^ult ~howr~ in ~i~ure 24, and illustrates a case
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.~ ~
,~, ,:, ' '
, i

in which a reference voltage geilerator circuit is
constructed by employing this voltage comparator circuit.
~ re 29 shows a constant-current circuit ~hich
exploits the difference of the throshold ~olta~es of two
MOS~Ts in accordance with this invention;
~igure 30 shows a constant-current circuit to whicn is
applied a A eference voltage ,3enerator circuit that ?roduces
a reference voltage on the oasis of the differer~ce of tne
threshold voltages of t~o ~iO~ 's in accord~nce with th~s
invention,
Fi,sure 31 sho~s a constant-current circuit in which
a current mirror circuit is added to the constant-current
circul. shown in r iOure 30;
Fi3ures 32 and 33 are circuit -11a~ra~s each showinO
a stabilized power supply circuit to which is ap?lied a
reference volta;~e generato. circuit that produces a reference
~oltase based on the difference of the threshold voltaOes of
.iO~?~Ts in accordance with this lnvention;
~ure 34 shows a stabillzed power ~upply circuit to
which is applied an operatlonal amplifier that has the
dirference of the threshold voltages of MOSF~Ts as its off-
set volta~e ln accordance with this inventio~,
rlgure 35(a) is a circ~t di2sram for explaining an
ex~m~le of a voltage re~ulator to whlch an offset type
operational amplifier circuit according to this invention
is applled~ while ~i~ure 35(b) $s an electrical characterlstic
di2 Jram for explaining the operation of the volta~e re~ulator;
~i~ure 36(a~ is a circult dia~ram ~or e~plain n5 a ~olta~e
regul2tor acoord'nO to anothe~ ~m'~dlment of tnl~ ln~ention~
while ~i,ure 36(b) is an electrical characteristlc dia~ram
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, ~

~o~
for explaining the operation of the volta~e re~ulator;
~igure 37 is a circuit dia~ram showing an example ln
the case in which this invention is applied to a battery
lifeti.~.e detector circuit;
rigure 38 is a diagram Or:l circuit for a clocX-driven
battery checker according to another embodinent,
~iOure 39 is a diaDram of a reference voltage generator
circuit whose reference voltage can be finely ad~usted with
a resistor outside an IC,
Figure 40(a) shows a Schmitt trigger ~lrcuit to which
the principle of this invention is applied, while Figure
4C(b) shows the hysteresis characteristic of the Schmitt
tricger circuit;
~i~ure 41 show~ a Schmitt trigger circuit accordinO to
another embodl~ent,
FiOures 42 and 4~ are dia~ra~s eacn showinO an oscillator
circuit to which the Schmitt trigO~r c$rcuit according to
this inv2ntion is applied;
Figure 44 ~hows a differential ampllfier which e~ploys
20 . ~IOSr~Ts;
Figure 45 shows a TTL - MOS signal level shifter circult
accordlng to this i~vent~on;
Fi~ure 46 shows a loglc threshold stabilizer circuit
accordin~ to this invention
Fi~u~e 47 shows a ~ub~trate bias generator circuit
accordir,~ to this lnventlon;
Figure 48 ~hows a status setting circult according to
thi.s in~ention,
r i~re 49 ~hows a ~tatus settin3 circuit -.~hich has
hltherto been proposed;
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. ~ _ ~ _ _ _ _ ___
~'

- Fi~ure 50 shows a MOS ~emory which employs the substrate
bi~s generator c~rcuit shown in ~i~ure 47,7
~igure 51 shows a memory cell in the i~,OS memory of
Fi,3ure 50;
~iOure 52 shows a semiconductor random acces~ memory
accordin3 to this lnvention;
~i~ure 53(a) shows ~ voltage detector circùit wh~ch is
used in the semiconductor ra~dom access memory accordin~ to
thi~ invention, while Figure 53(b) show~ the operating wave-
for~s of the voltage detector circuit;
Figure 54 shows an electronlc timepiece to whlch the
batte~y checker s~own in ~i~ure 20 ls appl~ed;
~l~ure 55 shows an electronic tl~epiece to ~hich a
s~milar battery checker ls applied;
;iDure 50 shows an electronic timepiece to which the
volt23e re~ulator as shown ln ri~ure 3~(a);
~i~ure 57 shows an electrQnic timepiece to which a
~i~ilar ~olt~e rogul2tor is applied;
Figure 58, which appears on the same sheet as Fig. 61,
is a structural sectional view of two MOSFETs which have
threshold voltages different from each other in accordance
with this invention;
r i~re 59 schematically show~ sectional structures of
p+ gate and N+ gate ~OS?~Ts usable for deriving the àifference
~5 (Efn ~ Efp) of the ~erml levels of ~I-type and ?-type semi-
conductors, in wh~ch the left half shows a ?-cha~nel FET
whlle the right nalf shows an N-channel r ~T;
~ ure 60 also schematically shows sectlonal s-ructures
of p~ ~te and ~I+ ~te ~O~ Ts usable for de~ivinu the
difference (E~n - ~fp) ~ the ~ermi levels of N-type ~nd
P-type sem.conductors, in which the left half shows a
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~,
~, 1

--- ?-channel ~r.T ~hile the right hal~ sho~l~ an .J-cha~nel ~ET
Fl,,ure 61 si~ilarly shows a structure of two ~-channel
~;Câ~ETs whlch have threshold voltaJes different from each
. other;
Fi~ures 62 and 63 are sectional views each showin~ the
essential portions of ~iOSr~T5 ~hich are required for the
constr~ction of this invention and which have ~ate electrodes
of dlffQrent ~er~i lQvels;
Figure ~4 is a sectional view of the essential ~ortions
of i~QSr'Lms ~hioh constitute a reference volta~e generator
device accordinG to th.is lnvention;
Fi~ures 65(a) and 65(b) are plan view an~ a sectional
view o~ an ~I+ ~ate P-channel i'~OaFE~ respectively the sectional
views being taI~en alon~ llnes indicated by arrows in the
corresponding plan views;
~ ures 65(a) and ~6(b) are a plan view an~ a sectional
view o~ a ~+ gate ?-channel ~IOS~T, respectlvely;
~igures67(a) and 67(b) show a plan view and a sectlonal
view of a P+ gate P-channel MOaF~T, respectively;
Figures 68t 2) and 68(b) show a plan view and a sectional
vie~ of a~ te P-channel ~CSF~T, respectlvely;
Flgures 69ta) and 69(b) show a plan vlew a~d a sectlonal
view of an ~ ate P-channel MOS?~T, respectively
Figures 70(a) and 70(b) show a plan vie~ and a sectional
view of an ~I+ gate N-channel M05r~T, respectlvely;
~l~ures 71(a) and 71(b) show a plan view and a sectional
YieW G~ a~ i gat~ ~-channel ;-IOa~_T~ res?ectively;
Fl~ures 72(a) and 72(b) show ~ plan view and a sectional
view of a P+ gate ~-ch~n~el l`~CaF~T~ respectively;
~0 Fi~ures 73(a~ to 73(~) illus'rate that .~+ ~ate (~art ~)
- 17 -
.~, '
,,-,
~ ,,

and P+ 3ate (part A) P-channel ii'OS~ETs are fa~ricated
to~ether wlth a P-channel 7~T (part C) and an ~J-channel
F~T (part D) ~hioh con3titute a conventional co~ple~enta~
,,0~ device;
Figures 74(aj to 74(d), ~igures 75(a) to 75(d),
Li~ures 76(a) to 76(d) and ~igures 77(a) to 77(d) sho~
sectional view in the principal steps in the case of ~anufac-
turing two ;~OS~ETs according to thls invention tocether with
a co~ple~entary IIOS de~ice, respective~y
Flgures 78(a) to 78(e) show se~tional views in the
various step~ of ~anufacture in the case of ~-channel ~O~Ts,
Fi~ures 79(a) to 79(e), FiOures ~O(a) to 80(d) and
~i~ures al(a) to 81(d) are sectional views in various ~teps
for explainin~ a method of manuf3cturing~ itCSF~Ts r or use in
a ref-rence volta~e Oenerator circuit device according to
this inveniion, respectively, and
Figures 82~a) and 82(b) and Figures 83(a) to 83(d) show
sectlonal views ln various steps for explainlng another
method of manufacturin~ MO~F~Ts for use ln a reference
volt~ge ~enerator circuit device accordlng to this inventlon,
respectively.
The physics of semiconductors which begins with
the crystalline structure of a semiconductor and which
develops into the energy band of a semiconductor and
phenomena brought about by donor and acceptor impurities
are well explained in the literature.
It is, of course~ wel ~nown thet se~iconducto.s o~
d~ffer~r.t oolosltions ha~e energy gaps ~g lnherent thereto
and that the energy gap rg exp-essed in eV h~s the dimension
.~0
- 18 -
. ~
I .~ '-- '" ',' ~ .
, .
. ,

of a voltage. As previously stated, however, there has
never been any suggestion of using the energy gap Eg as
a reference voltage source based on the fact that the
energy gap Eg exhibits a low temperature-dependency.
The present invention has been made by starting from
the fundamentals oE the physics of semiconductors. There-
fore, the detailed description of this invention will be
commenced by briefly referring to the pertinent points of
the physics of semiconductors. Since the material pro-
perties of semiconductors are explained in extensive
detail in many publications, reference will be made to
one such publication, namely 1'Physics of Semiconductor
Devices" by S. M. SZE, published by John Wiley & Sons in
1969, especially Chapter 2 "Physics and Properties of
Semiconductors" on pp. ll - 65.
Application of Ene~gy Gap Eg
Semiconductors have a variety of compositions. The
semiconductors typically utilized industrially at present
are non-compound semiconductors of germanium (Ge) or
silicon (Si), and gallium-arsenic (GaAs) compound semi-
conductors. The relationship between the energy gaps Eg
of these semiconductors and temperature are explained on
page 24 of the publication referred to above, and is
reprinted in Figure l.
As seen from Figure l, the energy gaps Eg of Ge, Si
and GaAs are 0.80 (eV), 1.12 (eV) and 1.43 (eV), respec-
tively, at normal temperature (300 K). Their temperature-
dependencies are 0.39 tmeV/K), 0.24 (meV/K) and 0.43
(meV/K~, respectively. By deriving voltages of values
equivalent to or close to the energy gaps E, accordingly,
reference voltage generator devices can be obtained which
-- 1~ --

have temperature-dependencies one order smaller than those
of the forward voltage drop VF of a PN-junction diode
and the threshold voltage Vth of an IGFET as stated
previously. Furthermore, the voltage to be obtained is
determined by the energy gap Eg inherent to the semi-
conductor. With, for example, Si, it is about 1.12 (V) at
normal temperature substantially independently of other
factors. It is possible to obtain a reference voltage
which is not affected by dispersions in the manufacturing
conditions etc.
An example will now be explained as to the principle
upon which the voltage corresponding to the energy gap -
Eg of the semiconductor can be derived.
Applicatlon of Difference of Fermi Levels (Work
Functions) of N-type, i-type and P-type Serniconductors
The conditions of energy levels when doping semi-
conductors with donor and acceptor impurities are well
known. Especially noteworthy to this invention is the
phenomenon that the energy levels at which the Fermi
energies of N-type and P-type semiconductors are located
are separated towards a conduction band and towards a
- valence band with respect to the Fermi energy level Ei
of an intrinsic semiconductor. The energy levels become
mGre distant from the Fermi level Ei of the intrinsic
semi-conductor as the densitles of the acceptor and donor
impurities increases, the Fermi level Efp of the P-type
semiconductor comes close to the top Ev of the valence
band, while the Fermi level Efn of the N-type semi~
conductor comes close to the bottom Ec of the conduction
band. Accordingly, when
- 20 -

1~
the di ference ~Efn ~ ~fp) of both the ~ermi levels 13 taken,
the ener~y level difference i3 substantially approximate to
the energy g~p ~ po~essed by the se~iconductor and lts
te~perature-depende.cy is also approximate to that of the
ener~y ga? ~g. The SalDe applies to the differences (~fn ~ El)
and (Ei - ~fp) bet~een the Fermi level~ of the ?-type se~.i-
conductor and the intrinsic semiconductor and bet~een the
~er~ levels of the N-type semiconductor and the intrinsic
se!ni~onductor. In this case, however, the absolute value
approaches Eg/2. In the following, the differences relative
to the intrinsic semiconductor will not be described in detail
on the ground that they become one half of the difference
between the P-~pe and the ~i-type. ~ will be stated in
detail 'ater, t;~e hi~her the i~puritf concentration, th~
lo~er ~he tem~erature-dependency of (Ef~ - Efp). In order
to attain a ~reat energy level di~ference approximate to
the ener~y gap Eg and to attain a low ternperature-dependenc~
tnereof, accordingly, it ls ~avorable to establlsh an impurity
density 2S close to the saturatlon density as possi~le.
The Fermi levels Efn and Efp concern not only the density
of the donor or acceptor impurity but also donor or acceptor
levels Ed or Eal which differ according to the impurity.
maierial3. ~s the level Ed or ra has an ener~ level nearer
to the conductlon band or the valence band res~ectlvely~ the
Fer~i level Efd or ~fa comes closer ther~to. In other words,
as the lmpurlty 1eYe1S ~d and Ea of the donor and acce~tor
have s;e~ levels, the difference (Ef~ - Efp~ of the
~er~ levels co~es clo~er to the energy gap r.~ Of tbe se~i
conductor~
~0 As the impurit~ level 2d or E of the donor or acceptor
- 21 -
~,
, ~
i.

is closer t the r ermi level ~1 of the intrin~ic ~eml-
conductor, that is~ as it has a deeper level, the dlfference
(~f~ - ~fp) Or the rermi levels becomes more distant from
the energ~ gap ~ o the semiconductor. Thls, however, does
not si~nify that the tem?erature-de2endency degrades, but
signifies tha-t the absolute value of the difference (Efn - Efp)
of the Fermi levels diminishes. Accordingly, the difference
(~fn ~ ~fp) of the ?ermi levels or the difference of work
functions is a ph;sical quantity innerent to the semiconductor
material, the impurity materials, etc~ ~rom another Yiewpolnt,
it can become a reference voLtage sourc~ parailel or similar
to the energJ gap ~g of the semiconductor. That is, the
difference (Efn - Efp) of the Fermi levels per se can be-
come a reference voltage source which is lower in temperature-
. .
dependency and less liable to be affected by the manufacturin~
conditions th2n the forward voltage drop VF of a PN-Junction
and the threshold voltage Vth of an IG~ET. In conse~uence,
the expedient of taking out the difference (Efn - Efp) of the
~ermi le~els by the use of impurity materials exhibiting
donor and acceptor levels Ed and ha having shallow levels
can become one method for derivi~g a voltage of a value
su~stantially approximate to the energy gap F~g of the semi-
con~uctor. n ihe other hand, as regards the ~etting of a
voltage value to be obtained, when it is desired to obtain
a comparatively large reference volta~e equivalent to the
energ~ ~ap o~ the semiconductor, impurities ~hich exhibit
shallow levels may be used, and when it is desired to
obtain a comparatively small reference voltage, impurities
which exhibit deep levels may be used.
Specific Examples of the Selec_ion of Impurity Materials
- 22 - !
~ 1~

-- ~ The relation.s between the ~ermi level ~f and the
donor level ~d~ acceptor level ~a~ donor density ~Jd~ acceptor
àensity 12 and the temperature T will be described in
~etail ~ith reference to Fi;jure 2 and L~ ir~re 3. Prior to
this description, the data on page 30 of the aforementioned
publication as reprinted in Figure 4 will be referred to in
order to explain what levels various impurities present to
the Ge, Si and GaAs semiconductors and to explain how the
impurities are utilized in this invention.
~i,ures 4(a), 4(b) and 4(c) are dia~ra~s ~hich show
the enerOy distributions of various i~ urlties for Ge, Si
ana va.;s, respectivel~. The numerals in ~he respective diagrams
indicate er.ergy differences ~c ~ ~d) from the ~ottom ~c of
a conduction ~and as to levels located above tne center of
a sap or the r er~i level of an intr~nslc semiconductor r i
drawn by a broken llne, and indlcate energy differences
(~a ~ ~v) from the top ~v of a valence band as to levels
located below the gap center Ei, the unlt being (eV) in both
the cases.
cO ~ccordin~ly, 2n im~urity material ~ndicated by a small
nu~erical value in each diagram is sucn that ~ts level is
c10s2 to the bottom ~c of the conduction band or the top ~v
of the valence band, and it is approprlate as an impurity
for obtaining a voltaOe close to the energy ~ap ~g. By way
of exa~ple, for Si which is used most frequently at present,
level differences (~c ~ ~d) and (~a ~v) r p
exnibitod by the donor impurities Lir Sb, P, As and Bi
and the acceptor impurities B, Al and Ga are the smallest,
. .
and bGt.~ the level dil~erences are below about ~ the
3~ energ-~ ,ap ~ cf ~ ;hen a teQperat~re c~.arOe fro~ C CX is
- 23 -
, F~
, .'.
.,
~ .~ . 1, ,

neglected, the di.ference (Efd - Efa) of ~e ~ermi leYel~ of
N-type Si and r-type Si employing these i~purlties becomes
about 94 ~ - 97 ~ o the ener~y gap ~g of Si, which value
is approxi~ately equal to ~g. ~ donor impurlt~ and an
acceptor impurity which exhibit the smallQst level differences
(~c ~ ~d) and (Ea - ~~r) ne.Yt to the above i.~puritles are ~
(about 16 ~ of ~g) and In tabout 14 ~ of _g), re.~pectively.
Th difference (~fd ~ Efa) of the Fermi levels of ~J-type
Si and ~-ty~e Si employing the respecti~re l~puritie~ becomes
about 0.85 ~g at 0 K, and the deviation from the energy
ga~ ~g of S1 is as great as about 15 ,s. It is accordin~ly
unders~ood that the deviation ls much greater than those of
the aforementioned impurities.
Thus, one donor impurity selected ~rom the group con-
sisitin~ of Li, Sb, P, As and ~i and one acceptor i~purity
selected from the group consistin.~ of B, ,`~1 and Ca are
suitable as the i~purity materials of ?-type and ~ type ~i
for obtainin~ fl volta~e substantially equal to the energy
ga~ r-g of ~i. The other impurities will be suited to the
end of obtainin~ volta~es considerably smaller than the
energy ga~ Eg of Si.
Physlcs of Fermi Level Ef
. .
Now, the difference (Efn - Efp) of Fermi levels
will be explained with reference to Figures 2(a) to
2(d). These figures are diagrams illustrative of
the ener~y levels of semlconductors~ Figure~ 2(a) and 2(b)
show the energ~ level model of an N-type ser~iconductor and
the temperature charzcterls~ic thereof respectively, while
~'igur s 2(c) and 2(d) .~how t'~e enerOy le~el ~odel OL ~ ~-t;-~e
3~ se~icon~uctor a~d the ~emperature characieristic thereof
- 24 -
~ r~
. ~

respectlvel~ 4~08~
; Carriers ln a sem~conductor consist of the sum between
electrons nd created by lonizatlon of donor impurities ~d
and electron-hole pa~rs excited from a valence b3nd~
~en the donor i~purity density Nd is sufficiently high,
the number of the excited electron-hole pairs is negligible,
and the number of conductlon electrons, n becomes:
n ~. nd ......................... (1)
nd and n are respectively evaluated from the proba~ility
at whlch electrons are trapped by the donor level and the
number of electrons whlch exist in a conduction band, and
become:
r
nd Nd ~1 1 + exp (5d -F)}
N ~
d r.F - E ~...... ~.-(2)
1 ~ exp ( d)
kT
and
n ~ Nc-exp ( Ec~ .......... (3)
Here, the effective denslt~ of states in the conduction band,
Nc becomes:
N 1 2(2~ kT)3/2
where h: Planck's constant, m: effectiYe mass of electron,
k: Boltzmannls con~tant, and T: lattice temperature.
~rom Equations (1~, (2~ and (3),
Nc exp ( F ~c) = ~ E_ _ e~ ( 4)
kT
- 25 -
-, ~
" ~ . .
:; ., ',' ~ '' "''
..

- and ~ 081
d ~ exp (~F c) ~ exp ( ~ ) ................... (5)
Nc kT kT
Here, since t~e Fermi level is supposed to lle at a
position proxi~ate to the ~ottom of the conduction band Ec,
the first term of ~quatlon (5) is negligible, ~o that:
E~ - 1/2 (Ed + Ec) ~ 1/2 kT~ o~ (6)
This equation (6) signifies the following. In the case
where the impurity concentration denslty Nd is high9 not
only at a low temp~ature; but also at normal temperature,
NC/~d approximates 1 (o~e) and ~ ~ ~ 0, so that the F~rmi
level E~ lles at the intermediate point between the bottom
r c of the conduction band and the donor level ~d and
the temperature-dependency becomes substantially equal to
t~,e temperature characteristic of Ec.
However, when the temperature has become sufficiently
high, the electron-hole pairs excited from the valence
band predominate, the influences of the impurities
. .
lessen and the Fermi level EFn in the ~J-type se~iconductor
comes close to the level ~ of the intrinsic semiconductor~
The above relation~hip is illustrated in ~igure 2~b~.
~ui~e the same applie~ to the case of a P-type semiconductor
containlng only an acceptor impurity as shown in Figure 2(c).
When the temperature is low and when the acceptor impurity den-
sity is high, the Fermi level EFp in the P-type semiconductor
lies at a substantially intermediate position between the top
Ev of the valence band the acceptor level Ea~ When the
~0 temperature is raised, the Fermi level EFp comes close to the
- 26 -
,
, ~,. ... ...
;~ ~ ~ .' ' ` ' '
_..

~ermi level r 1 of the lntrinsic se~lconductor~
The temperature-dependency of t~e ~erml level EFp in
the ~-type semiconductor is lllustrated in Fi6ure 2(d).
~ elation between ~em~erature Characteristlc of ~ermi
., , ~
Level Ef and I~purity ~enslty(SPecific Example)
. _ .. .. _ .. . . .
The relations between the temperature-dependencles of
the Fermi levels Efp and Efn and the l~purity densities
have been explained in terms of physical properties. Now,
by taking as a specific example the Si semiconductor,
which is used most frequently in practice at present, the
difference of the Fermi levels (Efn - Efp) and its
temperature-dependency in practical use will be explained
with reference to data on page 37 of the aforementioned
publication. The data are reprinted in Figure 3.
In conventional processes for 2anufacturin~ a ii semi-
conductor integrated circuit, boron (B) and phosphorus (P) are
solely used as the impurity materials. Their high impurity den-
sities are 102 (atoms/cm3). However, even when the donor and
acceptor impurity densities Nd and Na are lol8 ~atoms/cm3),
which is lower by two orders, the difference (Efn - E~p) of the
Ferml levels of the N-type ~emiconductor and the ?-type
semiconductor is 0.5 - (-0.5) ~ 1.0 (eY~ at 300 K as read
from Flgure ~, and it is a value comparatLvsly close to the
energy gap Eg ~ 1~1 eV at the same temperature. The chan~e3
- of ~he difference versus temperatures ar~ from about 1.04
(eY~ to 0.86 (e't) ln a range of ~ro~ 200 K to 4C0 K (~70 C
to 130 Cl, ~nd the ch~ngin~ rate 13 0.9 (mV/C~. Th~s ls a
~mall value of approximatel~ 1~ comp~ri~on with 2 to 3 mY~C
of the rates of changes versus ~e~per~tures of the thre~hold
3~ ~olTage ~ith cf an I~F~r and ~e for-w&rd dro? volta~e V~ of a
- 27 -
7''~'
.~
~ .

-~ dlode as state~ previously.
- ~en the i~purit~ de~sities are 102 c~ 3 or h~gher>
the Ferml level difference becomes substantially equal to
the silicon ener~y g2p ~g)Si = 1-1 (V), and the cilanOirg
rate versus temperatures becomes a~out 0.2 ~V/C, ~hich i5
a sufficlently small value.
Accordlngl~, iE 'he impurity concentrations are about
lOl~cm 3 or ~iOher, a temperature-dependerlcy which ls, at
least, reduced to 1/2 - 1/3 of t~ose of the prior art can
be attained. ~ore preferably, the impurity concentrations
are 102cm 3 or higher (a reduction of about 1/10), and most
preferably, they are the saturation densities or dege~erate
densities.
Princi~le of 3erivin~ ?iffer~nce of Fermi Levels and
Actual ~xam.~le
, ~ ~
Upon ~hat ~ri~.ci?le can the voltage corresponding to
the difference o~ the Fer~i levels (Efn - Efp), (Efn ~ Ei)
be taken out? ~n example is to utilize the difference of
the threshold voltages Vth of two MOSFETs of channels of
the same conductlvity type whlch ha~e se~iconductor gate
electrodes that are formed on gate insulating films formed
under ~ubstantially t~e same ~onditions on different surface
areas of an ldentical semiconductor body and tha~ are made
of materials being of an identical se~icor.ductor substance
(for example, silicon) b~lt having dlfferent conductivity
type~. A specific example of this will now be described.
Each of Flgures 59 and 60 depicts the conceptual sectlonal
structure~ of the respective F~T5 formed within a com?le~en~ary
~0_ inte~rated circuit !~'.OSI~). Herelnafter, for the saKe
of brevit;, the MOS tra~si3tor whose gate electrode is ~ade
~ 28 -
~1 ' ~'` ` ,~

3L9~
o~ a P+-type semiconductor sha~ll ~e called the "~+ ~ate MO~",
the ~OS tran~istor whose gate electrode i~ made of an N -type
semiconductor shall be called the "~ gate ~OS", and th. MOS
transistor whose gate electrode is ~.ade of an intrinsic or
i-type semiconductor shall be called the ~i zate ~iOS". In
Figure 60, the left half shows P+, i and N+ ~ate P~channel
~'OS transistors, while the ri~ht half shows P , i, and N+
gate ~-channel ~OS tra~sistors.
The dlfferences of threshold volta6es amon~ the ~OSF~Ts
(Ql) ~ (Q3) and ~4) ~ (~6) in ~igure 60 is as in the
following table:
Table tUn~t: volt)
¦ l Q2 ¦Q~ Q4 a5 ~6
. __ ~ . . _ __.. _ . . _. _,
Ql 0.55 l.l _ _ _
. . . .: .. _ ... . . _ .
Q2 0.5~ .. 0.55 _ _
. _ -- . . ~ _~
3 _1~l 0.55 :: _ _
G4 _ _ _ ~ 0.55 l.l
__ ____ . _ ~ - .. ... ~
~5 _ ~ _ 0.55 -~ 0.55
....... _ . . _ . .. _ _ ~ ~
6 _ _ ' _ l.l C.55 " \ \
As will be described in detail later, Figures 7~(a)
to 7~(f) illustrate sectional ~iew~ of principal steps whlch
show that the P+ gate MOS and the N+ gate MOS can be
fabricated without altering or adding to any of the steps
of a conventional process for manufacturing a comple-
mentary MOS integrated circuit (CMOS IC).
~ re~ 65~a) a~d 65(b) or ~i~Jures 6~(a) and 66(b)
- 29 -
1 ~~
,

deplct a plan vlew and a secticnal struct~ral view of ;1~
gate or P+ gate P-channel ~IOS transistors to be actually used
i~ clrcuit structures, respectively.
Referring to r 1 ~ures ~5(a) an~ 65(b) or ~i~ure3
6~(a) and 56(b), in order to form a self-ali~nment structure,
a P-type impurity i5 diffused in ooth those end parts ~S and
r~ of the gate electrode G ormed of an i-type or intrinsic
semiconductor whlch are close to a source (S) and a drain (~),
for both the P~ gate MOS and the N' gate rlOS because th~
~OS transistor is of the P-chann~l in this case. In 2 ce~tral
part Cp of the gate electrode G, a P-type impurity is diffused
for the P+ gate r.o~ and an ~J-ty~e impurity ~s diffused for
the .~1+ ~ate MO~. ~ region ijir. which no impurity is diffusQd~
is provided between the central region and both t~e end par's
~S and cD close to the source and the drain. It is thus
considered that the point of differencQ between the ~ gate
MOS and the N gate ~IOS is only whether the region of t~e
central region part Cp o~ the gate is of the P-type 3emiconductor
or the N-type sem~conductor.
In Figures 65(a~ and 65(b) or Figure~ ~6(a) and
66(b), numeral 101 designates an N sillcon su~strate,
numeral lC8 a P~ source region, numeral 113 a P+ drai~ reglon,
numeral 105 a ~ate oxide film, numeral 104 a thic~ field oxide
film, and numeral 111 another oxide film. As can be understood
from Figure 65(a) or Figure 66(a), a plurality of p+ source
regions 108 are electrically connected in common with one another
by an ~nterconnection layer 114, a pluralit-y of P~ drain
re_i~r.s 113 ar~ electrically connected in coi~on wi~h each
otner by an interconnection la-rer 112, and a plur21it~ of
3~ gate electrodes C are electricall~ connected in co~mon with
- 30 -
.
,,
s, _~
, ,'s
~ .

8~
one another by an interconnecl~on la~er 115.
?ur~her, in order to reduce as much as possible
variation of the effective channel len~t`~ls O r' the . .OS
transistors attr~buted to the fact that the ?-type impurity
diffused re~ions at both the end parts ~S and ED of the
gate electrodes ~ ~or~e~ for the self-ali~.nment may shift onto
either the left or right side (source side or d~ain side~
during manufacture on account of the error of mask alignment,
the colu~lns of the source regions and the ~r~in regions are
alternately arranged, and the columns are arran~ed so that
the left half an~ the r~ght half ~a~ oe ?ut into line
symmetry with respect to the channel direction as a whole.
~ccordin,ly, even ~/hen the shi tir.O sf the ~.as~ ali~nment
with respect to the chanr.el direc~ion (leftward or ri~htward
shifting) changes the eYfecti~e channel len~ths of tne ~ETs
in the respective columns, the avera~e effecti~e charnel
len~ths of the ~ gate MOS and the N~ ~ate ~;OS in the respec-
tlYe columns connected in parzllel have the chan~es cancelled
as a whole and become substantially constant.
~lgures 73(a) to 73(f) Lllustrete how the P~ gate
~OS and the N ~ate MC~ are constructed by the use of the
conventional manufacturin~ proces~ for a silicon gate C~:OS IC.
In Figu~e 73(a), numeral lCl designates an N-type
sil~con semiconductor having a specific resistance of 1 Qc~
to 8Qcm, on which a thermal oxidation film 102 is grown to
about 4,000 A to 16,000 A. A window for selective diffusion
is provided in the film by a photoetching technique. Boron,
to serve as a P-type impurity, is ion-implanted in a quantity
of approximately 1011 to 1013 cm~2 at an
50 KeV to 200 KeV, whereupon it is thermally diffused for
F~
,
I ._./ ' ' `
. .. . .

~Lf~8~
abou-t 8 to 20 hours, thereby to form ~ P well reg~on 103
whlch serves a~ z substrate of an N-channel ~.OS transistor,
In Figure 73(b), the thermai o~idation film 102 is
full~ rer20ved, a ne~ thermal cxidation film 104 is formed at
about 1 ~m to 2 ~m, and a region of this film corresponding
to the source, drain and gate of the iG~ transistor i~ re~oved
by etching. ~hereafter, a gate oxide film 105 which is
about 3CO ~ _ 1,5CO ~ thick is for~ed. On the resultant
substrate, polycrystalline Si 106 ~eing of the i-t~pe or
intrlnsic semiconductor is gro~n to about 2,000 A to 6,OOOA.
~y etchinOJ, it is removed with the gate part C of the ilOS
transistcr left behind.
In ~i~ure 73(c), a mask oxide film 107 is for~ed by
vapor Orowth, anl its regions under ~hlch a P-type impurity
is to oe diffused are removed by the photoetching technique.
Thereafter~ boron,bein~ the ~'-type impurity,is diffused at
a hign density of about 102 to 1021 cm 3 to ~orm a source
re~ion 108 and a drain region 113 o~ the ~-channel ~iOS transistor
and simultaneously to for~ a gate elecLrode of a P-ty~e
semiconductor.
In ~i~ure 73(d), as in the foregoing, a mask oxide
film 109 is formed by vapor growth, and its regions
undêr ~hich ~n ~'-type lmpurlty is to be difused are removed
by the photoetching technique. Thereafter7 phosphorus,bPinO
the ~J-type i~purity,i~ diffused at a high denslty of about
102 to 1021 cm 3, to form a ~ource region 110 and a drain
re~ion 116 of the ~-channel ~0~ transistor and simult2neously
to ~orm a Sate electrode o~ an N-type semiconductor.
In Fi,ure 73(e), the oxide film 10~ is removed. An
oxlde fi~m 111 which is approximately 4,000 ~ to 8,000 g
- 32 -
r.--
: . , .
, !
; ~,)' ,. '`
.~: .

38~
thlck is formed by the vapor ~rowth, dnd its re~ion
corresponding to an electrode leading-out portion is
re~oved by the photoetchin~ technique. Th reafter, a metal
(Aluminum) 15 evaporated, and an electrode interconnection
portion 112 is formed by the ~hotoetcnin~ techni~ue.
In Fi~rure 73(f), the resultant substrate i5 covered
~ith an oxide film bein3 1 ~m to 2 ~m thick by vapor
~ro~th.
Now, the threshold voltage of the ~;OS transistor
e~ployin~ the semlconductor for the gate electrode will be
descriDed with reference to Fi~ures 5(a) to 5~d). First,
in the case of the P~ ~ate i~Oj, the followin~ is indicated
from an enersy band diagram of Fi!-ure 5(a):
q VG + q ~FP+ + ~ = q V0 + q ~ f
~b;i.,E,~
+ '~ ~ 5 ............................. (7)
~Si
where VG: Potential difference between a semiconductor
substrate and a gate electrode ~P+ semiconductor),
: Electron affinit~J,
E : Energy gap,
-g
~srf~ Surface potent~al o~ an ~I-type se~icond~ctor subst.ate,
~5: ~ermi potential of a ~-type semlcon~uctor with
roferonce tc th~ ~ermi potenclal of an intrinsic se~icon~uctor,
~: F~rmi pot~ntial o~ the ~'-type se~iconductor ~ubst~ate
3 with reference to the Fermi potential of the intrinsic se~conducto
- 33 -
1'
, ~,~
,,

q: Un~t charge of electron,
VO: Potentlal dlfference applied to an insulator,
Ec: Bottom of a conduction band 7
Ev: Top of a ~alence band,
Ei: Fermi level of the lntrinsic ~emiconductor,
In Equation (7), the work function of the gate electrode i5
denoted a~ p ~ in potent~al, and the work function of the
semiconduotor is similarly denoted as ~Si Then,
~MP ~ + 2q + ~FP ......................... (8)
dsi Y ~ ~ 2~ ............................. "(9)
Therefore,
. .......................... (10)
From the relatlon of charge~ ~n Figure 5(b),
COX Yo + QSS + Qi + QB ..,...,(11)
where COx: Capacitance of the insulator per unit area 9
~SS: Fixed charges in the lnsulator,
QB: Fixed charge~ due to Lonlzatlon of impur5ties
in the semlconductor 3ubstrate,
Qi: Carriers formed as a cha~nel.
From ~10) and (11),
~COX S VC ~ ~P ~ ~S~ ~ ~Srf)
~ QSS Qi ~ QD ......... ~...... (12~
The gate ~oltage VG at the time when the channel Qi i3
for~ed Ls t~,e threshold voltage. Therefore, lecting V~hp
denote the chresho.d v31tage of th2 P~ gate MOS,
3~ V ~ 8 YC ~ sl srf - COx Cx
- 34 - :
. ~__
, ,';
, ,~ ,,
.~

At th~s ti~e, ~Srf ~ 2 ~F~
Likewise, in the N gate MOS transi~tor, only the work
function ~ of the gate electrode di~fers as follow~:
~MN ~ 2q + PF'~ ......................... (14)
Accordingly, the threshold voltage VthN+ of the N t gate
MOS becomes:
thN ~MN ~Si ~Srf C C ~.(15)
OX ~X
where ~r~ ~ 2 ~F~
Thu3, the difference Vthp~ - Vt~+ of the threshold
voltages of the P+ gate MOS and the N~ gate MOS becomes:
Vthp - V~h~ M~ ~ ~FP ~ dF~ ( 16 )
which i~ equal to the di~erence of the Fermi potentials
o~ the se~iconductors maklng up the gate electrodes.
Thl can be readlly understood from the fact that, when
Flgures 5(a~ and 5Ic~ are compared, the gate voltage at the
time when the same charge proflle i~ established i5 equal to
the difference of the work functions of the gate electrode~
and the difference of the Fermi levels.
'~hile the above descr~ptlon has been made by taking
the P -channel ~OS transistor as an example, quite the ~ame
applle~ to the caae of the N -channel MOS tran~istor.
From the above, it can be understood that a voltage
sub3tantially equal to the ener~y sap Eg can be derlved a~
the difference of the threshold voltages of the P+ gate MOS
a~d the N~ g~te MOS. As another methcd, the roltage of the
energy g2p ~g can be der~ved with tne dif~erence of the
3~ threshold voltage of a MOS who~e gate electrode i3 ~ade of .
- 35 -
1 ~
, ~ : , . .;
3 ~ ~,

8~
~ ~ an intrlnsic semlcon~uctor (hereinbelow, wrltten a~ the
"i gate MOS") and the threshold voltage of the P+ gate MOS
or the N~ gate MOS.
Letting Ythi denote the threshold Yolta~e of the i
gate MO~, slnce the Fermi level of the intr~njlc semiconductor
is O (zero) (as the ~ermi level of the intrinsic semiconductor
~s made the reference~, the difference of the thre~hold
voltage~ of the i gate MOS and the P+ gate MOS is:
I~thi - VthP~¦ - lo - ~FP~ ¦' 1/2 ~g ......... (17)
The dlfference of the threshold voltag~s of the i zate MOS
and the N~ gate MOS becomes:
lvthi Vth~ F~ - O ¦ 1/2 Eg ... O .... (18)
It can be readily understood that the difference becomes a
voltage of just a half of the energy gap Eg.
The voltage which i3 obtalned owin~ to the difference
of the threshol~ voltages of the i gate MOS and the P~ gate
or N+ gate MOS ls ~ery useful in that lt is approximately
0.55 Y and ~ultable for a low reference Yoltage source, and
that,as will be ~tated later, a reference voltage source
of hi~h precislon i3 easily obtaLned, not only by the manufac-
turing proce s of the CMOS lntegrated circuit, but also by
the manufacturing proces3 of single-channel MO~ lntegrated
circuit because the doplng of gate electrodes with an
impurity ca~ be carried out by one 3tep.
~igure~ 67(a) and 67(b) to Figures 72(a) and 72(b)-
dep~ct plan patterns and ~ectlonal structures along llnes
A - A of the plan patterns, of P+ gate, i gate a~d N+ gate
P-channel and N-channel MOS tran~istors to ~ actually used
ln c~-cuit str~ctures.
In the various figures, as in Figures 65(a)
-- 36 --
l r~
, .
~''' ' .
.
, ~,',, ' - -

and 65(b) or Figures 66(a) and 66(b), the P- or
~-type reg ons of a source ar~d a drain are formed by tne
diffusion of an im?urity b~ employing pol~crystailine Si
for a mask. Tn order to allow a margin for th~ mask aliOnment
between the mask for 3electivel~ diffusing a P-t~pe impurity
or an ~T-t~pe impurlty and the source and drain re~ions,
the sa~e i~purity as that of the source and drain regions
i5 diffused ln both end part~ ES and ED of a ~ate electrode
G ad~oining the source ~ and drain D ln both the P+ ~ate
~.OS and the N+ gate ~IOS. In, ~or exa~ple, the ?-channel ~.OS,
boron which is the P-type impurity ~s dlffu~od. In a central
part of the gate electrode, a P-type impurity i diffused
for the ?+ Oate ~IOS, and an 'J-type lmpurity is diffused
for the N gate ~OS.
~igures 67(a) and 67(b)~ Figures 68(a) and 6~(b~ and
~igures 6g(a) and 69(b) represent plan views and ~ectional
views of P-channel MOS transistors of the P~ gate, 1 gate
and N~ gate, re3pectively, while Figures 70(a) and 70(b),
Fi~ure3 71(a) and 71(b) and Figure~ 72(a) and 72(b) represent
N-channel MOS transistors of the N+ gate, i gate and 2+ gate,
respectively.
In Figures 67(a) and 67(b) to Floure~ 72(a) and 72(b),
in order to roduce to the utmoqt the varlatlon of the
effective channel lengths of the MOS transistors attributed
to the fact that those regions a~ both the end part~ ES arld
of the gate electrode~ G,whlch are formed ~or the self-
allg~ment,and ln which the same lopurity as that of the
source and drain reg~on~ 19 d$ffused,~;~ift to eith~r th~ lef~
or right side (sourcé side or drain side) during manufac-
ture on account of errors of the mask alignment, the columns
, , ~
., , . . .
~ ~, ~' ' , .
,,

of the ~ource reglons and the dra~n re~ions are alternately
arranged, and the columns are arr~nged so that the left hal~
and the right half ~ay be put into a line symmetry witn
respect to the channel dLrection as a ~hole. Accordingly,
even when the shifting of the mask alignment with respect
to the channel direction (leftward or rightward shifting)
chan3es the effect~ve channel len~ths of the ~ETs in the
respecti~e columns, the average effecti~e channel lenæths of
the P+ gQte MOS, i gate MOS and the N+ gate MOS ln the
respectl~e columns connected in parallel have the changes
cancelled as a whole and become substantially constant.
Fl~ures 74(a) to 74~d) illustrate how the P~ gate MOS
and the N+ gzte ~OS are constructed in the conventional
sillcon gate C;~OS manufacturing process.
;n Figure 74(a), numeral lOl deslgnates an N-type
silicon semiconductor havln~ a speciflc resistance of lQ cm
to 8Qcm, on which a thermal oxidation film 102 is grown to
O O
about 4,000 A - 16,000 A. A window for selective diffusion
is provided in an area of the film by the photoetching
technique. Boron, to serve as a P-type impurity, is ion
implanted in a quantlty Or approximately lOll - 1Ol3 cm 2
at an energy of 50 KeV - 200 xeV, whereupon it is thermally
diffused for about 8 - 20 hours, thereby forming a P well
~eg~on lO~ whlch ~er~e~ as a substrate of a~ N-channel MOS
tran~istor.
In Figure 74(b), the thermal oxidation film 102 is en-
tirely removed, a new thermal oxidation film 104 is formed to
about 1 Jlm - 2 ~m, and a region of thls film correc:yQndir.g
to the source, drain and gate o~ tne MG~ transistor ls
3~ removed b~t etching. Thereafter, a gate oxide fLlm lO5 which
- 38 -
r
~ . . .
. ~ I . . . .
., / ,, -

o o ~
ls ~bo~t ~CO h - 1,500 ,i thick is formed. On the resultant
substrate, polycrystalline Si 106 being of the i-type or
intrins~c semlconductor ia grown about 2,0CO A - 5,000 A.
~y etching, it is re~oved witn the gate part G of the ;~OS
transistor left behind.
In Fi~ure 74(c), a mask oxide film 107 ls formed by
vapor growth, and its regions under which a P-type
~mpurlty is to be dlffu3ed are removed by the photoetching
technique. Thereafter9 boron to become the P-type impurity
at a high denslty o~ about 102 - 1021 cm 3 ls dlffused, to
for~ a sourc~ region 108 and a dra~n re~lon 113 of the ~-
chan~el ~OS transistor and simultaneously to form a gate
electrode of a P-type semiconductor~
In Figure 74(d), as in the foregoin~, a mas~ oxide
film lC9 ~s for~ed by the ~apor growth, and it~ regions
under whlch an N-type impurity ls to be diffused are removed
by the photoetching technlque. Thereafter, phosphorus to
become the N-type impurity at a high concentration of about
102 _ loZl cm ~ 15 di~fused, to form a souroe region 110
and a draln region 116 of the ~-channel MOS translstor
and simultzneously to form a gate electrode of an N~type
semiconductor.
Subsequently, the oxide film 109 ls removed. An oxide
film which is approximately 4,000 A - 8,000 A thick ls formed
by th~ vapor ~rowth, and lts part corre~pond~ng to an electrode
~eading out portion is removed by the photoetching technlque.
Thereafter, a metal(aluminum) i~ eYaporated, and an electrode
lnterconnection portion ls fo~ned by th~ ~hotoetching technique.
Subsequently, the resultant substrate is covered wlth
an oxlde rllm being 1 ~ - 2 ~m thlck by vapor growth.
- 39 -
, j;"
.s,
~ '' ;~' ' ' .

~45~
Here, in Fi~ure 74(d), Q3 and Q4 indicate M03 transistors
which constitute a conventional C.lOS inverter, and Ql and
Q2 indicate P~ gate and N+ gate MO~ tran~istors for ~enerat-
ing a reference voltage.
Figure~ 75(a) to 75(d) ~how section~ in the manufactur-
ing proce~ of p Gate MO~ and i gate MOS transistors of
the P-channel type. In this example, the step~ up to Figure
75(c) are the ~ame as those up to Figure 74(c). In Figure
75(d), however, the ~ type lmpurity is diffused without
removing an oxide film lO9b overlying the gate of the
MOSF~T Q2.
Figures 76(a) to 76(d) shcw sections i~ the manufacturing
proce~s of P+ gate MOS and M~ gate MOS tran~istor~ of the
N-channel type.
Flgure~ 77(a) to 77(d) show section~ in the manufacturing
process of N+ gate MOS and i gate MOS transistor5 of the N-
channel type.
Now, a process in an N-channel MOS sem~conductor
integrated circuit will be explained with reference to
section~ illustrated in Flgure 78(a) to 7&(e).
(1) A P-type se~lconductor substrate 101 having 2
~peciflc re~istance of 8 - 20~ cm i~ prepared, and a thermal
oxidation film 102 whlch is 1 ~m thick i~ formed on the
surface of the ~ubstrate.
~5 (2) In order to expose the sem~conductor substrate
surface corresponding to portions in which i~SFETs are to
be formed, selected parts of the thermal oxidatlon film are
etched.
(3) T~ereafter, a gate oxide film (SiO2) 103 which is
750 to ~,OCO A thick is formed on the exposed emiconductor
- 40 -
~,
. :'
, '
:

substrate ~urface (Fl~ure 78(a)).
(4) That Far-t of the crate oxide film 103 which i~ to
come into direct contact with a polycry~talline silicon
layer is selectively etched, to form a direct oontact hole
lC3a. (Fi.rure 78(b)).
(5) Silicon ls deposited by the CVD (Chemical Yapor
Deposition) proces~ onto the whole ma~or surface of the
semiconductor substrate 101 having the oxlde fllm 102~ the
gate oxide film 10~ and the co~tact hole 103a, to form ~he
~olycrystalllne silicon layer whlch i5 3,000 to 5,000 A.
(6) Selected pQrts of the polycrystalllne sillcon layer
lC4 being of the i-type or intrin3ic semiconductor are etched.
tF~gure 78 (c)).
(7) ~ CVD-mask SiO2 film is deposited to a thickne.~s of
2, 000 to 3, 000 A on the whole ma~or surface of the Remi-
conductor substrate 101 by the CVD process.
(8) The CV~-mask SiO2 fllm 105 is selectively left only
at hloh resistance parts such a~ memory cell load resistors,
and on the polycrystalline silicon layer of intrin~ic level
2Q gate portions 104a~ (Flgure 78(d)).(9) ?hosphorus is diffuced into the semiconductor su~-
strate 101, tO ~orm source regions and drain regions 106 at
an impurity density of 102 atoms/cm3. At this tlme, the
i~purlty 1~ also introduced into the polycry~talline sil~con
layer, to form gate electrodes 104~, a direct contact 104c
and a polycrystalllne silicon interconnectlon portion 104d.
tFigure 78(d)).
(10) A P~G (Phospho-Silicate-51as~) f~l~ 107 is formed
at a thickness of 7,000 to 9,000 .~ on the entlre major surface
of the semiconductor substrate 101
- 41 -
: ,'~,............................................... . .

9~
(11) Al ~aluminum) i3 ther~after evaporated on the wh41e
area of the ma~or surface of the semiconductor ~ubstrate
101, to form an ~1 film 108 which is 1 mm thlck.
(12) The ~1 film is selectiv~ly e~ched to form inter-
connection regions 108. (Figure 78(e)).
The princi?le of derivlng the dlf`ference of Fer~1
levels described above and actual examples will be briefly
~xplained again. ~le~ent~ shown in Figure 58 are enhancement
type p-channel I~IIS~ETs (al) and (~2) which are formed on an
n-type semiconductor substrate 1. The gate electrodes of
the respective ~IISF~Ts are made of conductor layers which
are constructed in such a way that polycrystalline silicon
layers are doped with semiconductor impurities of differ~nt
conductivity typ~s. i~ore specific211y, the ~IISFETs (al, C2)
are fabricated as follows. As shown in Figure 58, P~-tYPe
semiconductor re~ions 4,5 to form the sources and drains
of MI~F~Ts are selectively for~ed on an n-type semiconductor
substrate 1. Gate insulating films 2 are formed on the
areas of the surface of the semiconductor substrate between
the opposing source and draln regions 4,5, and poly-
cr~stalline silicon la~ers 6 and 6' are for~ed on the gate
insulatin~ films 2. The polycrystalline silicon layer
to constitute the gate 6' of one MISFET (Q1) is doped
wlth a se~conductor lmpurity Or the ~ame conductivlty type
as that of the substr~te (n-type). The polycrystalline
sil~con layer to constitute the gate 6 of the other
MI~T (~2) ls doped with a semlconductor lmpurity of the
conductivity ~ype oppos' te to th2t of the subs~rzt2 (p-.ype).
The threshold voltages (Vt~l, Vth~2)
MIS~Ts (~ 2~ in the above constructlon are- e~aluated
- 42 -
1 ~
~, ; . ! ,

from the followlng equations (19) and ~20): -
V 99 QD
th'''l ' ~ ~ ~ C + C ......... (19)
thQ2 = ~ + 53 + QD ......... ~20)
ox ox
Here, ~Mn and ~;~p denote the work functions between
the gates of the respective ~IIS~Ts (Ql~ Q2) and tne
sub~trate, COx the gate capacitance oer unit ares, Qss the
surface charge, and QD the charge of ~ substrate depletion
layer.
'~'hen the difference of the threshold volta~es of both
the ~SF~T3 ~Ql~ Q2) ~s evaluated, it becomes the dif~erence
(~lp ~ ~ln) bet~een the work functlons which are tne first
terms of the ri~ht-hand sides of Equatlons (19) and (20), ar.d
it can be derived as a voltage which corresponds to the energy
gap of silicon. Slnce thi~ voltage becomes a volta~e stipulated
by the energy gap of sil~con, deviatlons in the manufacture
are not involved. In addltion, the temperature dependency is
extremely small. The reason why the threshold voltages of
MI~Ts exhibit great deviations i~ that the ~econd terms
(~5S/~OX) and the thlrd terms (aD/cOx) on the right-hand
sides of Equa~lons ~19) and ~20) fluctuate depending upon
the condition~ of manufac~ure. In this embodiment, the
the MISF~Ts (31' Q2) are manufactured un~er the a~e co~di-
tions, whereby the ~econd terms and third ter~s on the
rl3ht- hand sides of ~quations 19 and 20 ara made ~ub-
3tantially equal. By evaluatin~ the difference between the
ri~ht-hand sides~ the second and thlrd terms are cancell~d
Thu~, the magnltude equ1valent to the energy gap i~.used as
- 43 -
! _ ~ '' -- ' ' '- ' -- _ _ ___ ~
.,
.~ ' ,' ' ~ `"` ' '
~,' ' ` I

an output voltage,
Since the MISFFT (Q2) ha~ the source, drain and ga~e
electrode for~ed by the use of the semlconduotor lmpurity
of an identlcal conductivlty type, the conventlonal manufactur-
ing technology of a silicon gate ~ISFET in whlch the semi-
conductor impur~ty diffusions o~ its source and drain and
lts gate electrode are simultaneously carried out can be
e~ployed, On the other hand, the gate electrode of the
MISF3T (Ql) cannot be formed simultaneou~ly wlth the source
and drain thereof and accordingly needs to be formed by a
separate step~ In thls regard9 a method is consldered
~herein the MI~F~Ts (Ql~ Q2) a~ above described are formed
whlle employln~ the conventional ~anufacturing technology of
tho silicon gate ~5I~FT in ~hlch a gate insulatin~ film and
a ~ield insula-tlr.J film are used as a mask. ~lternatlvely,
the measure i~lustrate~ in rigure 61 may be considered. More
specifically, those parts 6a, 6a' of gate electrodes 6, 6'
of MISFETs (Ql' ~2) which are proximate to sources and drains
are made ~ate electrode portions ln which a p-type semi-
conductor impurity o~ the ~ame conductivity type as that of
the sources and drains is dlffused. The central parts of the
gate electrode~ whlch are not doped with any semicor.ductor
lmpurity, that is, which are made of the intrinsic semi-
condu~tor (i-type) are select~vely formed with a gate elec'rode
portion 6b in which a p-type impurity is diffused and
a gate electrode portion 6b' in which an n-type semiconductor
impurity is diffused, respectively. The parts doped
.. . .. .
with no semiconduct~r i~.purity have been di~osed in con-
si~eratlon of t.le mi~re~i~tratlon of the mask al~n~ent
when forming the gate electrode portions 6b, 6b'
- 44 -
, ~
, i'''

- of the dlf~erent semiconiluctor impurities in the selected
reglons. In th1s method, the ~ate electrode portions
6a, 6b of the MISFET (Q2) are formed by the same step as
that for the diffuslon of th* source and drain.
~ach of the MI~F~s ln the above construction has a
~ate electrode which is made up of the plurality of ~ate
electrode portions. The plurallty of gate electrode portions
are connected in common and the difference of threshold
voltages of both the MI~Ts (Ql~ ~23 are taken, whereby
tnreshold voltage components based on t~ie electrode portion~
of the same structures (gate electrode portions 6a and 6a',
and i-type electrode portions) in both the ~iI3~Ts (Ql~ q2)
are canceled. In addition, re3ardlng the ~ Ts owin~ to
the gate electrode portions ~5b, 6b'~, the second and third
terms on the ri~ht-hand sides of '~quat1ons (19) and (20) are
not cancelled. As the difference voltage, there is obtained
the voltage whlch corresponds to the silicon energy ~ap being
the dlfference of the work function between the central
parts 6b, 6b' of t~e gate electrodes and the substrate as
descrlbed previou~ly~ and whlch is approximately 1.1 V.
Fl~ure 62 ~hows a complementaty insulated ~ate field-
effect transistor integrated circuit (Cr~OSIC) according to
another embodiment of this invention. P-channel MOS tran~i3tors
A, B and C are for~ed on an N-type sillcon body 1, while N-
channel ~r,os tran~istors D, E and F are formed on a well
layer 2 ln which a P-typ~ impurity ~s diffused at a low
concentration. A reference vol~a~e generator device is
constructed by e~ploitin, the difference o~ the threshold
volta~e~ of the ~ S trans stors ~ and ~, the MOS tran3istor~
3C A and C or the ~0~ transis~or3 B and C, or the difference of
- 45 -
~, _
,, ~

the thr~shold volta~es of the I~OS transi~tors D and ~, the
MO~ transistors D and F or the ;~CS transistors 2 and ~.
Here, numeral 3 designates a thlck field oxlde ~ilm (~iO2~,
and nu~eral 4 a Oate o~ide fil~ (~iO2). ~u~eral 5 designates
2 P-t~pe semiconductor re~ion for the ~ource or drain of the
?-channel MOS~ r T ~ and numeral 5 an ~-type semiconductor
re~lon for the source or draln of the N-channel MOS~T.
:~umeral 7 indlcates P type polycrystalilne silicon, numeral
N-type ~olycry~talline silicon, and numeral 9 the ~ntrinsic
semiconductor or i-type polycrystalline silicon. ~he reference
voltage generator device derives ~he Fermi level difference
amon~ tne materials 7, 8 and 9 in the for~ of the voltage.
~i~ure 6~ shows an embodiment which is a further impr~ve-
ment on the embodiment of ~igure 62. P-t~pe impurity layers
10 shown in Fi~ure 63 are disposed under the ~ate oxide
films 4 ln a manner to overlap with the central parts 8 and
9 of the gate electrodes of the respective ttansistors 3 ard
C in Figure 62, and the transistor A is also provided with ~-
a P-type impurity layer 10 so as to have an effective
cnannel length equal to those of the transistors B and C.
Furth~r~ N-type impurity layers 11 shown ln ~i~ure 63 are
disposed under the gate oxide films 4 in such a manner as to
overlap with the central parts 7 and 9 of the gate electrodes
~f the respective transistors E and ~ in ~igure 62, and the
transistor D is also provided with an N type impurity layer
11 so as tO ha~e an effective channel length equal to those
of the transistors E and F Th-~ effective channel lengths
of tne transistors .^, B and 5 or the tran3istors 3, ~ and
can be mad~ slb~tantlally equal by dispos~ng the ?-t~pe
lmpurit-J layers 10 or the N-type impurity layers 11.
- 46 -
.
,,.

96~
Accordingly, the characteristics between the drain current3
and gate voltages of the tran~13tors A, B and C or the
tran3istors ~, E and ~ beccme curves which are parallel to
one another and which shift in the direction of the gate
voltage axis by the differences of the Fermi lev21s of the
polycrystalline sllicon ~aterials at the central parts of
the gate electrodes of these transistors. Therefore, the
differences of the thre~hold voltages of th~ transis+ors
can be derived with high precision in reference voltage
generator circults to be described later.
Th~ tem?erature-dependencies of the dif,erences of ,he
threshold volta~e of the three sorts of IG?~Ts are very
small because the temperature-dependencies of the differences
of the ~ermi levels of the gate electrode semlconductors are
lo~.
FiOures 79(a) to 79(e) illustrate a method of manu~ac-
turing the C.~IOSIC shown in Fl~ure 63.
(a) A low concentrat~on P-type well region 102 ls
formed in an ~I-type sllicon body lO~ by the conventional
selectlve dlffuslon process. Subsequently, a field oxide
~ilm 103 is formed. After for~ing a gate oxide film 104
in reces~es of the ~llm 103, a P-type impurity layers 105
and an 'I-type impurity layers 106 are forme~ by the con-
ventional selective ion lmplantation processes.
~5 (b) Polycrystalline silicon 2ate electrodes 107 are
forned by the conventional che~ical vapor depositlon and
photoetchln~. At thls sta~e, the electrodes 107 are of the
intrinsic semiconductor.
(r) A mas'x o~ide il~ 108 is rormed on sel~cted areas
by the cnemical vapor depositlon. U5ing it as a mask, source
- 47 -
.
~:

08~
and drain layers 109 of r-chanrlel i40~F~T~ and ~-type
polycrystalline layers 110 are formed by the selective
diffusion of a ~-type impurlty.
(d) A ma3k oxlde film 10~' ls formed on selected areas
by the chem~cal vapor deposition again. Using it as a mask,
source and drain layers 111 of ~,-channel ~OSFETs ar.d .~-type
polycrystalline layers 112 are formed by the selective
diffusion of an ~I-type impurity.
(e) A phcsphosilicate gla~s ~ilm 113 is deposited9
contact holes are formed thereir., and aluminum electrodes
114 are for~ed. Then, the device is completed.
~ ure S4 showY another embodiment of the structure
of IGF~Ts whlch constltute the r~ference volta3e generator
device of this lnvention and which have gate electrodes of
different Fermi levels. Here, IGFETi3 A, B and C have a gate
electrode whlch is made of P-type silicon 7, a gate electrode
whose both ends are made of P-type silicon 7 and whose
central part is made of intrlnsic sillcon 4 and a gate
electrode whose both ends are made of P-type silicon 7 and
whose central part is made of aluminum 12, respectively.
These ~te electrodes are overlying on the gate oxide films
(SiO2) 3 whlch are for~ed on different surface areas of an
identical .~type sil~con body 1 under substantially the same
conditions. Further, the IG~ETs have source and drain layers
8. As to the threshold volta~es, when the threshold voltage
VT~ of the IGF~T A ls made -O. a v, that of the IGF~T B becomes
approxlQately -1.40 V, and that of the I~FET C becomes
approx~mately -1.95 V~ They produce differences which are
i~ubstantially equal to the differences of the ~er~1 levels
of the Si and Al materials at the central parts of the gate
- 48 -
~, ' ,
1~
j .

electrodes. ~ ~ 4~ ~8~
Thls embodi~ent has been made with note ta~en of the
fact that the temperature-dependency of the difference
of approximately 1.15 eV between the Fermi levels of the
hi,h concentration Ptype ~llicon an~ ~he aluminum or the
difference of approxi~ately O.S0 eV between the ~er~i level~
of the inirins1c silicon and the aluminum ls low.
~igures 80(a) to 80(d) illustrate an embodiment of a
method of manufacturlng a ~-channel IGFET inteFrated cl.cuit
wh ch includes all the ICFETs A, B and C ~hown in ~igure 64.
(a) ~ thick fleld oxlde film (SiO2) 2 having recesses
is formed on the surface of an N~type silicon body 1, a gate
oxide fil~ 3 is formed in the recesses, and a pol~crystalline
silicon layer 4 ls deDosited b~ the chemical vapor deposition.
~he polycry~talline silicon layer 4 ls of the intrinsic
semiconductor. ~urther, a mask oxlde fil~ 6 is formed on a
part of the layer 4 by the chemical vapor deposition.
(b) The polycrystalline sllicon layer is selectively
removed by the conventional photoetchinJ process, and a P-
type lmpurity such a~ boron is thermally diffused, to ~orm
source and draln layers 8 and ~-tYpe Dolycrystalline silicon
layers 7. At this time, the part of the polycrystalline
silicon layer 4 covered with the oxide film 6 i~ held intrinslc.
(c) An lnsulating film 9 such as phosphosilicate
~las~ fllm owlng to the chemlcal vapor deposition is de-
posited, and contact holes are formed therein. ~t this ti~e,
a contact hols 10 is also formed in the central part of a
gate electrode ~n an area to become ar. IGF~T ~.
(d) Alu~inu~ electrode3 11 and 12 are for~ed, and a
3C heat treat~ent ls conducted at ~80 to 540 C l~or 30 minutes
- 49 -
~ ~ , .
, ~' ~
,,i'" ` `.

8~
to 3 hours. Then, the polycrystalline sillcon at the
contact hole 10 diffuses towards the upper surface of the
aluminum layer owln~ to its allo~in~ reaction with the
o$1umin~m, and a structure in which the alu~num and the
~ate oxi~e film lle in direct contact is established.
The method of manufact~rlng the ?-channel IG~T integrated
circuit as lllustrated in Figures 8cta) to 80(d) is also
a~,~licable to the manufacture of a comple~entary MIS integrated
circui+ substant1ally as lt i3.
The alloylng reaction may be replaced with an e~pedient
in which th.e central part of the gate electrode is removed
-~y photoetcning, whereupon aluminum i3 brought into direct
contact ~ith ~he gate insulating film.
l'he reference voltage generator device `o~sed on such
a cor.s~ruction exhibits a small te~perature-dependency and
small manufacturing deviations, so that it can be utilized
for various electronic circuits~ -
Fi~ure 81(d) shows the structure of IGFETs A, B, C and
D whic~. have threqhold voltage di~erences based on the Fermi
level differences of gate electrodes ln accordance with
another embodiment of thi~ lnvention. The IGF~T A is a
P-chanr.el MO~F~ having a gate electrode made of P type
silicon 11, while the IG F~ ~ is a P-channel MOS~2T having
a gate electrode whose both end parts are made of P-type silicon
11 and ~hose central psrt is made of 'q-type silicon 8. The
IGF~T C is an N-channel MOSFET having a gate electrode made
of ~-t~pe slllcon 8~ while the IG~ET D is an .~'-channel
MC~_T haYing a gate electrode whose `ooth end parts are made
of ~'-t~pe silicon 8 and ~ose central part is ma~e of P-type
silicon 11. ~ reference voltage generator device is constructed
- 50 ~
''
':

by employing a voltage based on the differenoe of the
threshold voltag~s of the MOSFET~ A and B or the MOSFETs
C an~ D.
Figures 81(a) to ~l(d) illustrate a method of fabricat-
ing a ~OS integrated circult whlch includes the IGFETs A, B,
C and 3.
(a) A P-type well region 2 is formed in an ~-type
silicon body l, and a thick field oxide film 3 having recesses
ls formed. Thereafter, a gate oxide film 4 ~5 formed in the
recesses of the oxide film 3, and a film 5 of polycrystalline
silicon bein~ the intrinslc ~emiconductor is deposited and
worked by the photoetching proce~s.
(b) A mask oxide fllm 6 ls formed on ~elect2d areas
by chemical vapor deposition. Using it as a mask, an
~-type impurity such as phosphorus is diffused into ~elected
regions, whereby N-type reglonq 7,to become the source~ and
drain~ of N-channel MOSFET~ and N-type polycrystalline layers
8~are formed.
(c) A mask oxlde film 9 ls formed on selected areas
by chemical vapor deposition. Using it as a mask,
a P-type lmpurity such a~ boron is lon-lmplanted, whereby
P-type regions lO,to become the sources And draLns of P-
channel MOSF~Ts and P-type polycry~talline ~ilicon layers
11, are formed. Here, when using boron, the oxide film
9 ls made about ~,GOO A thlck, and an lmplantation energy
of 30 to 50 KeV and an lmpla~tation quantity o~ 2 x 10l5 to
l x 10l6/cm2 are appropriate. The actlvation of ~he implanted
ions i~ sultably done by a heat treatment a- gocc for lO
minutes to at l,000C for 30 minutes.
The di~fusion of the N-t-~pe l~purlty ln the step (b)
- 51 -
' . ' ' . .-
~ ,~ ' '' '.,' '" ,' ' `'` ' `
.

- may be performPd a~ter the step (c). In this case~ the
N-type lmpurlty dif~us~ on lndicatPd ln the step (b) had
better b~ executed by the ion i~plantatlon o~ phosphorus
or the like. When using phosphorus here, the oxide
fllm 6 is made about 3,000 A t~ick, and an lmplantation
energy of 60 to lCO ~eV and an lmplantation quantity Or
2 x 1015 to 1 x 1016 /cm2 are approprlate. Suitable for
the actlvatlon of the i~planted lons is a heat treatment
at 900C for 10 mlnutes to at 1,000C for 30 minute~. By
carrylng out the doplng with the P-type impurlty in this
manner, the heat treatment after the doping with the P-type
lmpurlty can be relleved, ~o that the channel port~ons can
be prevented from bein~ doped with the P--type lmpurlty.
(d) i~fter depo~itin~ a phosphoslllcate Ola~ ~llm 12
by chemical vapor deposition, contact holes are formed,
and alum~num electrode~ 13 are for~ed. Then, the devlce 1
finlshed.
Referring a~ain to Fi~re 58, another embodi~ent of
thl~ inventlon will now be described. In the figure, a P-channel
MOSFET (Gl) has a gate electrode made of N-type polycrystalllne
silicon 6', and a P-channel ~lOS~ET ~2) has a gate electrode
made of P-type polycrystalline ~lllcon 6.
Since these FET~ are ~anufactured under 3ub~tantially
th~ ~ame conditio~s except the conductivity type~ o~ the
gate electrodes, the difference of the thre~hold volta3es
Yt~ of both the FETs beco~e~ substantlally equal to the
difference of the Ferml level3 of the P-type ilicon and
the N-ty~e slllcon. ~he gate electrodes are doped wlth
,espectlve lmpurltles near the ~aturation densities, and the
dlfference become3 sub3tantlally equal to t~e ener~y gap Fg
- 52 -

of silicon (approxlmately 1.1 V)7 The V~n-dlfference can
be ta~en out at hlgh precision by makinOr the channel dimensions
of both the FET~ equal, and it ls utilized as a re~erence
voltage source.
Since a reference voltage generator device ba~ed on
suck a con~truction exhi`oits a ~mall temperature-dependency
and small manufacturing devlations, lt can be used for varlous
electronic circults.
In Figure 5&, numeral 1 desi~nates an ~-type sllicon body,
numeral 3 a thlck field oxlde fllm, numeral 2 a gate oxide
film, numeral 4 a P-type source region, and numeral 5 a P-
type drain region. Here, the N~type polycrystalline silicsn
gate 6' has a structure ~hich i5 doped wlth botn an ~-type
lmpurity and a P-type lmpurity, the density o~ the N-type
impurity being 1.5 time~ or more hiOher than the density of
the P-type lmpurity Alternatively. lt has a structure which
i3 doped with an N-type impurity, almost no P-type impurity
being contained, and nevertheleqs, which is self-aligned with
the source and drain.
The reason why the density of the N type i~purlty needi
to be 1.5 times or more higher than the denslty of the P-type
impurity is as follows~ In the ordinary hlgh-dens1ty impurity
doping technlques, the control o~ a density is sub~ect to
deviations of (~et ~alue ~ 20 ~ or so~ Accordingly, the
ratio between the deviations of the N-t~pe impurity density
and the ?-type impurity density becomes ~1.5 + 0.3)/(1.1 + 0.2~.
Slnce the mlnimum value of this ratio becomes 1/1, the Fermi
level of the polycry~talline ~illcon doped w~th both the
N-type and P-type lmpuritles ~aries greatly.
In order to allow ~ome extent of manufacturing dispersion,
- 53 -
.
.
,
,, ' !

~ 8~
accordin~ly, the ratlo of the l~purlty densitie~ need~ to
be 1.5 or greater without fail.
Flgures ~2(a) and 82(b) lllustrate a method of manufac-
turin~ I~F~Ts for settin~ the ratio of the impurity densities
at 1.5 or greater.
ta) ~n N-type silLcon body l at a comparati~ely low
impurity density (for example, below 5 x 10l6 cm 3) is
oxidized to form a thick oxide film 2 for isolatin~ element-~.
After for~ing a gate oYide film 3 in recesses of the film 2,
an intrln~ic semicondu~tor polycrystalllne sillco~ film at
6 and 6' is deposited by chemical vapor deposition.
Further, a mask oxide film 7 is formed on a selected area by
the chemical vapor deposltion. Using the oxide film 7 aq a
ma~k, the polycrystalline silicon film 6' is doped with an
N-type ~mpurity such as phosphorus or arsenic selectively
and at a high density (for example, above 5 x lOla cm ~).
Thus, the N-type polycrystalline silicon film 6' is obtained.
(b) After re~oving the ma~k oxide film 7, the wor~ing
of a polycrystalline silicon gate electrode i5 done by
photoetchlng, and source and drain lmpurity layers 4 and 5
are Lormed at a low density (for example, below 3.3 x 1018 cm 3)
by thermal diffusion of a P-type impurity such as boron.
Here, ~h? density of the N-type lmpurity with whlch the
polycrystalline film G' i~ doped in the stage (a) is made
Z5 1~5 tlmes or ~nore hlgh~r than the denslty of the P-type impurity
wlth which the polycrystalline silicon fllm 6' ~s doped at
the time of the L'-type lmyurity diffuslon in the stage (b),
whereby the polycrystalline iilcon gate 6' i~ held at the
N-type.
F~gures 83(a) ~o 83(d) illustrate another method of
- 54 - -
. ~.
, ~
.,~ .

9OBl
manufacturP accordin~ to thi~ inven~lon. ~igure 83~a)
~hows the same manufacturln~ ~tep ~ ln ~lgure a2(a).
- (b) After removlng the mask oxlde ~llm 7, the prooe~ing
of a polycrystalline ~illcon gate electrode is done by
photoetchin~. Thereafter, usln~ the polycrystalline sil~con
gates 6 and 6' aa a mask, the gate oxide fllm whlch overl$es
parts correspondlng to sources and dralns to be formed is re-
moved, whereupon the resultant silicon body is sub~ected to
oxidation in steam at 750C to 900C for 60 seconds
to 600 seconds. In the oxidation, the o~ide fllm-growth
rate of the 3illcon surface depend~ upon the d~nslty of ~n
impurity contained in the silicon. The oxide film-growth
rate becomes very high when the impurity density is at
least 5 x 1ol8cm~3, preferably 102 cm~3 or higher.
Therefore, comparatively thin oxide films 8 and 10
of 20 to 40 A are respectively formed on the surface~ of the
parts correspondinO ~o the source and drain and having the
comparati ely low impurlty density and on the surface of the
intrlnsic polycrystalline ~ilicon 6. On the other hand,
a comparatlvely thick oxlde film 9 o~ 70 to 200 A is for~ed
on the surface of the N-type polycrystalline silicon 3ate 6
havlng the comparatlvely hlgh lmpurity density.
(c) Boron can pas~ through an oxide ~ilm of a thickness
of at most 40 A by thermal diffusion, and cannot pass
through an oxlde fllm of a thlcknes~ of at least 70 A.
Therefore, boron iA ubsequently thermally d~ffused at
950 to l,CCO C ~or about 20 minutes. Thus, the boron
penetrates through the comparatively thin oxide films 8 and
10 to for~ +he P ty~ lm?urity 'a~ers 4 and 5 a.nd the ~-type
pol~cry~alline ~ilicon layer 6~ At this time, the ~-type
- 55 -
l ~
~,
6~

~L~.9Le3~138:3L
polycrystalline sllicon layer ~' is protected by the ccm-
ratively thick oxlde film 9, and it i3 not doped wlth the
boron. As an alternative ex?edient, before the ther~al
diffusion of boron, the oxide fllms are etched with an
etchant consisting of HF : H20 = l: 99 for 60 seconds, to
remo~e the ox~de films 8 ~nd lO and to leave the oxide fil~
9 with a thickness of 40 - 50 A. Thereafter, the thermal
diffusion of boron i3 carried out. Thus, a simllar structure
is obtained.
(d) Thereafter, a phosphosilicate glass film ll is
formed, contact holes are formed, and aluminum electrodes
12 are formed. Then, the fabrication of the device ls
completed.
Although the present method of manuf2cture has been
explained as to the case o~ the silicon gate P-channel MOSF~T3,
quite the same applies to the case of P-channel l~tOSFETs in a
silicon gate CMOSIC.
Now, circuits according to embodiments of this lnvention
for derlving the difference of the threshold volta~es Vth o~
the MOS transl~tors wlll be expla~ned.
Although the circults described below can beco~e ex-
pedlents for taking out the differences of the Fermi level3
(Efn ~ Efp), (2fn - E1) and (E1 - E~p), they are further
. applicable as reference voltage generator devices whlch in
general, utillze as a reference ~oltage a voltage based on
the difference of the threshold voltages Yth f FETs havln3
unequal threshold voltage values.
Flgure 6(b) shows a circuit which ~enerates ~oltagec
correspond-ng to threshold voltages o~ MOS tran~istors.
Transii3tors Tl and T2 construct the so-called MOS.dlodes
- 56 -
~, ,;, "
., ,. ~ -' ,''~
, i-

~n which dralns and gates are connected ln common.
o designates a constant-current source, and Tl and T2
~ndlcate MCS~Ts whlch have ~nequal thre~hold vol-tages Vthl
and Vth2 as indicated in ?lgure 6(a) and substantlally equ~l
mutual conductances ~. Lettin~ the dr2in voltage~ OL the
respective tran3istors be Vl and V2,
/ ~ ( Vl Vthl )
/2 ~ tY2 Y~h2) .. ~......... ..(21)
; Therefore,
V
V2 Vth2 ~ ........ 7 ( 22)
By takin6 the dif;'erence of the drain voltages, the difference
of the threshold voltages can be derived.
As the constant-current sources, sufficiently high
reslstances may be used. If their characterlstlcs ar~
uniform, diffusion resistanc~,polycrystalline Si resistances,
resistances formed by ion implantation, or high resistances
. formed of MOS transistors can be used.
'~hen, 1n this circuit, the N~ gate P~channel MOS and
the P+ gate P-channel MOS previously explained with reference
to Flgure~ 58 and 59 respect~vely are u~ed a~ the tr~nslstors
Tl and T2, that dl~ference (~n ~ E~p~ of the Fer~i levels
f the N-type semiconductor and the P-type semiconductor
wnich is a value substantially equal to the di~erence
of the threshold volta~e~ can be derlved.
Besides by making th-~ co~Ga~tlcns of the gate electrodes
different, i . is posslble to endow the unequal threshold
voltages by, for example, implan~ing ions into the channels,
- 57 -
V ~ -- .
~ ~ , .
~,' ,~ ~ ,
,
. . '~

~ 8~
alteriDg the thicknesses of a doped ~ate oxlde or 2ate
lnsulatin~ fll~s, ~tc. When such a meai3ure 13 applled to
the circult of Flgure 6(b), the dlfference of threshold
voltages corresponding to the implanted quantlties of the
lons or the difference Or threshold voltaOes correspondin,
to the quantltles of an lmpurity wlth which the gate insulat-
in~ films are doped or correspondin~ to the thicknesses of
the ~ate insulating films can be similarly derlved as the
re~erence voltage.
For example, the ion implantatlon ls ~uch hi3her in the
precislon of the impurlty concentratlon than the conventional
diffuslon because the quantity of implantation can be ~onltored
in the form of current. Fi~ure 7 illustrates thls situation.
~ven if, lettln~ Tl denote the char~cteristics of MOS transistor~
before the lmplantation of ions, they haYe been indivldually
dispersed during manufacture and the threshold valuei are
individually shifted by ~Vth on account o~ the lon implanta-
tion, the ma~nltude ~Vth bein.~ the di~ference of both the
threqhold voltageis ii~ deter~lned by the quantlty of the ion
implantation and is therefore dispersed to an extremely small
extent. It can accordingly be similarly used as a reference
voltage with little dispersions of manu~acture. More
specifically, letting Vthl indicate the threshold voltaye of
the MOS transistor Tl which is not subjected to the ion
implantation, likewise to Equation (15): -
y ~ ~ QSS '~B ............................ 0... ~23)
Lettin~ ~QB indlcate the i~crement Or flxed c~.an~es i~ the
substrate due to the ion implantation, the threshold ~olta~e
Vth2 of the ~0~ transistor T2 sub~ected to the ion i~plantation
- 58 -
~, ~
?, , . . : . . .
~ .

beco~es:
F COX COX ~.,...... (24)
: Accordin~ly,
Vthl Vth2 COX ....... (25)
The temperature varlation of this difference voltage between
the thre3hold voltages is extremely small because QB ls
almost lnvariable against temperature changes.
Additional ~reat advantage~ are that the reference
voltage can be freely ~et by the q~antity of ion lmplantation
and that the device can be easlly produced even by a single-
channel rlOS manufacturin3 proce~s.
~i~ure3 ~ and 9 show examples of circuits wherein an
~l+-~aie F~T Tl and a P+-gate FET T2 havinc unequal threshold
voltages as ln the case of Figures 6(a) and 6(~) are u3ed,
and the F~T Tl is connected in the ~IOS diode form and i~
connected ln serles wlth the FET T~, to derive the
difference of the threshold voltages. It is ~uppo~ed that
the ~T Tl has a threshold volta~e Vthl, while the F~T T2
has a threshol~ voltage Vth2.
Under the conditions in which a resistance Rl is
sufficiently great as compared with the impedance of T
and that a resistance R2 is suf~iciently great as
compared with the impedance of T~,
Vl - V2 ~ Vthl .................... ~... (26)
Vl Yth2 ........................ (~7)
Therefore, Y2 ~ V~hl ~ Vth2 ..................... (28)
F gure ll(a) shows a device wh~rei~ voltage~ correspond-
ing to the thre~hold voltages of a~ .~i+-gate ~CS Tl a~d a
P+-gate MOS T2 are ap~lied to both termlnal of a capacitor
- 59 -
. ~
~ ~J ~ ~
.

Cl connected to the ~OS transistors, and a voltage held
ln the capacitor i~ taken out as a difference voltage.
Fl~ure ll(b) depicts the operating timings. ~OS ~ETs T5
and T6 are turned "on" by a clock pu}se ~1~ to charge t~.e
difference voltaOe of the threshold voltages Vthl and Yth2
of the ~OS F~T Tl and T2 ln a capacltance Cl.
After turning the ~SOS F~Ts T5 and T6 lloff" by th~ pulse
~1~ a MOS F~T T3 is turned '1On" by a clock ~2 so as to
~round a node ~ of Cl. Slnce9 at this time, the difference
~oltage of the tnre~hold volta~es is retained ln Cl, the
difference potential appears at a node ~ of the capacitance
Cl as it ls. In the case of a use for voltage detector circuit
to be stated later, the po~ential of the node ~ at this tlme
can be employed as a reference volta4e as it is. In order
to permit the use in a more general form, however, transmission
~ates T6 and T7 are turned "on" by a clock ~3 wlthin a perlod
of time ln which the high level signal o~ the clock ~2 is
enterlng, the potential i~ held ln a capacitance C2 connected
to the non-inverting input (+) of an operatlonal ampllfier 5,
and the ~otentlal i~ recieved by the so-called voltag~ follower
in which 100 ~ of an output is negatlvely fed back to the
inverting input (-) of the operational amplifier 5. Then,
as the output of the voltage follower, th~ difference of the
. threshold ~oltages of Tl and T2 is obta.~ed as a reference
voltage when the internal .impedance is sufficiently
low.
~i~ure lO(a) is a circuit diagram showing an embodlment
of a dyna~lc type di~ference volt~ge output circuit which
exploits t:qe diffe.ence of the threshold voltages of an
N+-gate ~.-char~el ~09 ~1 and a P+-gate N-channel ~OS Q2.
- 60 -
.
l ,
, 1~ ~ .
: ~ .?
,

~ 8
In this clrcuit, he gate~ and drains of the MISF~T~
(Ql~ Q2) are interconnected, and they are connected to a blas
power supply -VDD through load resistors (Rl, R2). A capacitor
(C) is interposed between the gate and drain terminals, and
the difference component between the threshold voltages of
the MISr~Ts (~1' Q2) is stored in the capacitor so as to
provide an output. More specifically, a P-channel MISFET
(~3) which ls driven by a clock pulse (~) is incorporated
between the gate and source of the MISFET (~l) of the smaller
threshold ~oltage. The respectlve load resistance~ of the
MIS?ETs (Q1~ Q2)' and the "on'l res~ance of the i~lISFrT (a3)
is made sufflclently smaller than the "on" resistances of
the ~.IS~Ts (Ql~ Q2)- Owing to such a cl.cuit arranOement,
as shown in an operatinO wavefor~ dia3r2m of ~igure lC~b),
when the clocX pulse ~ has reached a low level to turn the
MIS~ET (Q3) "on", the difference -(V2 - Vl) between the drain
voltages (threshold voltages Vl, V2) of both the MI~FETs
~ Q2) is provided from the drain o~ the MI~F~T (~2) or
the terminal of the capacitor (C) remote from the MISF~T (~3).
The difference Yoltage output similar to those of the fore-
going circuits are obtained by sampling it at the time (~).
Figure 12 shows a reference ~oltaOe generator device
which utilizes an N+-~ate ~IOS T~ as well as a P+ -gate MOS
T2 and ~ capacitance C2 similarly. A MOS Fr T T8 is turned
"on~ by a clock ~l- At thls time, a MOS FET Tg i5 in the
"off" state owin3 to a clock ~2. The potential of a node
become lower than that of a node ~ by the threshold voltage
Ythl of the MOS F.T T1, and the po~enti~l of a noda ~ becomes
lower than that of the node ~ by the threshold volta~e Vth2
of the MO~ F~T T2 Accordin~ly, the difference voltage of
. - 61 -
~' , , ' - ;
. t~J~

both the threshold voltages Vt,~l and Yth2
the capacitanc~ C2. Subsequently, the l~OS ~T T8 ls turned
"off" by ~1 and the ~OS F~T Tg is turned "on" Dy ~2. Lhen,
the difference ~oltage of the threshold vol~ages is provided
at the node ~ .
Figure 13 shows an operational am?l~f~er accordin~ to
th~ principle of this invent~on. Tl and T2 deslgn~te a differ-
ential pair constituting a differantial amplifier clrcult,
and Tl2 and T13 deslgnate active loads of the di~fer~ntial
ampllfier. ~ transistor Tll forms a constant-current
circuit together wlth transistor~ Tl4 and Tl6. Transistors
T15 and Tl6 constitute a level shift output buf~er circuit
whose constant-current source load is the transistor T16.
Although the e~a~ple of a circult arrange~ent based on C-iiOS
is shown in the figure, the circuit can o~ course be constructed
of single-channel MOS.
In this operational amplifier, the differential pair
tran~istors Tl and T2 constltutin3 the diffarential amplifier
circuit are especiall~ endowed with unequal threshold volta~es
Ythl and Vth2 on the basis of the ~ermi level difference of
the gate electrodes stated before 7 the dif4erence of the
threshold voltages can be utillzed or derived as a(reference
volta~e. This is an applicatlon of the operational amplifier
which has hitherto not been existent.
FlOure 14 chematically depict3 an ordinary operational
a~plifier by picking up only the differentlal portion thereof.
It ls here assumed that MO~ transistors Tl and T2 have un-
equal threshold voltages 'Jthl and Vth2 respectiYely and that
the other oharacteristics such as mut~al conductances are
equal. ~lgns (-) and (+) appearlng on the ir,put side
- 62 -
, ~

8~
-slgnlfy the inverting and non-invertin~ inputs, respectively.
Letting Vl denote an in~ut voltage of the tran~istor
Tl and V~ an input volta~e of the translstor T2,
Vl -- Ythl a ~J2 Vth2
that ls,
Vl - V2 ~ Vth1 ~ Vth2 ..................... (29)
~he output level chanc-es with this inpu~ voltage condition
as the boundary.
The operational amplifier ls endowed with an input
offset corresponding to the dif~erence voltage of the thres-
hold volta~es. Therefore, when either of the inverting
lnput (~) and the non-inverting input (+) is grounded or
connected to a reference potentlal of a power sup-ly, it can
be operated as a ~oltage comparator whose reference voltage
is the offset voltage. Cn the other hand, when the output
is connected to the inverting input terminal (-) to construct
a voltage follower c1rcuit and the non-inverting input ter~inal
(+) is grounded as shown in ~igure 14, the difference of the
threshold voltages ls obtained at the output Out. In this
case, in order to effect the operation of the operational
amplifier, the transistor T2 needs to be of Ihe depletion
mode MO~ r ~T. For example, in case of usin3 the P~-gate
MOS for T1 and the N+-gate MOS for T2, they may be ~ade the
depletion type by sub~ecting the channel portions of both
the MOSF_Ts to the ion implantation under the same conditions.
Figure 15 shows a device which can arbitrarily set a
reference voltage by the u e of the operational amplifier .n
Figure 14. An output is fed back to the inverting input (-)
through voltaJe divider mean~ Rg and R6. Thus, letting r
- 63 -
~ ~ , --- .
, ,'~ . `'`'.
~t, ~ ~

~ ~9~8~
denot~ ths volta~e divl~ion ra~lo R~/A~R6, the output
voltaOe V becomes:
yO ~ thl__ th~ ................ ~........ (3C)
The volta~e divlder means R5 and R6 should desirably be
l~near resistances, but any resistances may be adopted
insofar as their characteristic~ are sufficlently uniform
to z per~isslble extent.
~hereas the circults of Figures 14 and 15 premise the
use of the depletion type MOS, circuits in Figures 16 and 17
are ~ade operable with enhancement type PiOS. Of course, the
depletion type MOS may well be adopted.
Likewlse to the example of ~iOure 14 7 the example of
~isrure 15 directly feeds an output back to an inverting input
(~)- Letting V~D denote a supply volta~e, the output VO
becomes:
Vo 3 VDD - (Vthl ~ ~th2) o- ----- -- (31)
With the circuits of Figures 14 and 15, at least one of the
differential pair transistors need~ to be put into the de-
pletion mode, which necessitates an increase in the number of
manufacturing steps in some cases. However, they can derive
the difference voltage of the threshold voltages Vth with
reference to the ground potential.
Conversely, with the circuits of Figures 16 and 18, th~
reference o~ the difference ~ol~age to be obtained ls not
the ground potential. However, the conditlon of the operatin~
mode of the ~ET is not imposed.
'~rnlch clrcult for~ is to be adopted may be decided by
the merlt or demerlt to which more lmportance is attached.
Llkewlse to the example of Figure 15, the exam~le of
- 64 -
.
, ,,
', ' ` . ~ ' ' ,` `
i ~

8~
Fi~ure 17 feeds an output back to an invertlng lnpu~
throu~h Yoltage divid~r means R7 and ~8~ The output become~;
V0 - V~ _ thl th2 ........................ 0.... (32;
~igure 18 shows a volta~e detector circl~it wherein a
reference voltage VR from a reference voltaOe generator
device RVG accordin~ to this invention which exploits the
difference of the threshold voltages Vth i~ ap~lied to one
input of a convent~onal voltage comparator VC and a voltage
V~ to be detected is applied to the other input, whereby
the height of the volta~e to-be-detected Y3 relative to the
referenoe voltage VR can be discriminated.
.;n example ln Flgure 19 i5 a voltage detector circuit
wherein a reference volta~e VR from a reference volta_e
generator device RVG which utilizes the dlfference of thres-
h~l~ voltaOes Vth corresponding to the Fer~i level difference
of gate electrodes in accordance with thi~ invention is
applled to one input of a voltage comparator VC and wherein
a voltage obtained by dividing a voltage to-be-detected VD
~ith voltage divider means Rg and Rlo is applied to the other
lnput. Le~ting r denote the voltage divi~ion ratio, Vref
denote the reference voltage and VSense the detectlo~ level:
Vsense = ref .~...O.. (33)
The detection level Y~en~e can be arbitrarlly ~et through
the vol~age division ratio r.
An exa~ple in ~lgu,e 20 is a ~oltage detector circuit
which uses the operational a~plifler with t~.e o~fset corres-
ponding to the dlfference o~ the thre3hold voltages Yt~ as
~0 described wit~ reference to r igure 13 and exploits the offset
- 65 -
~ .~ ` ,
. .

voltage as a reference voltage as explained previously.
Rll and R12 lndlcate voltage divider means as ln thé exa~ple
of F1gure l9.
If the volt~ge to-~e-detected VD i.~ a battery supply
voltage ln the example of Figure 18, l9 or 20, the voltage
detector circu't can be utilized as a battery checXer in a
sy3tem which uses a battery as a power ~upply. A concrete
example in which the voltaOJe detector circuit of Figure 20
is applied to the battery checker of an electronic tlmepiece
105 is shown in Flgure 54, and will be described ln detail later.

Figure 21 shows another embodiment of an operational
amplifier circuit which is constructed by connecting in
; the differential form N-channel MOS FETs Ql and Q2 having
unequal threshold voltages Vth on the basis of the differ-
ence of the Fermi levels of gate electrodes in accordance
with this invention. ~OS FETs Q3 and Q4 operate as load
FETs of the dlfferent~al pair MOS FETs Ql and Q2' and
a MOS FET Q5 operates as a constant-current scurce of
the differential palr MOS FETs Ql and Q2.
Figure 22 shows a di~ferential amplifier circuit
which has as its of~set voltage the d~fference of the
threshold voltaOes Vth o~ MOS transistors Ql a~d Q2
according to this invention.
Figure 23 shows the drain current - versus - gate
voltage characteri~tics of the MOS transistors Ql and
Q2 in Figure 22.
In this case, the mutual conductances of the MOS
transistors Ql and Q2 constituting the dlfferential
pair are designed so as to become equal. As the current
of a constant current source CS of the differential
circult cAanges to Io~ Io~ and Iol', their points of
CS ~ S character~stic of
the transistor Ql vary to poln ts 1, 1 ' and 1 " and
their points of intersect1ons with the VGs ~
characteristics of the transistor Q2 ~ary to points
2, 2' and 2~. At first, voltages VGl and VG2 are appl~ed
to the gates of the respective transistors Ql and Q2 in
order to bring the differential circuit lnto ~e balanced
state. Herein, e~en when the current o~ the cons~ant-
cu.~rent source CS has cAanged from Io to Io~ or Iol' ~n
- 67 -
.
,
,, ~''" , `'.
. ~
.
,

o~
dependently of the temperature, the difference of the vol-
tages VGl and VG2 which balance the dif~erential circult
are held substantially constant. In actuality, t~e
difference voltage reI~lects the d~fference (Vthl - V
o~ the threshold voltages of the transistors Ql and Qz
as it ls. Accordingly, the temperature characteristic of
the differenCe (Vthl ~ V~h2) of the threshold voltages
of the tran~istors Ql and Q2 a~pears as it is, as the
diffei-ence (VGl - VG2) of the voltages to be applied to
the gates of the transistors Ql and Q2 in order to put
these transistors into the balanced state.
Y~èn the P+-gate and N~-gate N-channel M0~ transistors
previously described are respectively used as the transis-
tors Ql and Q2~ a voltage of approximately 1.1 V
corresponding to Ihe band gap is obtained. In the case
of a silicon semiconductor, this difference voltage
has a temperature gradient of ~0.24 mv/C.
me temperature dependency of the difference voltage
of the gate voltages can be nullified by maklng the
values of the conductances of the transistors Ql a~d Q2
unequal.
It,ls supposed by ~ay o~ example that the temperature
dependency of th2 co~s~ant~current source CS of the
differential circuit has a positive gradlent, while
the dif~erenCe (~l~hl ~ V~12) f the threshold voltages
of the transistors Ql and Q2'1 exh~bits a temperature
dependency of z negatiYe gradient. As indicated at Ql
and Q~" ~n Figure 23, the condtlc~ance of Q2" is made
f~maller than the conductance -~ Ql' whereby the gate
voltage of the transistor a2 under the balanced state
- 68 -
,,,
, ~ ' '
f,

638~
varies as indicated at 3, 3' and 3" in dependence on
the temperature, and the temperature dependency of the
difference of the gate voltages of the transistors Ql
and Q2" as based on the dlfference of the conductances
of the transistors Ql and Q2'i has a positive gradient.
By properly combining the magnitudes of the conductances,
the total temperature dependency can be made zero or
can be improved substantially.
When the temperature dependency of the
cons-~nt-current source of the differenti~l circuit has
a negative gradient, the conductance of the transistor
Q2' is made greater than the conductance of the transistor
Ql conversel~ to the above, whereby the temperature
dependency can be improved to zero.
Under the balanced state, the following relations
hold among the current Io f the constant-current source,
and the threshold voltages Vthl and Vth2, mutual conduc-
tances ~1 and ~2 and ga~e voltages VGl and VG2 of the
respective transistors Ql and Q2:
0 ~~ ~ (VGl ~ Ithl) = ~~ ~ (Vc2 ~ Vth2)2 ....... (34j
VGl ' Ythl ~ ~2 I /~1 .o.(35)
VG2 = Vth2 + ~ 2 I /~2 ... (36)
~25 VGl ~ VG2 ' (Vthl ~ V~h2) ~ ( 1 ~
.~.(37)
In ~quation (37), when ~1 > ~2~ , and ~hen
~ 2' ~ ~ ~> 0. Therefore, the temperature
gradient of the second term of Equatlon (37) can become
- 69 - i
r
.

`:
both posit~ve and negative.
~ igures 24 and 25 show application circuits of
voltage comparators each being another embodiment ~ich
can reduce the temperature dependency on the basis of
the concept described above.
In Figure 24, ~IOS FETs ~1 and ~2 whose threshold
voltages Vth are unequal owing to the difference of the
Ferml le~els of gate electrodes in accordance ~ith this
inventlon are operated as source follo~rers. ~he balanced
state corresponds to the time when the di~ferential
input voltage of a voltaOe comparator circuit or opera-
tional a~plifier circuit C~1 becomes O (zero) volt.
Under the balanced state, the follo~,ing relations hold
among the threshold voltages v~l and Vth2, mutual
conduc~ances ~ and ~2' gate voltages VGl and VG2, source
voltages Vl and V2 and drain currents Il and I2 of the
respective klOS FETs Ql and Q2:
Il 2 ~1 (VGl ~ Vthl--Vl)2
202 ~~~ ~2 (JG2 ~ Vth2 ~ ~2)2 ... (3~)
Vl = Vz ... (39)
Accordingly,
. . . _
Gl Vtbl + Vl ~ ~2 I~ ... (40)
25JG2 = Vth2 ~ Y2 +~ 2 I2/~z (~)
rGl VG2 ~ (Vthl ~ Vth2) + (~ 2 Il/~ 2 I2/~2)
...(42)
~hus, assu~i~g that Il = I2 ~ he tempera~ure
Y (~Gl ~ VG2) can be made zero by appropriat21y
- 70 -
. ~
.

~ 8~
setting ~1 and ~2 in conformity with the temperature
dependency of I and ~he temperature dependency of (Vt~l -
Vth2) qulte similarly to the case of the differential
circuit.
Further, in this example of the circuit, assuming
that ~ 2 = ~ Equation (42) becomes
VGl--VG2 ~ Vth~ Vth2 ~ ( ~ 1 - ~ 2) . .(43)
Therefore, even ~en the currents Il and I2 are set
at unequal values, the tempera~ure dependency of the
(VGl - VG2) can be similarly ~ade 0 (zero)
As an example of a constant-curre~t circult, one
as sno~n in Fi~ure 26 is considered. Here, when the
conductances of FETs Q2 and Q3 are made 1 : n, a current
flowing through the FET ~3 can be made n.I relati~e to
a current I flowing through FETs al and ~2.
Accord~n~ly, Il and I2 in Equation (43) can be
readily realized by changing the ratio n in the above
constant-current clrcuit.
ZO Figure 27 shows an embodiment of a specific form
of a re~erence voltage generator circuit ~ased on the
differential circuit of Figure 220
t rs Ql' Q2' Q3 and Qg enclosed with dotted
lines in Figure 27 constitute a constant-curren~ circuit
similar to ~hat in Figure 26, while transistors Q4, Q5,
a6, Q7 and Q3 constit~te a dlfferentlal circui~ similar
to that in ~igure 22, ~ere, the transistor ~6 is a
P~-g~te ~I-channel MOS transistor, and the ~ransis'or
~ is an ~J+-gate N-char~el MOS tran~istor.
The arrow symbols of the gates represents the N~-gate and
- 71 -
,

9~
~he A~+-gate discriminatingly.
The ~IOS transistors ~6 and r~ have their threshold
voltages shifted by equal values by mearAs of the ion
implantation or the liXe, and the MOS transistor ~ is
made a depletion ;IO~ transistor.
An output based on transistors Q8 and Qg is negatively
fed back to the gate of the transistor Q5. For an output
voltage, the offset voltage o~ the transistors a6 and
Q7 can be used as a reference voltageO Letting VO denote
the output voltage and letting in Equation (37)
VGl Vo, VG2 0; rthl = Vthn+j Vth2 = VtA~p+,
~1 ~6 and ~2 = ~7, then: -
VO - Vthn~ ~ Vth + ~ ~ ( 1 1 ) ( 44)
, (Vthl ~ Vth2) is the di~ference between
the threshold ~oltages of the P+-~ate ~i~^channel ~IOS
transistor and the ~+-gate N-channel ~OS transistor
and become substantially equal to the band gap voltage
of 1.1 VO Tne outpu~ voltage VO has the form in which
the correctionA voltage of the second te~m ~s added to
the band gap voltage.
- Letting the mutual conductance of tA~e transistor
Q1 be ~1~ and supposing the drain v~lta~e of ~he transis-
tor Q2 to be substantlally eaual to the ~kreshold voltage
Vt~ thereof,
o = '~1[(YDD ~ Vthn)(JDD Vthp)
~ (~DD ~ Jthp) ~ ~-(45)
In addition,
~ P (~/L)l
- 72 -
--
.

81
~ 6 = ~ON('r/L)6~ 7 ~or~( ~JL)6
.rhere
~ Op and ~ON denote the mutual conductances per ~nit
area of the ~-~iO~ and P-MOS transistors> respectively.
Accordingly 9 the output voltage becomes:
VO Vthn~ ~ Vthp+ +
. .
~('.I/L)7 _ ~
~(,I/L)s (W/L)7
DD thn) (VDD Ythp) ~ 2 (VDD - Vt~ )2]
...(46)
Differentiatlng Equation (46) as to t.~e temperature T,
~ ~ ( thn+ Vthp+) +
L)~
~ L~6 (~'I/L)7
x ~ DD thn)( DD thp) -~~(VDD Vthp) ]
...(47)
('~/L)6 and (I~J/L)7 can be set so ~hat a '. may be held.
Figure 28 shows an embodiment of a reference voltage
generator circuit which is based on the principle const-
ruction of Fi~ure 24. A circuit within dotted lines inFigure 28 forms the comparator circuit ~1~l in Figure 24.
s Ql~ a2- Q4 and Q~ constitute a cons-tant-
cuL~rent circuit. Currents to ~low tLhrough transistors
a3 and Q5 can also be made unequal by making the
ratios of the conduct2nces of the transistors Q4 and
- 73 - j
, ...
g

Q6 different relative to the conductance of the transistor Q~.
Here, the transistors ~3 and ~5 are an N -gate
N-channel MOS tr&nsistor and a P -gate ~--cnannel i~lOS
transistor respectively
~s in the foregoing, the output voltaGe VO is neOa-
tively fed bac~ to the gate of the transistor Q3 so as to
form the voltage follower, and the ground potential
is applied to the transistor Q5.
rhe tem~erature dependency of the output voltage
can be made O (zero) by making the conduc~ances of the
transistors Q3 and Q5 or the conductances of ~he transistors
Q4 and ~ unequal in accordance ~ith ~q atio~ (42) or
(43) 7 or b~J combining bo~h these measures
By wa~ o~ example, it is supposed that the conduc- -
tances of the transistors Q3 and ~5 are equal &nd ~, -
that the current to flow through the transistor Ql is Io~
and that the ratio of the conductances of the transistors
~2 and Q4 is 1 : n, while the ratio of the conduct&nces
of the transistors Q2 and Q6 is 1 : n'. Then, the output
~olta~e tJo becomes:
VO ~ Vthn~ ~ VthPt- +¦ '~ -,~, (48)
~y ad~usting ~he values of n' and n, the temperaiure
2~ dependenc~ of the output voltage VO c~n be made subst~tial y
zero. A further circuit arrangement which generates a refer-
ence voltage and which can reduce to zero or at least improve
the temperature dependency of the reference voltage, is shown
in Figure 25, in addition to the foregoing circuit arrangements.
This circuit is operated with the sources of transistors.
- 74 -
;~
.,,
:~ '~' , . . ~

Ql and Q2 ~rounded.
~ n example in Figure 29 is a clrcuit of a constant
current ~hich is determined by the difference of the
thresnold voltages of ~IOS F~Ts Tl and T2 in ac^ord&nce
~rith this in~ention,
The MOS FETs Tl and Tz have equal mutual conductances
~, and their threshold vGltages have values Vthl and
Vth2 ~ifferent from e~ch other owing to the difference
of the Fermi levels o~ gate electrodes in accordance ~Jith
this invention. If a resistance R20 is sufficiently
high as compared with the impedance o~ Tl, the drain
voltage (= gate voltage) Vl of Tl becomes substant~all~
equal to Vthl.
l~ihen T2 is in the saturation region, a current
I2 flowinO through T2 is:
IOUT ~ ~~~ (Ythl ~ Vth2) --(49)
An example in Figure 30 is a constant~current circuit
employing a reference vol~age generator device RVG which
ge~erates a reference voltage V ~ (= Vthl - Vth2) decided
by the difference voltage of the threshold voltages
of ;~OS FETs corresponding to the d1fference of the Fermi
levels of the gate electrodes thereo~ in accordance
with this i~vention,and an ordlnary operational ampli~ier
~C. In the constant-current circuit, a voltage drop
IoUtR2l ba~ed on a current I flowing through a MOS FE~
T22 i~ compared wl~h a reference voltage YRE~, and the
gate voltaOe of Tl is controlled so that both may become
equ~l at all times.
- 75 -
. ~
. ..
~ , ;, `, .

8~
Out 21 ; VI~EF,
IOut = ~ ...(50)
iIere, the reference voltage may be obtained by
endowing the operational amplifier VC ~ith an offset
and grounding tl~e non-inverting input (+) of the opera-
tional a~plifier ~C as in the ~oregoing example of Figures
13 and 14.
~n example in Figure 31 is a constant-current circuit
wherein -the so-called current mirror circuit in ~hich
i;O~ transistors T31 &nd T33 have the sa~e cha-acteristics.
An example in Figure 32 is an ap~lication ~.~erein
a reference voltage VREF ~hich is decided by the difference
~oltage of the threshold volta~es of MOS F~Ts corres~o~ding
to the difference of the Fermi levels of the ~ate electrodes
of the l~IOS FETs in accordance ~th this invention is
exploited for a stabilized power supply circuitO A
reference voltage generator device RVG is constructed
by any of the above-stated several methods according to
the principle o~ this i~ventisn. A divided voltage of a
stabilized output owi~g to ~oltage divider me~ns R13 and
R14 and a reference voltage are compared9 and the gate
~olt ge of a controlling MOS F~T T20 is controlled so as
to brinO them into agreement, thereby to stabilize the
output voltage VOut. ~ny operational amplifier may be
used as long as it~ characteristics are allowable.
In theexample o. Figure 33, the ~lOS transistor used
for ~20 in the exa~ple of Fi~ure 32 is replaced w1th a
bi~olar trans~stor TRl.
.,
- 7h -
., ~ ~ _
" ~`'` ;
, ,...

8~
An example in Figure 34 uses the operational amplifier
VC as shown in the example of Figures 13 and 147 which
has the offset voltage based on t~e difference voltage
of the threshold voltages Vth of MOS FETs and whose non-
inverting input (+) is grounded. T2l may be a MOS tran-
sistor, a bipolar transistor or a junction field-effect
transistor,
Figure 35(a) sho~rs a voltage regulator according
to this invention ~irh is a fur~her improvement on th~
1~ stabilized power supply circuits illustrated in Figules
32, 33 and 34, and Figure 35(b) is a characteristic diagram
thereof.
The circuit arrangement in Figure 35(a) has the
construction of a comparing voltage reO~ulator. It differs
from a conventional voltage comparator in -that the input
characteristics of an operational amplifier VC being a
voltage comparator are asymmetric at the input terminals
of an non-invertlng input (+) and an lnverting input (-).
That is, this voltage comparator does not b~lance ~hen
the voltage levels of ~he non-inverting input (+~ and
the inver~ing input (-) are e~ual to each other~ and it
b~lances ~he~ a predetermined hlgh input voltage (in ~he
absolute value3 is applied on the invertlng input ( ).
In other words, in this voltage comparator, the lnput
levels of the non-inverting input (+) and ~he inverting
input (-~ have ~n offset with respect to the balance
point.
On the other hand, according to a conventional
voltage reO~ulator, in case where an input voltage Vln
is 'nigh, an output voltage VOUt depends upon a reference
- 77 -
. _ . .
~; `
, . ..

voltage Vref generated from the re~erence voltage gene-
rator RVC and the dif erence of VOUt ~ Vln ~s made
large, whereas in case where the input voltage Vin is
low, VOUt depends solely upon Vi and the difference of
llin Voutj is made s~all. According to this in~ention,
the changing point P between both the cases is set at a
point of Vin 3 Vl with respect to the input voltage Vin
(Vl lndicates the lowest operating voltage of a regulator
load L).
According to the voltage regulat~r of this irven-
tlon thus constructed, when the input voltage Vi~ is
higher than the lowest operating voltage Vl, the load L
is operated by the output voltage VQut which is higher
than the lowest operating voltage Vl but lower than the
input voltage Vin, and hence, the power dissipation is
reduced while ensuring proper operation. When the input
voltage Vin is low, the load L is operated by the output
voltage which is substantlally equal to the ~nput voltage
Vin or some~Yhat smaller than it, and hence, a volt~ge near
~he lowest operating voltage Vl of the load L for the
lnput volta~e Vin is supplied~ Since the output ~oltage
VOU~ is reduced to a voltage suited to the load L for
the high lnput voltage Vi~, this voltage regulator can
endow the load L with a low power dissipation and a wide
range of input voltages Vin.
Such an e.fect of this invention w~ll be described
in detail with re~erence tG the graph of Fi~lre 35tb)
in comparison with the prior-art voltage comparing regu-
lator having no offset~
In the fiqure, the abscissa represents
- 78 -
,,
i

the input voltage Vin,while the ordinate
represents t.he output VOUt and the reference voltage
Vref. ~traight line al indicates V t equal to V in
other words, a virtual curve in the case wnere the load
L is operated directly by the input voltage Vin without
employing the voltage generator.
Curve c indicates a reference voltage Vrefl generated
from any of the reference voltage generator devices in various
forms. Depending on the type thereof, the reference voltage
generator circuit device RVG utilizes various parameters
of semiconductor devices such as the threshold voltage
Vth of a ~IOSFET, ~he ~u~ual conductance m~ the forward
voltage V~ or back.~ard Zener voltage Vz of a PN-~unction,
and the current gain hfe of a bipolar transistor. There-
fore, the reference voltage Vrefl depends upon the supplyvoltage Vin according to the voltage dependency of ~he
parameter [ Vrefl ' ~ (Vin) J-
When the reference voltage Vrefl is
used as the reference ~oltage of the voltage comparator
circuit YC and where the comparator circuit YC is not
endol~ed with the off3et as previously stated, ~he output
voltage VOUt becomes e~uaI to the reference voltage V~efl
and agrees with the curve c. Since the reference voltage
Vrefl does not become higher than the .Lnput voltage
Yin, the outpu~ voltage YoUt become3 lower -than the in~ut
vol~age Vin in any range. As a result, the input voltage
Vin at the time when the outpu~ voltage VO,lt becomes
equal to the lowest operatin~ voltage Vl of the load
(point ~) becomes V2 (V2 > Vl). Accordingly, the usable
range of input voltages Vin as viewed from the load L
- 79 -
~, ~
,

-
8~
suI~fers a loss of a voltage component corresponding to
IV2 - vll.
In order to ~ake this loss small, in the volta~e
reOulator of Fi~ure ~5(a) according to this invention the
operation21 amplifier VC making up the voltage comparator
balance~ when the inverting input (-) has become higher
than the non-inverting input (+) by the offset voltage ~off.
In consideration of the offset voltage ~Voff of the
operational amplifier VC, a reference voltage Vref2
(curve d ) wh i ch is smaller than the virtual reference
voltage Vre~l and ~hich has a similar characteri~tic is
employed as an ac~ual reference voltage Vref. The v.lues
of Vref2 and ~Voff are set so that a substantial co~.pari-
ltage (Vref2 ~ ~Voff) at an input voltage V3 in
the normal operation may become equal to the virtual
reference voltage Vrefl, namely~ that it may agree with a
desired operating point ~0
With such a construction, the voltage comparator VC
formed into the voltage follower balances under the condi-
.. . . . ......... .
n of ~out ' Vref2 + ~Voff- SInce input voltages Vi
satisfying the balance condition are only Vin ~ Vref2 +
o~f ~ .,
When the input voltage Vin is smaller than
(~ef2 + ~Voff)~ the output voltage VOUt also becomes
smaller than it, so that t~le voltage comparator VC func-
tions to raise the output voltage VOUt. This
feedbacX control, however7 is limited ~inen ~le cu~2ut
voltage V0ut ha.s become equ~l to the ~nput voltage Vin.
Accoruingly, with the infle~ion point (P) at Vin
= Vref2 + ~Vo~f, the output volta~e VOUt is reduced
-- 80 --
., . _ ~.

(limited~ to Vref2 + ~Voff (curve bl)
volta~e Vln is higher than the infléxion point P, and
it is made substantially equal to the input voltage Yi~
(curve a2) when Vi~ is lower than the inflexion point.
If the inflexion point P is the same as or higher
than the lowest operating voltage Vl (point Q) ~rith
respect to the input voltage Vin (on the abscissa),
the foregoLr.~ loss can be avoided.
This is because the curve bl has a point of ~-~tersec-
tion w~th the straight llne al owing to ~Voff~
when the operational amplifier does not have the offset
volta~e ~tJoff and where there is no point of ~ntersection
with the strai~ht line al as in the cur~-e ~, such æ~ . -
effect is not achieved.
Although a MOS FET TC in Figure ~5(a) functions as
a source follower~ it is a depletion mode N-channel FET,
so that it makes VOut a Vln possible when Vin ~ V
Joff and that its threshold vol~age Vth has no loss~
Accordingly, this is e~fectlve whe~ the input ~oltage
Vin is small.
This, however, does not deny the usc of a source
~ollower FET of ~he enhancement mode~ The enhancement
mode FET is V~J effectiYe when the input voltage
is gre~t and the Vth loss is not a serious proble~ and
when the adoption of a depletion mode FET manufacturing
process is difficult. In ~is case, curve a2 ~VOut -
Vin) ~Ihlch deter31nes lower output vol~ages VoUt ~ below
the changing point P) merely shif~s downwards by V~h
(Vout = Vin - V~h~ ~ and it is similarly possible to bring
~0 for~h the e~fect as previously stated on the output
- 81 -
.
.. . . .
,

9~
volta~e V t
In the figure, the N-channel Fr~T can be replaced
~ith a P-cnannel FET In this case, ~he P-channel FET
functions Yi~h the source grounded, and the loss of Vth
above described is not involved.
~ lhe~her the source groundin~ or the source lollower
is adopted as the controlling FET does not produce an
essential difference. However~ in case of the source
gro~ding, no special consideration for the loss of
the threshold voltage Vth, as is required for the depletion
mode FET, is necessary. In case of the source follower,
when the operation of the voltage comparison r.eeds to
be cyclicall~r sampled (for example, wnen the co~parator
is subjected to the clock drive in order to render the
power dissipation low), this FET is convenient as it
function~ as a voltage follower. This is because the
output voltage is determined by the gate voltage if the mu-
tual conductance gm of the FET is suf~iciently high.
It is also possible to use a bipolar transistor
as the controlling transistor.
It is not necessarily denied that the offset QVoff
becomes a ~unction of the lnput voltage Vin~ In setting
the in~lexion point P, however, it is desirable tha~
~Vo~f is constant with respec~ to Vi~
If a re~erence voltage which has a fluctuating
factor similar to that of the load L is used as the
re~erence volta~e Vre~2, output ~oltages V0ut correspond-
ing to t~e characteristic of ~he load L c~n be oDtained,
which is also convenient. If 7 ln that case, Vref2 is
set a~ the lowest voltage at which the load L can operate
- 82 -
,, .~ .
t~
.
,

9 ~E~
in advance, ~VO~ can be exploited as means of a certain
~argin.
',~hile a construction for bestowing the offset ~Voff
and a~ appllcation circuit exploit the difference of the
threshold volta~es of two MOS FETs according to the
princlple of this invention to be described later, another
method ~or endo~ ng the output voltage VOUt with the
inflexion poin~ will be explained here with reference to
the circuit diagram of Figure 36(a) and the graph of
Figure 36(b).
In the following descriptlon and the graph of
~ e 36(b), all the voltage values shall be absolute
values.
In Fi~re 36(a~, Q107 designates a controlling
transistor which is made o~ an I~J-channel depletion mode
FET- N-channel FETs Qlol and Q102' and P-channel FETs
Q104 and Q106 construct current mirror circuitsO A drain
current approxlmately equal to the dra;n current of Q103
flows ~hrou&h a diode-connected P-channel FET Q104
and a diode-connected N-channel FET Q105- The source
drain voltaOe drops VD~ of the diode-connected P-channel
F~T Q104 and N cha~nel F~T Q105 become appro~i~ately
equal to respective threshold ~ol~ages Vthp and Vthn owi~g
to the hlgh impedance loads Q102 and Q106- Acc ~ y~
~p (Vout ~thn) are reSp~ctivel~ applied
,_ to the non-inver~ing input (+) ~d the invertLng input
(-) of an operation~ plifier VC constructing a volta~e
comparator ~cur~es d and D in rigure ~6(b)).
Supposing a case where the operational amplifier VC
has no offsel, it balances when bo~h the ~np~ts of the
- 83 -
, ~
, , .~
~ ' t
:~ ~
,

non-inverting input (+) 2nd the inverting input (-) are
equal. Accord~lgly, the equilibrium condition is (VOut -
V ) - Vt~ , t~ t is, VOut = Vthp + Vthn
voltage VOut is limited to (Vthp + Vt~n) when Vin 2 vthp +
Vthn, and it becomes substantially equal to Vin when
Vin ~ Vthp + Vthn. Accordingly, in~case where the load L
is constructed of a complementary MOS integrated circuit
(~IOSTC), the operating lower-limlt voltage of the ~OS
circuit usually becomes (Vthp + Vthn) an
volta~e VOut can compensate for it.
Although J~he threshold voltage to be derived by
the dlode-connected ~IOS Ql04 and Ql05 i
inherent threshold voltage, it is not equal thereto and
follows up the drain current o~ the circuit. Of course,
it is favorable to make the output ~oltage VOUt of ~he
equilibrium point somewhat greater than the inherent
(Vthp ~ Vthn). To that end, the mutual conductance of the
FET Q103 may be made small in adv~Lnce so as to reduce
the current to flow through each MOS diode Ql04 or
Q105
The approxlmate threshold voltage to be derived
by the MOS diode premises the ~low of the drain current.
- m erefore, the clrcu~t must be con3tructed so t~t the
currents may flow through both the dlodes even wherl the
lnput voltage Yin becomes low.
The reference voltage generator device according to
this ~nvention can genera-te the ~ifference voltage of
the threshold voltages of ~OS as ~he reference voltage,
and can therefore be constructed of ~IISFETs. Accordi~gly,
3~ lt can be extensively utilized as v~rious constant-voltage
- 84 -

~ ~9 ~L
sources in monolithic integrated circuits for an
electronic desk top calculator, an electronic timepiece
etc. made up of ~ISFETs. As illustrated by way of exam-
ple in Figure 37, a lifetime detector circuit for a
battery can be obtained in such a way that the output o~
the reference voltage generator device (N+-gate N-channel
MOS Ql' P+-ga-te ~t-channel MOS Q2' resistor R1) as shown
in the foregoing embodiment is applied to one input of
a voltage comparator circuit (7) as a reference voltage
and that a voltage obtained by dividing a Dattery voltage
(VDD) by means of divider resistors (Rlo, Rll) is applied
to ~he other input.
In this case, since the battery voltage does not
lower suddenly, it is desirable to drive the constant-
voltage generator circuit~ the voltage divider circuitand the voltage comparator circuit with clock pulses,
thereby to achieve the reduction of current consumption.
Likewise, when the constant-voltage output is --
not required at all times, the constant-voltage generator
circult may be clock-driven as stated above.
The circuit for ob ~ ng the difference of the
threshold vol~ages o~ the ~SFETs ~Ql' Q2) ls not
restricted to the constructlon of the above embodiment J
but it can be modifled in various ways and any specific cir-
cuit arrangement may be used.
Figure 3~ shows another embodiment in which thisinven'~on is applled to a battery checker.
Q1' Q2' ~ and Qg co~stitute a constant current
3' 5' ~ Q6 and Q7 constitute a di~ferential
circuit. Qll and Qlo serve for the clock drive to the
- 85 -
. ~
, , . ............................................................ ...
l . , , , ~.

end of the reduction of power dissipation.
~ 1 ar.d R2 constitute a battery voltage divider
circuit for setting the detection level of a batter~
voltage. Gl and G2 func~ion to latch an output owing to
Q8 and Qg.
Q4 and Q6 are an N+-gate P-cha~nel ~IOS ~nd a P+-ga~e
N-channel MOS, respectively, By ~he ion implantation o~
equal quantities, Q6 is adapted to o~erate in the deple-
tion mode.
The embodiment shown in Figure 38 is the battery
chec~er for a timepiece. When the detection
level is set between 1.3 V and 1.5 ~, a current flowing
through ~7 has a ~osi~i~e gradient for t~le temperature,
ar.d the difference (= band gap voltage 3 1.1 V) of the
threshold voltages of Q4 and a6 has a negative gradient
for the temperature. Therefore, the dimensional ratio
of ~he ~OSFETs is set so that the conductance of Q~ may
become smaller than t~e conductance of Q4,
Figure 39 shows a hi~h-precision reference voltage
generator circuit of the voltage follower type u~ilizi~g
an operational ampl~fier. N-channel MOS FETs of the
~+-gate and N+-gate are used for ~4 and Q5, respectively.
Further, the conductances of the FETs are maae different
to pro~uce an offset voltage~ By adJusting a resistor
~1 outslde an IC, a constant current to flow ~hraugh a
constant-current source ~6 is adjusted, thereby to adjust
the offset ~olta~e, Thus, the f~ne ad~ustment o~ a
re~erence vo}tage is made possible.
Or. the other nand, as a Schmitt trigger clrcuit
composed oi ~SFETs, a circuit as shown in Figure 40(~)
- 86 -
. ~_~
,
~- ~ 3
~,,, ~ . . .

which has reduced the number of constituent elements has
been proposed by one of the inventors.
The circuit shown in Figure 40(a) is such that two
inverters are connected in cascade and that a MISFET
(T3) forming a positive feedback circuit is disposed
between the input and output of the inverter on the output
side. With this circuit, the width of a hysteresis curve
(the difference of two logic threshold values VTLl and
VTL2) deviates on account of deviations in a supply
voltage (VDD), the threshold voltages (Vth) of
MISFETS, etc. Therefore, when the circuit is applied to
an oscillator whose output oscillates within the voltage
width~ the frequency deviates disadvantageously.
This invention employs MISFETs formed by a method
wherein the threshold voltage of one (T2) of MISFETs
constituting the first-stage inverter in Figure 40(a) is
made higher than that of the other MISFET having the same
conductivity type channel by a voltage component based on
the difference of Fermi levels. In this way, it is
intended that the width of the hysteresis curve of the
Schmitt trigger circuit (the difference of two logic
threshold voltages) assumes a fixed voltage (a voltage
substantially equal to the Fermi level difference)
fluctuating little against the supply voltage, the manu-
facturing deviations of the MISFETs, temperature changes,
etc.
In the following, this invention will be described
.
- 87 -
. .,

~ ~f~ ~ 8~
in connection with a preferred embo~iment. Refe~ring to Figure
40(a), the ~chmitt trigger circuit ls const~ucted Or an
in~~erter l to which an input signal (Vi) is applied, an
inverter 2 which receives an output of the inverter
5 l as its input and which forms an output signal (V~)
- and a MI~FET (13) which is interposed betw~en an input
terminal and a ground terminal of the inverter 2 and which
is controlled by the output si~nal (V0).
~he ~TSF~T (T3~ acts as positive feedback means
o. the output side inverter 2. The operation of positively
feedin~ the input signal of the inverter 2 to the
out~ut signal thereof is inseparable from the operation
of the inverter l forming the input signal. The circuit
operation is more easily understood when explained in
i5 relation with the input side inverter l, as in the
following.
When the input signal (Vi) iq at a high le~rel (~round
level), the output of the input side inverter l becomes
a low le~el (-V~D) because the N-channel MI~FET (Tl)
is "on" and ~he P-channel MISFET (T2) is "off". m e
~ N-channel ~IISF~T (T4) of the output side inverter 2
receiving this output of the input side inveF~er l
turns "off" and the P-channel MISFET (T5) tur~s "on",
so t~at the output of the output side inverter 2 becomes
z5 the high level (ground level). For this reason, the
P-cnannel MI~F2T (T3) falls into the "off" sta!e.
l~hen, lL~der this condition, the i.~2ut si~nal (V
intends to change to the low level, the output of ~he
~nverter l forms an output signal which is dependent
upon the le~el of the input s1gnal ~Vi~ and ~hlch ~s deter
- 88 -
r~
. : .
,
.

mined by the i~pedarlce ratio of the i~ISF Ts ~T1, T2),
because the MISF~T T3 is "off". T'ne input level of the
output ~ide inverter 2 is changed from the low level to
the high le~el.
Accordingl~, when the outpu~ of the ou-tput side inver-
ter 2 is changed from the high level to the low level
and thls ou~put signal ('~0) has exceeded the threshold
voltage of the ~IISFET (T3), ~le MISFET (T3) starts the
"on" operation. Owing to the "on" operat.on of the
MlSFET (T3), the output level of the input side inverter
1 is decided by the impedance ratio between the MISFET
(Tl) and tqe parallel ~IISF~Ts (T2, ~3), and it lS shifted
onto a higher level side. In other words, upon the
"on" operation of the MISF~T (T3) which is controlled
by the output of the output side inverter 2, the posi-
ti~e feedback in which the input level of the output side
in~rerter 2 is changed into the high level slde is
applied to the input of the output side inverter 2.
Then, the output signal (VO) changes abruptly. Accord-
ingly, the loglc threshold value tV~LZ) ln Figure 40(b)
is determined by the threshold voltages Vthl ~d Vth2 and
mutual conductances ~1 and ~2 of the MISFETs (Tl~ T2)
in Figure 40(a). Tha~ is,
25V ~ Vth2
VT~2 .............. ......................... .... ~(51)
1+~
On the other hand, when the input siænal (Vi) is
at the lo-~ level, the N-channel MISFET (Tl) of the in~ut
~ 89 -
'~ ,,,~ ' ~ ' ' '
f,,'',~
~ ~.J
i,.

8~
side inverter (l) ls "off" and the P-channel ~ FET (T2)
is "on", the .~J-channel `~ISl~T (T4) of the output side
inverter 2 is "on" in the P-channel MISFET (T5) is "off",
ar~d the P-chr~nnel I~lIS~E~ (T3) is "on" owing to the low
level of the output signal (V0), so that the output signal
of the input side inverter l is determined by the
impedance ratio between the MISFET (Tl) and the parallel
illIsFrlTs (T2, ~3).
Accordlngly, in the course in which the input signal
(Vi) changes from the low level to the high level 9 unless
the input si~nal (Vi) becomes a level higher than the
logic threshold voltage (VTL2) in the preceding op~ratlon,
tne output signal of the input side inverter l does
not change to the low level. However, once this output
(the i~put signal for the outpu-t side inverter 2) has
begun to change towards the low level and to change
the output of the output side inverter 2 onto the
high level side, the impedance of the MISFET (T~) changes
to increase. Therefore, the positive feedback in which
t~e change of the output of the input side inverter l,
namely, the input signal of the output side inverter
2 is promoted is applied, and the output signal (VO)
changes abruptly, Here, when the P-channel ~r~SFFT (T2)
has it3 gate electrode formed of a semiconductor of
Z5 the opposite conductivity type (N-type) to the conductivity
tJpe (P-t-~2e) of the gate of the conventional P-channel
- MISF~T (T3~ or formed of an ~ntrinsic (i-type) se~icon-
ductor, it has a threshold voltage which is .higher tha~
the threshold voltage VTH of the ordinary ~iISF~T (~3) by
a volta2e corresponding to the dif~erence ol Fer~i levels
-- 90 --
, ~'.'' .
. ~"" ..

9~
e.~. to the difference of the intrinsic level and the
Fe~ level, respectlvely.
Accordingl-~, the logic threshold voltage (l~TLl)
in Figure 40(b) ls approxlmately expressed as follow3:
VD~ - Vthl ~ Vth3
VTLl ' ~ ~ ~~ ... (52)
r
1 ~ I
~ 2 ~ ~3 is held by ~akin~ the sizes of the MI~FET (Tl)
and the MISF~T (T2) e~ual~ Therefore, the difference
(VTL2 ~ J,rLl) of the two logic threshold values becomes:
1~ ,~
V~L2 - V~Ll = ~ ( th2 th3) ~(53)
1 + ~
`I ~1
Accordin~ly, the difference (VTL2 ~ VTLl) of the
logic ffi reshold values in Figure 40(b) assumes a fixed
voltage which is proportional to the difference (Vth2 -
Vth3) of the threshold voltages of the MI~FET 2 and the
MIS~-.T 3, that is, the difference of the Fermi levels
of the gate electrode3 of these MISFELs 2 and 30
An example for deriving the voltage correspond~ng
to the difference of the Fermi levels is to utilize
the difference o~ the threshold voltages V~h o ~o
~IOSFETs having semiconduc~or gate electrodes which ha~e
different conductivity ty~es and which are formed on ~-ate
-- 91 -- -
.. . .. _ _
, ~
~,', ,.

~ *~
~nsulating films formed on an identical semiconduc~or
substrate by an identical process ~ereunder, a specific
example will be explalned.
Fi~ure 59 prevlously referred to represents the
conceptual sectional structure of the respective FETs,
and the structure cæn be fabricated by the MOS ~anufacturing
- process illustrated in Figures 73~a) - 73(f). Hereunder,
for the sake of brevity, the MOS transistor whose gate
electrode is made of a P -type semiconductor shall be c~lled
the 11p~ ~ate ~OS"~ and the MOS transistor whose ~ate
electrode is made o~ an N+-type semiconductor shall be
called the 1'N gate MOS".
~ he difference (Vthp~ - V~j+) of the threshold
voltages of the P gate ~10S and the N gate MOS becomes
the difference of the ~ermi potentials of semiconductors
making the gate electrodes as seen from ~uat~on (16).
While the above description has been made by taXing
the P+ channel ~iOS transis tor as an example, ~uite the
same applies to the case of the N -channel Ç~IOS transistor.
Besldes, quite the same applles to the i-type gate PIOS
whose gate electrode is made of an intrlnsic semiconductor.
~ igure 41 shows a Schmitt trigger circult according
to another embodiment of thls invention. The point of
difference from the embodiment of Figure 40~a) i~ that
an input inverter ll includes a P~-gate P-channel
depletion type MOS transistor Tll for a load, a Pl-gate
P-channel ennancement type ~IOS transistor T12 for dri~e
and an N~-gate P-channel enhancement ty~e MOS transistor
T13 for feedback, and that an out~ut in~erter 12 includes
a 2 -gate P-channel depletion type MOS transistor T14 for
-- g2 --
l ~ _ 7'
; ~
,~, ~ '1 ' ,' "' ~' '' ~ ~ .
. i' ,, '
, ~ _

a load and a P~-gate P-channel enhancement type MOS tran3is-
'' tor T15 for drive. It is identical that the difference of
logic threshold values becomes a conslant voltage propor-
tional to the difference of the Fermi levels of the gate
electrodes of the MISFET 12 and MISFET 13.
Now, an oscillator will be described as an exam~le
of application of the Schmitt trigger circuit of this
invention. "
F~gure 42 is a circuit diagram of an oscilla~or
to whi~h the ~chmitt trigger circuit of this invention
is applied. A part enclosed with dotted lines in Figure 42
is the ~chmitt t.igger circuit. An output of the Sc.~mitt
trigger circuit (STC) becomes an input of an ~nverter
3 , an output of which becomes an input of the Schmitt
trigger circuit (STC).
Upon closure of a supply voltage, the level of
a point (d) proceeds towards the le~el (-VDD) gradually.
When it has exceeded the threshold voltage (VTL2) of the
Schmitt trigger circuit ~STC)~ the potential of a point
(f) changes to the ground ~oltage, and the potential of
a point (g) changes to the supply voltages (-VDD). Then
as -~he point (g) is the input of the ~nverter ~3), a
MISFET (T4) tur~s 'lon", and the potential of the point
(d) proceeds towards the ground Yoltage immediately.
When the level of the point (d) has become below the logic
threshold voltage (VTLl) of the Schmitt trigger ci~rcuit
(STC), the potential,of the point (f) changes to the
ground voltage, and the voltage of the point (g) changes
to the supply w ltage ~-VDD). Therefore, the l~ISFET (T4)
of the succeeding in~erter (3) -turns "of~", and the
- 93 -
,
, ~'s ;' t~

~ 8~
level of the polnt (d) is charged according to a time
. constant CR which is determined by a resistor (R~ and a
capacitor (C) connected to the point (d). When the
potential of ~he polnt (d) gradually approaches the
supply voltage (-VDD) and has exceeded the threshold
voltage (VTL2) of the Schmitt trigger circult (STC), the
potential of the point (f) changes to the ground potential,
and ~e potential of the point (g) changes to the supply
Yolta~e (-VDD). Therea~ter, the inversions are similarly
repeated to cause oscillation~ Since the potential of the
point (d) reciprocates between the ~o logic threshold
voltages (VTLl, VTL2~ of the Schmitt trigger circuit (STC),
the oscillation frequency of the oscillator is determined
by the speed at which charges are stored into or discharged
from the capacitor (C) by the resistor (R) or the MISFET
(T4). Assumlng now that the resistance (R) is sufficiently
greater than the impedance of the MISFET (T4), the oscil-
lation frequency of the oscillator circuit i5 determlned
by only R and C, and ~he oscillation of a ~requency which
is stable agalnst fluctuations in the supply voltage~
temperature changes, manufacturing deviatlons, etc.
~ hen ~he resistor (R) is mounted outside the inte-
grated circuit, only one pin su~ices for the integrated
circuit of the os~illator circult, and the stable oscil-
-- 25 lation is realizable under such a conditlon.
The resistor (R) may be any of a di fusion resis~or,
a resistor owing to a MISFET, etc. However, when a
resistor of sufficie~tly small deviatlon is formed i~ an
integrated c~rcuit, the oscillator circuit ca~ be entirel~r
contained thereinO
- 94 -
~ ,~ .
, i~', ; .. ~' `'1
, ~

~4~
Figure 43 is a circuit diagram showing an example
of an oscillator circuit utilizing the Schmitt trigger
circuit (STC) as shown in Figure,41 in which the width
o~ hysteresis is constant according to this invention.
A third inverter 3 is connected to the input of the
Schmitt trigger circuit (STC), a fourth inverter 4
is connected to the output of the Schmitt trigger circuit
(STC), and a resistor ~R) and a coupling capacitor (C)
for determining the oscillation frequency are connected
to the input of the third inverter 3.
Control of Threshold Volta~e
The threshold voltages ~Yth) o~ MOSFETs `being
discrete elements in a MOS integrated circuit form an
important parameter which determines the characteristics
of the LSI. The threshold voltage Vth undergoes a great
deviation due to the manufacturing pr~cess and a great
change depending upon the temperature, and the control
of Vth is a dlfficulty in the manufacture of the MOS LSI.
In this inventlon, as shown by way of example in
Fi~ure 50, a bias voltage VBB is applied to a silicon
substrate of a MOS memory IC to reduce parasitic capaci-
tances. In order to obtain the bias voltage VBB, a
substrate bias generator circuit SBGC i~ employed. Th~
- substrate bias generator circuit SBGC has an arrangement
which is illustrated in ~iO~ure 47.
In this inve~tion, the comparator employing the
dlfference of the work functions o~ the gat~ elecirodes
of MIS FE~s as previously stated is used in the substrate
bias generator circuit SBGC so as to control Vth into a
constant volta~e.
- 95 -
. . .
,' .
,

Vth cbanges in dependence on the substrate bias VBB
and is expressed by the following equation:
Vth ~ VthO ~ ~ (2 0F + IVBB I -- 2 ~)
where VthO denotes Vth when ~he substrate bias voltage
VBB - O V, K denotes the substrate ef~ect constant, and 0F
denotes the Fermi level. Therefore, Vth is con~rollable
by varying the substrate bias VBB. ~ substrate bias
voltage generatlng circuit S3GC shown in Figure 47 has a
Vth sense port-on 471, a comparator 472, an oscil-
lation circuit 473 and a waveform shaping portion 474.
The oscillation circuit portion 473 may be replaced with
another oscillation circuit. The wavelorm shaping por~ion
474 is composed of two MOS diodes Ql and Q2 and a capa-
citor Cl, and it functions to drawing out charges of VBB
to the earth point by a pumping action. Owing to the
pumping action, VBB is drawn towards a negative voltage.
The maximum voltage V~BM o~ ¦VBBI is determined by a point
at which the drawin~-out voltage owing to -~he pumpl~g act-
ion and the substrate leakage current are stabllized.
As long as the oscillation circult is opera~ing, V~B is
held at the stable point VBBM. After stop of the oscil-
lation, however~ the charges of the substrate lea~s due to
~-- the substrate leakage current and VBB approaches the
ground level~ ~en YBB has become close to the ground
level, Vth lowers.
The comparator portion 472 in Figure 47 exploits
the difference of the Fermi levels of the gate electrodes,
and an example in the ~-ch~nnel process is show~ in
Flg~re 21 The comparator portion 472 employs an
intrinsic silicon gate MOS as ~ in ~1gure 21, and an N
- 96 -
F
- ,
. .

~f~ 9V8~
gate MOS as Q2. These are depletion type ~OS. Therefore,
this comparator ef~ects the inversion when a voltage of
= 0.55 V has been put into an inv~rting ir.put (-)
The Yth sense portion 471 in Figure 47 is composed of a
resistance and a diode-connected ~iOSFET Q~. Here, ~he
resistance may be either a polycrystalline silicon diffused
layer resistance or a MOS resis-tance, and the resistance
v~lue i~ set so that an output may become 0.55 V when
~th of Q3 has become 0~55 V. Now, when the substrat2 bias 'O voltage VBB is close to the ground level and Vth of Q3 is
below 0.55 V, the (-~ input voltage of the co~parator
portion becomes below O.55 V, the output of the comparator
becomes 'tl" ard the oscillation circuit continues to
operate. ~lhen the substrate bias voltage VB3 approaches
V3B~ and Vth rises and exceeds 0.55 V, the comparator
output becomes "O", the oscillation ceases and the substrate
blas voltage VBB becomes close to the ground level due to
the leakage. That is, since a feedback loop is formed9
Vth is controlled to the stable point by this substrate
b~as generator circuit SBGC. The voltage 0.55 V obtained
in the comparator portion 472 is l/2 of the energy gap,
~ which changes little agalnst temperature change~ 9 manufac-
- turing disperslons and supply voltage fluctuations.
Therefore, it becomes possible to control Vth at a very
high prec~sion, and a MOSLSI ~hich is wide in the te.~exa-
ture margin, the manufacturing process margin and the
power supply ~argin is ob~ai~ed. As will be stated later,
also in poi~t o~ the process~ the intrinsic silicon gate
MOS G1 of ~he comparator portion 472 can be obtained.
by quite an identical process to that for obtaining a
- 97 -
. ~ , , _ .
"
~ ~ .
~ ,, ~ ,: '',, .

8~
high resistance load ~ in a memory cell shown in Figure
51, so that the control of V, h can be readily realized
wi~h the prior-art process.
Level Shift Circuit
, _ _
In case where a 5 V power supply is employed as
a power source in a MOSLSI and w~ere signals from a TTL
logic circuit are employed as inputs, the outputs of the
'l~L logic circuit become 2.0 V as a high level and 0~8 V
as a low level. In converting the TTL signals into the MOS
levels, it has heretofore been carried out to take the ratios
of inverters in an input portion and to convert them into
the MOS levels. However, there has been ~he problem
that the input level margin becomes s~all on acco~n~ of
the dispersion of Vth and temperature changes.
Figure 45 shows a TTL-~ MOS signal level converter
circuit whlch employs the reference voltage Vref generated
from the reference voltage generator ci.cuit utllizing
the difference of the Fermi levels of the gate electrodes
as pre~iously describedO The signal level converter
circuit in Figure 45 is preferably applied to the address
- buffer clrcult~ XAB and YAB of th2 MOS memory ~hown in
Figure 50. A3 the reference w ltage Vref, the reference
voltage o~ 1.4 V is generated by the foregoing reference
voltage generator circult o~ Figure 15~ A dit^ferential
ampllfier employing MOSFETs in Figure 44 is employed as
an amplifier t~) in Figure 45, and an input buffer in
which the logic threshold voltage o~ an input is 1.4 V
equAl to '~he reference voltage Vr~f is prepared. With
the present method, the TTL-~ MOS ~ignal level con~erter
circuit is obtained.
- 98 -
. ~ ~
: ~ J `', ~

9~
Alternatively, a slO~nal level converter circui~
which has the logic threshold vol~a~e of 1.4 ~r can be
obtained by e~ploying the circuit shown in Fi~ure 13 a3
the a~plifier (~) in FiOFure 45. The inphase input (+)
~ is grounded as sho~m in Figure 14, and an address
signal Ao - A4 is applled to ~he antiphase input (-).
As the transistors Tl and T2, depletion type ~IOS FETs
are used. By making the threshold voltages Vt~l and
V~h2 of the respective FETs unequal, ~e operational
a~plifier is endowed with an input offset voltage of 1.4 V.
A circuit ln Figure 46 intends to al~ays hold the
logic threshold voltages of logical circuits such as
in~erter constant against changes in the service supply
voltage, the threshold voltages of ~IOS transistors, tem-
peratures, etc.
i~n inverter 1 composed of Q2 and Q3 and an inverter
2 composed of ~5 and Q6 are especially provided with ~IOS
rE~s Ql and Q4 for controlling logic thresholds, respec-
tively.
' A logic threshold detector circuit 3 which is composedof a controlling MOSFET Q7 and an inverter (G8, Qg) with
its input and output coupled is constructed so as to be
similar to the inverters 1 and Z stated above ~the
pattern slze ratios oî MOSFETs are equal). ~ing to the
coupling of the input and output of ~he inverter (Q8' Q9)'
~ust the loglc threshold voltage is obtained.
Ckæl indica-te~ the comparator circuit prevlously
stated with reference to Figuresl3 and 14 which has the
reference voltage Vref as the off~et of the differential
_ 99 _
. ~-

9~81
circuit. The comparator circuit C~Pl compares the logic
threshold and the reference ~oltage possessed therein,
and controls the gate voltage of the controlling MOSF~T
Q7 so that the di~erence of both the voltages may become
substantially O (zero).
More specifically, if the logic threshold > the
reference voltage (Vref), the output of CMPl becomes a
high level, ~ld the equivalent resistance of Q7 lncreases
and this transistor functions in the direction of lowerirg
the logic threshold. In case where the lo~ic threshold
< the reference voltage ~Vref), the converse is true.
BotA the voltages fall lnto the equilibrium state when
they are equal.
The gate voltages of the controlling MOSFETs Ql and
Q4 are common with the gate voltage of the controlling
MOSFET ~ , and the former transistors and the latter
transistor are in the s$milar relatiQnship. Thus, the
logic t.~resholds of the inverters 1 and 2 become equal to
the reference vol~age, and very stable inverter charac-
teristics are exhlbited.
As stated at ~he beginning, this is not restrictedonly to the inverters9 but is similarly applic~ble to the
other logical circuits such as NAMD and NOR.
Thls is readlly applicable to the case of inverters
and the like logical circuits of o ~ y single channel
- types, not the CMOS construction.
These circults are useful as input ln~erface circuits
which can dlgitally process slgnals reliably especially
when ~he ranges of input leYels and logic amplitudes are
narrow.
.' .
- l o o
_ ~
., ~ ' .
.

There will now be ex~tlained specific examples in
~ich ~.e reference voltage ~enerator means accord~ng to
this invention is applled to a s~atus setting circuit
(an auto-clear circuit) for electronic devices.
Figure 4~ is a circuit diagram showing an e ~ tle
of a status setting circuit, whlch is a flip-flop circuit
constructed of two inverters each including two MOSFETs.
.~eferring to the figure, in case where potentials at points
a and b are O (zero), both the MOSFETs Tl and T3 falls into
the "ON" state upon closure of a power supply (-VDD)
becau~e they &re N-channel ~OSFETs. Simultaneously with
the closure of ~he supply voltage, ~he points a and b
change tow&~ds the supply voltage t-YDD). At this time~
the Fermi levels of the gate semiconductors of the
~I-cha~nel ~IOSF~Ts Tl and T3 differ from each other, and
the threshold voltage Vth3 o~ the MOSFET T3 is about three
times greater than that Vthl of the ~IO~FET Tl (example:
Vthl = O.45 V, Vth3 ~ 1.25 V). merefore, in the course
of the fall of the supply voltage, the MOSFET T3 turns
"OFF" previously. Slnce~the MOSFET Tl continues to be in
the 'lOri" state, the points b and a are respectively stabi-
llzed at -VDD and the ground potential.
In case where, with the power supply (-VD~) disconnec-
ted, the point a is at O V a~d charges remain at about 1 V
at the point b, T3 is i~ the "oFF'' s~ate tlll VDD s Vth3
ln the course of the fall of the supply voltage, and the
MOSFE~ Tl falls into the "ON" state at V~D - Vthl.
Therefore, e~en when tne point a has been O V and the
point b has been about 1 V (or up to YthN of T3) in the
in$tial state, the point b becomes VDD and the point a
- 101 -
r~
,
,

becomes O V in the stable state. Further, since all the
FETs are constructed of E(enhancement)-MOSF~Ts in tne
present circ it, the current consumption in the stable
state is almost zero.
Figure 49 is a circuit diagram which shows an example
of a status setting circuit having heretofore been
proposed. Referring to the fi~lre, the threshold voltage
Vth o~ ~IOSFETs T2 and T4 are equal to each other, and
an ~-cha~nel D (depletion)-MOSFET Tl is inserted in order
to increase the stability of a latch circuit. Owing to
~he D ilOSF~T, upon closure of the power supply (-VDD~
the point a falls simultaneously with the power supply
without fail, and the point b does not turn "ON" unless the
supply voltage falls to Vth of the MOSrET T4, so that the
point a and the point b become -VDD and O V in the stable
state respectively. Since, however, the L~;OSFET is
inserted between the point a and -VDD in the present cir-
cuit, the P-MO~F~T T3 turns "ON" when the state in whicn
tne point b is -YDD and the point a 15 0 V (RE~T) is sub-
sequently established from some reason, and a D.C. path
due to Tl and T3 arises to result i-n a high curre~t
consumptlon. In contrastl wlth ~he status setting circult
of this invention as shown in Figure 48, the status
setting can be reliably done and the current con~umption
2~- is Yery low as described above9 and hence, e~fective
status setting means can be provided.
Now, æn embodiment in which this invention is applied
to a semiconductor random access mamory (R~l) wlll be
described.
In general, in a storage de~ice constructed of
- 102 -
~ - .
, 1~,,' , .. .
~ 1~` , .... . .

~ 90~
a static Pl~, the volta~e control of lo~ering a supply
voltage is carried out in order to reduce power dissipa-
tion at the time when the stora~e device is not used
(stand-b~f status)~ This is called the data rete~tion mode.
In this case, a signal voltage is lowered simultane-
ously ~ith the supply voltage. In this regard, since a
power suppl~ line has a greater time constant than a
signal llne, the signal voltage lowers to a predetermined
value faster. Usually~ in a semiconductor RAM, a read
control slgnal is set at a supply voltage level, a ~rite
control signal at a reference voltage level, and a ohip
select signal at a reference potential le~el.
In the data retention mode, therefore 7 the level of
the con~rol signal lowers faster than the supply voltage,
1~ so that the read control signal becomes the write control
signal level instantaneously and that the chip select
signal is formed For this reason~ the write operation
is effected ins~antaneously, and the i~formation of a
bit selected at ~hat time is destroyed.
In order to solve this problem, in a RAM constructed
of field-effect translstors of a single channel~ it is
considered to dispose a tlme constant circuit for making
the time constant of the signal llne greater. 'J~th thls
measure~ howe~er, an external circuit is required, and the
control signals are adversely affected.
In a C-MOS (complementary MOS) integrated circuit,
a p-r-p-n element i3 prone to be formed on acco~t of the
structure thereof~ Therefore, ~rhen the sig~ oltage
is made ~igher than the supply ~oltage, such a p-n-p-n
element operates, and a great current flows between
- 103 -
, ~ ,~ .. _ _ _
. ~ \.
' --~, 1''; `~'
" ,,.

908~
the supply voltage ~d the reference potential. ~or
this reason, a time constant circuit with ~Jhich the
signal vol~a~e and the supply volta~e lo~Jer at ~he ~ame
time ~ust be selected ~or the C-MOS memory.
These facts are serious problems i~ the des~gn and
~anufacture of s~orage devices on the side of the user o~
memory chips.
In this regard, it is ds3irable that a circuit for
sensing the lowering of the supply voltage is contained
in the sa~e chip as that o the R~l. However, I~IOSF3Ts
on the sem~conduclor ch~p have the temperature dependency
of threshold voltages Ytn, manu~acturing de~iatio~s, etc.,
and it has been dif ~cult to obtain a detection voltage
- necessary for the sensing at high precision.
Hereunder, this inventlon will be concretely described
~long an embodiment.
Flgure 52 is a bloc~ dlagram of a static type semi-
conductor memory integrated circuit device showing an
embodiment of this invention.
In tne fisure, 1 designates a memory matrix (64 x
- 64 bits) circuit which is constructed of static memory
cells.
2 designates an X-decoder circuit. It discerns
an informatlon pattern assigned by a row select signal
(Ao - A4) and applied through a buffer circuit B.~, to
assign a row-(~) line of I/64.
3 indicates a Y-decoder and input/output circuit.
~h~ circuit 3 discerns an information pattern assigned
by a column select signal (~5 - ~ ) and applied ~hroug~
a buffer circuit ~Y~ to assign a column (Y) lin~ of 1~64.
- 104 -
r ~ ' , ~ . '
~' ' ' , ' .~ '
. _

It al~o gives the assi~ed column line of the memory matrix
an inpu-t data applied through gates '~3. It also provides
an outpu~ data from the assigned colu~n line to ter~ nals
(1/01 - 1/04) through gates RB.
4 indicates an input data control circuit, which
gives the input/output circuit the input data to-be-
written. (1/01 - 1/04) indicate input/output t~rminals.
(C~) denotes a chip select signal, which indicates the
selection of this chip by the "0" level i.e. reference
1~ potentlal leYel.
(~) denotes a ~rite/read control signal. It si~nifies
the write operation when it is at t~e "0" level i.e, the
reference potential level, while it signifles the read
operation ~rhen it is at ~he "1" level i,e. suppl~ voltage
level.
5,6 designate gate circuits which are alternately
controlled by the control signals.
That is, only when (~) is "0", the gate circuits,
are controlled by either "0" or "1" of (~E)g to execute
the write or read operatlon.
7 designates a voltage detector circult. It
detects the data retentlon mode on the basis of the fact
that the supply voltage has beco~e below a predetermined
voltage, and it controls the gate circuit 5 so as to
inhibit the (W~) at that time. Thus, the malfunction
as preYiousl~ described, is prevented. An example of
the concrete arrangement o~ the voltage detector cir~uit
7 is shown in Figure 53(a).
~ 2esistors (Rl t ~Z~ connected in series constitute
a circuit for dividing a supply voltage (Vcc). The voltage
- 105 -
- . _
, j `~ '' ',.
~ ,~"'''' ' .

div~der circuit applies a divided voltage (a) to the
gate of an ;~i-channel ~IISF~T (Q2). The supply voltage
(Vcc) i~ applied to the gate of an ~i-channel ifI~FET (Q4)o
A ~ISFET (~5) has its gate supplied with a suitable
bias voltage from (d), and constructs a constant-current
source. It constitutes an operational amplifier, together
with load ~IISFETs (Ql) and (Q3) and the two differential
input ~IISF~rs (Q2) an~ (Q4).
The differential i~put MIS~ETs (Q2) and (~4) are
f4rmed on~ for e.cample, rJ type silicon layers of equal
conductivities, and the respective gate electrodes are
made of different materials so that the threshold voltages
may become unequal. ~he gate electrodes of ~he two
~IISFETs (Q2) and (~4) are made of, for e~ample, silicon,
and their conductivity types are made different. The
~IISFET (Q2) has the N-type silicon gate, whereas the
I~SF~T (Q4) has the P-type silicon gate. As a result,
the threshold voltage (Vth4) of the ~IISFET (Q4) becomes
~reater than the threshold voltage (Vth~) of the ~ FET
(~2) by the difference o~ the Fermi levels of the P-type
and ~T-type silicon 2ates.
Accordlngly, ~he operational amplifier has an offset
~oltage equal to the difference of the threshold voltages~
Under ~he state under which the supply voltage ~cc
is comparatively great in ~he sircuit of Figure 53(a),
~he ~SFET (Q4) is in the "on'l state and (Qz) is ~3 the - --
"o~f~' 3tate, ar.~ ~he potential of a point c is at the
low level. Due to uhe lowering of the supply voltage
YCC7 Lhe potential of the po~nt (a) changes as indicated
- 3Q- b~J a cu~e a in Figure 53(b). ~hen, due to the lowering
- 106 -
.~
. ~
, , i

of the supply voltage Vcc, th~ potenti~1 difference
,,
be~reen the suppl~ voltage Vc~ and the potentlal of
the point a has become smaller than the offset voltage,
the MISFET (Q4) falls into the "off" state and (Q2) falls
~nto the "on" state In consequence, the potentials
of the po~nts D and c in the circuit o~ Figure 53(a)
change as indicated by curves b and c in Figure 53(b),
respectively. That is, the potential of the ~oint c
becomes the high level when the supply voltage Vcc has
lowered to a predetermined value.
As described above, the detection level of the
circuit of Fi~ure 53(a) is determined ~y ~he offset
voltage o~ing to the MISFETs (Q2) and (Q4) and the divlded
~oltage owlng to the resistors Rl and R2 I~ is not
1~ affected by the threshold voltages of the respecti~re
MISFETs.
~he offset voltage is at a comparatively high precl
sion becau3e it ls decided by the differ2nce of the Fermi
levels of the gate electrodes of the two MISFETs (Q2)
and (Q4) as stated previously. Since, in a semiconductor
integrated circuit~ the relati~e values of the resistances
of resistor elements are at a comparatively high precision,
the -~oltage division ratio owing ~o the resistors (Rl)
and ~R2) is at a comparatively high precision.
As a result, the detection level o the circuit
of Figure 53(a~ can be set comparatively accurately.
- In Flgure 53(b), a wa~eform (d') indicates the
output of the gate circuit ~5) during the data reten'ion
m~de during which the gate circuit (5) is not con~rolled
by the detectio~ out~ut.
- 107 -
1~
Ç 1``
. ,...

In the data retention mode, ~he input contr~l signals
(~) and (~) lower faster thc~n the supply voltage (VcC)
of the gate circuit ~5). Therefore, when the dlfference
of both the voltages has become above the logic threshold,
the output waveform (d') as stated above is generated.
This forms the cause of the malfunction explained before.
According to the circuit of the present embodiment,
however, the control signal (c) is applied to the input
of the gate circult (5), so tnat the wavefo.m (d') is
inhibited from being provided. Thus, the erroneous write
in the data retention mode can be prevented, and data
stored in the matrix memory are not destroyed.
In accordance with the embodiment set forth above,
the erroneous write in the data retention mode can be
perfectly prevented. Moreover~ the detector circuit can
be constructed with the simple circuit arrangement and
can be contained i~ the memory chip. It is therefore
unnecessary to care for the prevention of malfunctions
on the side of the user of the semiconductor memory device.
For example, the gate circuit which is controlled
by the voltage de-tection output may obtain the ch~p
select signal. All the memory cell select signals may
be inhibited so as to select no memory cell.
Thls is because the erroneous write can be prevented
when one of conditions necessary ~or the execution of the
write operation is inhibited.
The voltage divider circuit which constitutes the
voltage detector circuit in the previous embodiment
may utilize resistance by means of M~FETs ins~ead o.
the resistor elements. ~esirably, the resistance of this
~4~8J
- 108 - ;
~,.__
, ~' '
~.'''" ` ,"
; k~
.

~1~9V~
voltage di~ider circu~t is made a large value In order
to make the power dissipation low.
The tw~ ~'~SFET~ of the foregoing embodiment whicn
have silicon gate electrodes of conductivity types
opposite to each o'~her are fabricated within a silicon
monolitnic semiconductor lntegrated circuit chip. Since
these ~ETs are manufactured under substa~tially the same
conditions except the conductivity ~ypes of the gate
electrodes, the difference of the threshold volta~es Vt~
of both the FETs becomes approximately equal to the dif-
ference of the Fermi levels of P-type silicon and N-type
silicon. The P-t~pe and ~i-type gate electro~es are doped
with respective impurities to the vicinities of the satura-
tion densities, and the difference becomes approximately
equal to the energy gap Eg o~ silicon (about 1.1 V), which
is utilized as a reference ~oltage source.
The reference voltage generator device based on
such a ~onstructio~ is low in the temperature dependency
and small in the manufacturing deviations.
The voltage detector circuit 7 can be modified
variously,
That is, the reference voltage sources which exploit
the difference of the Fermi levels of semiconductors
forming the gate electrodes of two MOS FETs as shown in
Figure 6(b)~ Figur~ 8, Figure 9, Figure lO(a), Figure
- ll(a), Figure 12, ~igure 13, Figure 14, Figure 15, Figure
16 and F~gure 17 are effective as the reference vo,tdge
source i'or the ~Joltage detector circuit of ~his invention.
~o this e~d, there can be employed two FET3 which
have semlconductor gate electrodes of different conductivity
- 109 -
. ~
~3~,, `~~ `
,

svs~
types as already explained wltA reference to Figure 59,
for example3 a MOS transistor with its gate electrode made
of a P+-type semiconductor or a P~-gate ~IOS transistor
and a MOS transistor with its gate electrode made of
an N -type semiconductor or
an ~ -gate ~IOS transistor As already described with
reference to Figures 73(a) to 73(f), the above two FETs
can be manufactured without the change or addition of any
step by the conventional CMOS manufacturing process.
In case of employing the conventional CMOS manufac-
turing process, the self-alignment structure as shown
in Figures 65(a) and 65(b) and Figures 66(a) and 66(b)
is obtained as stated below. ~ince the MOS translstors
are of the P-channel in this case, a P-type impurity is
diffused into both end parts of a gate electrode adjoining
the source and drain in both the P+-gate MOS and the
N+-gate MOS. In a central part of the gate electrode,
a P-type impurity is diffused for the P+-gate MOS, and
an N-~ype in~purity is diffused for the N~-gate MOS.
Between 'he central region and both the end parts ad~oin-
ing the source and drain, regions i in which no impurity
is diffused are disposed. mus, it ls considered that the
difference o~ the P~-gate MOS and the N~-gate MOS is only
the conductivity type ~P or N) of the semiconductor ~orming
the central region of the gate.
- Further, in order to reduce to the utmost the devia-
tion (difference) of the effective cha~el leng~hs of the
MOS t.ansistors a ~tributed to the fact that the regions of
the gates which are ~ormed for the self-ali~nment and in
which the P-~e impurity is diffused shift onto elther
-- 110 -
. ~
, ~
, .
,
.

08~
the leEt or right side (so~rce side or ~rain side) during
manufacture on account of the error of the mask
ali~nment, the columns of the source regions and the drain
regions are alternately arranged, and the left hal~ and
the ri~ht half are put into a line sy~metry with respect
to ~he channel direction as a whole. Accordingly, even
hen the misregistration of the mas~ alignment with
respect to the cha~lel direction (lef~ward or rightward
shifting) changes the effective cnar~el len~ths of the
FETs in the respective columns, the avera~e effective
channel lengths of the P -gate MOS and the N~-gate ~IGS
in ~he respective colum~ns connected in parallel have the
shifting canceled as a whole and become substantially
constant.
~esides by ma~ing the compositions of the gate elec-
trodes different, unequal threshold voltages are realized
by the ion implantation into channels as described with
reference to Figure 7J by utilizing a doped gate oxide,
by chan~ing the thickness of ~ate insulating films, etc.
An example in Flgure 54 is the example in which
the battery checker of the example o Figure 20 is
applied to an electronic tlmepiece.
Tl ~ T2 7 T41 - ~49 and ~41 and R42 constitute a
circuit which checks the voltage level o~ a mercury
battery El having a nominal voltage of 1.5 V. A transistor
pair (Tl, T2) in a differential portion is constructed o~
a P gate ~-channel ~OS Tl and an N g~e N-channel ~IO~
T2, the channel portions o~ which are subjected ~ ion
i~planta~lon so that the threshold voltages of both the
tran~istors may lie within 1 0 IV to 1~5 V beinO the
- 111 --
.

49~18~
operating power supply rango o~ the electronic timepiece.
The diIfer~nce of the threshold voltages to ser~e
as a reference voltage is about 1,1 V in case of a silicon
semlconductor. In order to set at about 1.4 V a level
for detecting that the voltage o~ the battery El has
lowered, an adjustment is made by the resistance ratio
of the resistance means R41 and ~42.
In order to make the curren-t consump~ion negli~ible
in practical use, the battery checker is intermittently
operated by a clock signal ~ which is obtained from a
frequency dlvider circuit FD and a timing circuit ~l.
A~ output of the battery checker is statically
held by a latch which is composed of NAMD gates NA
and i~A2. The timing circuit ~I is controlled by a
logic level of an output from the latch circult, whereby
a driving output of a motor is changed and the method
of moving hand o~ the timepiece is changed so as to
indicate the lowerin~ of the battery voltage~ The lowering
of the battery voltage can also be indicated without chang-
ing the movements of the hand and by, for example, flicker-
in~ an electrooptic device such as a liq~id crystal and
light emittlng diode.
In the figure, OSC indicat~s a crystal oscillator
circuit which is constructed of a ~OS inverter and
which also includes components outside the IC, a crystal
Xtal and capacitances CG and CD. WS indicates a waveform
shapinO circuit which converts ihe oscillat_on output
from a sinusoidal wa~e into a rectan~ular ~ave. Ckl
in~cates an excitation coil of a step motor for driv~ng
the second hand. BFl and 3F2 indicate bu fers which are
- 112 -
.
, ,
, ~

94~831
constructed of CMOS inverters and which serve to drlve
the excitation co~l ~I while inverting the polaritles
every second.
All the circuits within the IC are operated by
the mercury battery ~1 of the nominal 1,5 V. ~l is
the tlming pulse generator circult which reveives a
plurality of frequency division outputs of different
frequencies from the frequency divider circuit .~D and
the con~rol output of the latch composed of MAl and
NA2 and which generates pulses having any desired period
and pulse width. The IC is of a monolithic ai semlconductor
chip for a hand type electronic wrist watch whlch is
fabricated by the Si gate CMOS process alread~J e~lalned
with reference to Figures 73(a) - 73 (f).
Figure 55 shows an example of the co~struction
of a circuit system for an electronic wrist watch con-
taining a battery checker therein. In this example, the
co~ductances of FETs Q4 and Q5 of a differential clrcuit
are made unequal as in Figure 39, and the detection level
can be finely adJusted by means of an adjusting resistor
Rj outside ~he IC.
Owing to the resistor R~, de~iations ln the manu-
facture can be per~ectly avoided in use.
Now, an example in ~hich the voltage regulator as
shown in Figure 36(a) is applied to an electronic tlme-
piece will 'oe explained wlth reference to Fi~ure 56.
In Figure 56, OSC d~signates a crystal oscillator,
'~S a waveform snaping circult whlch converts a sinusoidal
wave oscillation output into a rectan~ular wave, FD a
frequency divider circuit, TM a timing pulse g~nerator
- 113 -
?
, ~"
d ~
~ ~ : ? ?

circuit whicn prepares pulse~ of pre~etermined period
-~ ar.d ,rid-th from frequency ~ivi sion outputs, LF a level
shl~t circuit ~Jhich converts a signal of low level into
a signal of high level, BC a batte-y lifetim2 detector,
VC a voltage comparator, V~ a voltagP re~ul~tor .~ich
uses the voltage comparator VC, H a hold circu~t, DT
an oscillation state detector, and ~`~ an excitation coil
of a step motor for driving a second hand.
The detector DT detects it -through the I~ equency
divider FD and the timing circui-t ~ that the oscillator
OSC has oscillated. In case of the oscillatio~, it
actuates the voltage regulator V~ to drop the operating
voltaOe VOp of the oscillator OSC as well as IYS, FD, I~l
etc. into a ~alue below the ~attery voltage (-1 5 V).
rhe moment a battery E is turned "on", the input
node of an inverter I7 becomes ~he earth potential
(logic "O") owing to e discharsin~ resistor R104, so
that an N channel FET Q201 is brought i~to the "0~"
state and that the output of the regulator is made
-1.5 V being the battery voltage. At this time, a FET
Q203 is also turned "ON", and the gate node of a FET Q202
is charged. This is to the end of previously making the
negative feedback loop of the regulator active lest
the regulator output should drop the momen-t the FET Q~
is subsequentl~ switched "OFF".
Whe~. the oscillator has startPd operating~ the
other logical circuits are alread~ in the oper~tive
state, so that a pulse ~B is supplied from the timinOs
circuit ~fi to the detector DT~ ~`~ exclusiYe OR c~rcuit
~;~1 d~-tects the ~ssue of the pulse PB. One input thereof
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83L
receives the pulse ~B delayed by inverters I4 and I5
and an integration circuit C10l and Rlo~ wiln respect
to the other. Upon the issue of the pulse ~B' ccord-
ingly, a pulse of a width corresponding to the delay time
is pro~ided at ~he output of the gate ~,Cl. This pulse
is integrated by a rectifier circuit made up of à FrT
a225, an inver~er I6 and a capacitor C102, and turns
"OFF" the N-c~annel FETs Q201 and ~20~ P P
a short time from the begi~ning of the issue of ~B.
Thus, the regulator VR gen~rates a predetermined voltage
(less than 1.5 V) at the source electrode of the con-
trolling P-channel ~ET Q202 by !~e negative feedback control
loop, ~nd it contributes to reduce the po~er dissipation
of the electronic timepiece.
Hereunder, the operation of the regulator, especially
the voltage comparator VC will be explained. ~ince this
comparator VC effects an operation similar to that of the
comparator CP described with reference to the principle
dia~ram of Fi~ure 35(a) and the characteristic diagram
of Figure 35(b), only a brief explanation will be given~
Pegarding P-channel ~IOSF3Ts Q206 and Q2~7' in order
~o obtain the offset voltage VO~, the gate of Q206 is
made ~he ~-type as in Ql of Figure 60 and Figures 67~a)
and 67(b), and the gate of Q207 is made ~he i-type
(l~trinsic semiconductor) as in Q2 of FlOGure 60 and Figures
68(a) and $8(b). Accordingly, ~he threshold voltage Vth
f Q207 ~ecomes hi6her than ~at o~ Q b t O
w~ich serves as the aforeclted offset ~oltage Vof~.
On the other handr since both an N-channel FET Q208 ~nd
~0 a P-chzrnel FET Q209 are diode-connected, the sum of
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;-, ' ' .
~,' .1'
.
,

both the threshold voltages Yth i.e. (Vthp + Ythn
is applied to the gate of Q207 being the non-inverting
input (+) of the comparator VC, and`the sum serves as the
voltage Vref2 as indicated in the curve d in Figure 35(b).
On the other hand, the gate of the FET Q~06 being the
inverting input (-) of the comparator is connected to the
source of the controlling P-channel FET Q202 of the source
follower type.
Accordingly, the output voltage VOUt of the voltage
regulator YR which is generated at the source of the con-
trolling FET Q202 under the control action of this control-
ling FET Q202 driven by the comparator VC becomes VOUt =
thp209 Vthn208 + ~Voff (in case where Vin 2 Vth
Vthn ~ ~Voff) I~en the input Yoltage Vin is low, the
outpu-t voltage becomes VOut - Vin as in the foregoing.
Of course, the output voltage VOUt of the voltage regu-
lator VR ls utilized as the operating voltage VOp of the
oscillator OSC as well as WS, FD, TM, etc.
In order to render the power dissipation low, thls
comparator has the operating time limited by a timlng
slgnal ~A owing to the on-off operation of the driven FET
Q211- f course~ the s~me applies to the circuit for
obtaining the reference voltage Vre~2. To this end, a
aapacitor C104 is connected to the gate of Q207 and a
capacitance C105 is connected to the gate f Q202 50 as to
hold the voltage of the reference voltage~rref2 and to
hold Jhe gate voltage ~ Q202~ respectively. These capaci-
ta~ces C104 and C105 are added sep&~ately from para~itic
capacitances such as gate capacitances. A capacitor C
~0 serves to prevent any oscillation whlch is attributed to
r
~, , .. ~ .
.
.

81
a phase rotation caused by the cascade connection of sev-
eral ~ETs ln the ~eedback loop.
S~nce the battery checker BC has a construc~ion
similar to that in Figure 54, t~e explanation is omitted.
At the output stage of the IC, drivers I2 and I3
for the excitation coil directly use the battery of 1.5
V as -~he power supply in order to make the driving
capabillty high.
Figure 57 shows an example in which the voltage
regulator VR and the battery checker BC accordLng to
this invention are applied to a digital display electronic
timepiece.
In the flgure, parts OSC, ItJS and FD u~e an ad~usted
voltage lo~rer ~han 1.5 V as a power supply as in the
example of Figure 56, and also logical circuits within an
IC such as decoder DC and time correction circuit TC
use~ the lower voltage as a power supply.
DB designates a voltage doubler circuit which boost~
the voltage of 1~5 Y to 3~0 V, whlch is used as a drive
voltage for a liquid crystal display DP (a driver is not
shown~. Each of LSl and LS2 lndicates a level shif~
circuit, which co~Yerts a low slgnal level into a hlgh
one D.C.-w~se and supplies lt to circuits of h~gh supply
voltages.
It ls ef~ective for rendering the power dissipation
low and the expansion of a service power supply range
that, as thus far described, the low operat~ng power
supply ls used for the ordinary logical circuits with~n
the IC which operate at low operating ~oltages, while
the hi2h operat~ng power supply is used for the display
- 117 -
. ~
1- , , . ., .~
I' .. ..

g~
driver etc. at the input/output interface of the IC
which requlre high operating voltages.
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~, r ~
1~ ` ` ~;`
. . i