Note: Descriptions are shown in the official language in which they were submitted.
94~8
LOW VOLTAGE CURRENT MIRROR
Background of the Invention
This invention relates to the field of current mirror
circuits and, more particularly, to the provision of an
accurate current mirror operating on a minimum supply
voltage.
Current mirrors are well known in the art as a means
for supplying a known current as, for example, in biasing
transistor gain stages. While a "current source" may be as
simple as a resistor, current mirrors have become increas-
ingly used for several reasons. First, they offer improved
circuit performance and more accurate current control than
do resistors, and may also require less area on an
integrated circuit chip. The most conventional and simple
circuit for a current mirror requires high beta transistors,
or at least transistors having consistent values of beta, in
order to approach the desired correlation between output and
reference current. In IC processing, this is, of course,
difficult and thus expensive as beta values tend to have a
wide range of values and restriction of the usable range of
values makes for a low IC production yield.
More complicated current mirror circuits have been
devised which are less sensitive to beta variations. one
such is known as the Wilson current mirror which decreases
the sensitivity to beta value by means of an additional
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buffer transistor which supplies the base current for the
~irror circuit transistors without significantly disturbing
the reference current. In such a circuit, however, a high
supply voltage is required, due to the series-connected
emitter-base juntions. This.limitation precludes the use of
such a circuit in many of today's miniature electronic
devices such as hearing aides, pagers, etc.
Summary of the Invention
It is therefore an object of the present invention to
provide a highly accurate current mirror circuit for use
with low voltage supplies.
It is a particular object to provide such a circuit
which is highly independent of the beta values in an inte-
grated circuit application.
These objects and others which will become apparent are
provided in a current mirror circuit wherein the two matched
transistor devices are biased by an automatically controlled
biasing network. A sensing circuit compares the current in
one of the transistors with the reference current and
adjusts the biasing voltage, forcing the collector current
of that transistor to be equal to the reference current. In
this mirror circuit, there are no bias paths containing more
than one diode drop, thus the circuit can operate with
supply voltages ranging down to l.0 volts.
More particularly, there is provided:
A current mirror circuit usable with a single cell
voltage supply and comprising:
a voltage supply;
a reference voltage source;
first and second transistors of the same conductivity type
with bases coupled together, the second transistor being coupled
between the voltage supply and the reference voltage source and
supplying an output current:
a first current reference source coupled to the first
transistor means;
a resistor coupled to the voltage supply:
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diode means coupled between the resistor and the bases of
the first and second transistors;
an adjustable current source coupled between the bases of
the first and second transistors and the reference voltage
source; and
a third transistor of the said conductivity type coupled
between the resistor and the reference voltage source for
forcing the output current to be a direct function of the
reference current provided by the first current reference source.
1~ Brief Description of the Drawing
Fig. 1 is a schematic diagram of a conventional prior
art current mirror circuit.
Fig. 2 is a schematic diagram of a Wilson prior art
current mirror circuit.
Fig. 3 is a schematic drawing of the current mirror
circuit of the present invention.
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Fig. 4 is a schematic diagram of an application of the
circuit of Fig. 3.
Detailed Description of a Preferred Embodiment
Fig. l shows a schematic diagram of a typical current
mirror circuit as is well known in the art, and is given
here to serve as a reference only. It consists of matched
transistors Ql, Q2 and a current reference source IREF. Ql
is diode-connected and is coupled to the reference current.
The collector current of Q2 (IC2) is the output current of
the circuit. Since the emitter current in a bipolar trans-
istor is a function of the emitter-base junction saturation
current density, the area of that junction, electronic
charge, the base-emitter voltage, Boltzmann's constant, and
the absolute temperature, it is apparent that, for transis-
tors of the same conductivity type on one IC chip, the only
variable between emitter currents is the emitter-base junc-
tion area; i.e., IE2 = NIEl, where N is the ratio of
the two emitter-base junction areas.
IBl IE1/(s + l)~ IB2 = NIEl/(~ + l) and
= IC/IB, then IREF = ICl + IBl + IB2 ~IBl + IBl Bl'
C2 ~IB2 = ~NIBl Therefore,
C2 = ~NIBl = N
REF ~IBl + IBl + NIBl l + (N+l)/~
Thus IC2 = NIREF/~l + (N+l)/~], and only for large values
of beta does IC2 closely approximate NIREFand the error
increases as N increases.
In the current mirror of Fig. 2, commonly known as the
Wilson current mirror, IoUT N
REF l + (N+l)
B(B+l)
the variation of IC2 with beta has been reduced by the
buffering action of Q3, (replacing the Ql diode connection
with the Q3 base-emitter junction) which supplies the base
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current for Ql and Q2 without significantly disturbing the
reference circuit. However, since the two diode drops are
in series, the use of this mirror structure requires a
supply voltage of at least 2 volts, which is more than is
available in many miniature electronic devices.
The circuit of the present invention as shown in the
preferred embodiment of Fig. 3, provides the advantages of
both the two previously described circuits and the disadvan-
tages of neither; i.e., it provides the same accuracy as
the latter circuit with the low voltage requirement of the
former.
Again, transistors Ql and Q2 (within dashed line 10)
are two matched devices, i.e. having the same conductivity
type and characteristics, preferably on a single chip. Both
Ql and Q2 are initially biased by a biasing network 12
consisting of R, Q4 and a current source IBIAS. Ql is
coupled to the reference source IREF as before. A balance
sensing circuit 14 such as transistor Q5, compares ICl and
IREF and adjusts the mirror circuit bias voltage until the
two currents are equal. Since Ql and Q2 have matching
characteristics, IC2 is forced to equal NIREF, N being
the ratio of the two base-emitter junction areas.
More specifically, IBIAS establishes a voltage drop
across the combination of the diode-connected transistor
Q4 and the resistor R that biases the base-emitter junctions
of transistors Ql, Q2. The bias network parameters, namely
the value of the current source IBIAS~ the value of R and
the voltage drop across Q4 at the bias current level are
selected so that, if transistors Ql and Q2 require no base
current (if they had infinite beta), the base to emitter
voltage of transistors Ql, Q2 would correspond to the value
needed to establish an emitter current of IREF in Ql and
NIREF in Q2.
For finite values of transistor beta, transistors Ql,
Q2 will draw base current from the current source IBIAS~
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with the result that less current will flow through Q4 and
resistor R. In consequence,the collector current of Ql will
be less than IREF. Transistor Q5 serves to measure this
imbalance between the mirror currents,the excess current is
S the base current for Q5, which is multiplied by the beta of
Q5 and applied to the resistor R of the bias network 12.
The current through R that is applied by transistor Q5
serves to increase the base-emitter voltage of Ql and Q2,
and raises the value of the mirror current until it very
closely approximates the value of the reference current. It
can be shown then that,
IC2 = N
IREF 1 + (
~(~ + 1)
It will be noted that this is the same expression given
above for the Wilson current mirror.
Fig. 4 shows a typical use of a current mirror in an IC
design where the mirror circuit of Fig. 3 is used to
transfer a current reference level from an NPN transistor to
a series of PNP transistors. With prior art circuits,
separate current reference circuits would have been required
for biasing various chains of interconnected current source
transistors due to the beta sensitivity problem.
In this application, a current reference at a terminal
16, which is used in Circuit No. 1 is also needed in Circuit
No. 2. As may be seen in Fig. 4, the Q2 of Fig. 3 may
actually be any desired number of transistors Q2, Q2', etc.
The current sources supplying IREF and IBIAs are here
shown as PNP transistors Q6 and Q7, respectively, but Q6
functions with Q8 as a conventional current mirror (similar
to that of Fig. 1), using the current reference from
terminal 16. IREF may be made any desired fraction of IC8
by ratioing the areas of Q6 and Q8, or by the use of Q9 and
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R2, diverting a portion of IC8 from the base-emitter junc-
tion of Q8 and thus reducing IREF accordingly (this control
including ON-OFF type control). This current diversion may
be accomplished via a control terminal 18. The current in
each individual current source transistor is accurately
controlled and separate current reference circuits are no
longer required. The elimination of the extra reference
circuits results in significant savings in IC chip area and,
therefore, in IC cost.
Thus, there has been shown and described a current mir-
ror circuit for integrated circuit application particularly
which will provide highly accurate reference currents with
voltage supplies lower than 2 volts. While specific cir-
cuits and transistors have been shown as preferred, it will
be obvious to those skilled in the art that other choices of
transistors and arrangements thereof are possible and it is
intended to cover all such as fall within the spirit and
scope of the appended claims.
