Language selection

Search

Patent 1149969 Summary

Third-party information liability

Some of the information on this Web page has been provided by external sources. The Government of Canada is not responsible for the accuracy, reliability or currency of the information supplied by external sources. Users wishing to rely upon this information should consult directly with the source of the information. Content provided by external sources is not subject to official languages, privacy and accessibility requirements.

Claims and Abstract availability

Any discrepancies in the text and image of the Claims and Abstract are due to differing posting times. Text of the Claims and Abstract are posted:

  • At the time the application is open to public inspection;
  • At the time of issue of the patent (grant).
(12) Patent: (11) CA 1149969
(21) Application Number: 1149969
(54) English Title: THYRISTOR
(54) French Title: THYRISTOR
Status: Term Expired - Post Grant
Bibliographic Data
(51) International Patent Classification (IPC):
  • H01L 29/74 (2006.01)
  • H01L 29/417 (2006.01)
(72) Inventors :
  • VOSS, PETER (Germany)
(73) Owners :
  • SIEMENS AKTIENGESELLSCHAFT
(71) Applicants :
  • SIEMENS AKTIENGESELLSCHAFT (Germany)
(74) Agent: OLDHAM AND COMPANYOLDHAM AND COMPANY,
(74) Associate agent:
(45) Issued: 1983-07-12
(22) Filed Date: 1980-02-28
Availability of licence: N/A
Dedicated to the Public: N/A
(25) Language of filing: English

Patent Cooperation Treaty (PCT): No

(30) Application Priority Data:
Application No. Country/Territory Date
P2907732.5 (Germany) 1979-02-28

Abstracts

English Abstract


8 48,826
ABSTRACT OF THE DISCLOSURE
The present invention provides with a single
body of semiconductor material a main thyristor and two
auxiliary thyristors. The two auxiliary thyristors are
connected in a parallel electrical circuit relationship
and one of the auxiliary thyristors fires at a lower dv/dt
than either the main thyristor or the other auxiliary
thyristor.


Claims

Note: Claims are shown in the official language in which they were submitted.


6 48,826
We claim as our invention:
1. A semiconductor device comparing within a
single body of semiconductor material a main thyristor and
a first and a second auxiliary thyristor, the two auxil-
iary thyristors being connected together in a parallel
electrical circuit relationship.
2. The semiconductor device of claim 1 in which
the second auxiliary thyristor fires at a lower dv/dt
loading than the first auxiliary thyristor and the main
thyristor.
3. The semiconductor device of claim 1 in which
the first and the second auxiliary thyristors have sepa-
rate emitter regions and a common emitter electrode.
4. A semiconductor device comprising a body of
semiconductor material, said body having a major top
surface, said body being comprised of a main thyristor and
a first and a second auxiliary thyristor, each of said
thyristors being comprised of four regions of alternate-
type conductivity, a p-n function between adjacent re-
gions, said main thyristor having an emitter region and an
adjacent base region terminating on said top surface, an
electrode affixed to said emitter region on said top
surface, a second electrode affixed to said base region on
said top surface, said electrodes being spaced apart from
each other, said first auxiliary thyristor being disposed
between said emitter electrode and said base electrode,
said first and said second auxiliary thyristors being con-
nected in a parallel electrical circuit relationship.
5. The device of claim 4 in which said second

7 48,826
auxiliary thyristor fires at a lower dv/dt loading than
said main thyristor and said first auxiliary thyristor.
6, The device of claim 5 in which the two
auxiliary thyristors have separate emitters and are
electrically connected by a common emitter electrode.
7. The device of claim 6 in which the emitter
region of the main thyristor surrounds the emitter regions
of the auxiliary thyristors.
8. A self-protected semiconductor controlled
rectifier device comprising:
a first layer of a first conductivity type,
a second layer of a second conductivity type,
being adjacent to said first layer for
forming a first PN junction therewith,
a third layer of said first conductivity type,
being adjacent to said second layer for
forming a second PN junction therewith,
a fourth layer of said second conductivity type,
being adjacent to said third layer for
forming a third PN junction and having an
exposed surface,
a first main electrode in ohmic contact with at
least the surface of said first layer, and
a second main electrode in ohmic contact with at
least the surface of said fourth layer;
(ii) a pilot thyristor section including said first,
second and third layers, said first electrode and a fifth
layer, said fifth layer being isolated from said fourth
layer by said third layer, adjacent to said third layer
for forming a fourth PN junction therewith having an exposed
surface, being smaller in area than said fourth layer, and
being adapted to operate in association with said main
thyristor thereby to turn on said main thyristor section when
said pilot thyristor section is turned on;
(iii) an auxiliary pilot thyristor section including said
first, second and third layers, said first main electrode,
and a sixth layer of said second conductivity type, said
sixth layer being isolated from said fourth layer, having

8 48,826
an exposed surface, forming a fifth PN junction with said
third layer, and being smaller in area than said fourth
area;
(iv) a gate means in contact with a part of
the surface of said third layer for turning on said pilot
thyristor section in response to a gate signal being applied
to said gate means;
(v) first auxiliary gate means being in contact
with said fifth layer; and
(vi) second auxiliary gate means being in contact
with said sixth layer;
the improvement wherein:
(vii) said auxiliary pilot thyristor section is
triggered with a voltage increasing rate dV/dt lower than
those of said pilot thyristor section and said main thyristor
section, and
(viii) the whole peripheral region of said fifth PN
junction is short-circuited by said second auxiliary gate
means.
9. A self-protected semiconductor controlled
rectifier device comprising:
(i) a main thyristor section including,
a first layer of a first conductivity type,
a second layer of a second conductivity type, being
adjacent to said first layer for forming a
first PN junction therewith,
a third layer of said first conductivity type,
being adjacent to said second layer for
forming a second PN junction therewith,
a fourth layer of said second conductivity type,
being adjacent to said third layer for forming
a third PN junction and having an exposed
surface,
a first main electrode in ohmic contact with at
least the surface of said first layer, and
a second main electrode in ohmic contact with at
least the surface of said fourth layer;

9 48,826
(ii) a pilot thyristor section including said
first, second, and third layers, said first electrode, and
a fifth layer, said fifth layer being isolated from said
fourth layer by said third layer, adjacent to said third
layer for forming a fourth PN junction therewith, having
an exposed surface, being smaller in area than said fourth
layer, and being adapted to operate in association with
said main thyristor section thereby to turn on said main
thyristor section when said pilot thyristor section is
turned on;
(iii) an auxiliary pilot thyristor section in-
cluding said first, second, and third layers, said first
main electrode, and a sixth layer of said second conductiv-
ity type, said sixth layer being isolated from said fourth
layer, having an exposed surface, forming a fifth PN junction
with said third layer, and being smaller in area than said
fourth area;
gate means in contact with a part of the surface
of said third layer for turning on said pilot thyristor
section in response to a gate signal being applied to said
gate means;
auxiliary gate means for electrically connecting
said pilot thyristor section and said auxiliary pilot
thyristor section;
the improvement wherein:
said auxiliary pilot thyristor section is lower
in voltage increasing rate dV/dt than said pilot thyristor
section and said main thyristor section, and
the whole peripheral region of said fifth PN
junction is short-circuited by said auxiliary gate means.
10. A self-protected semiconductor controlled
rectifier device as defined in claim 8 or 9 wherein said
sixth layer is formed in a disc-like shape.
11. A self-protected semiconductor controlled
rectifier device as defined in claim 8 or 9 wherein said
main thyristor section is formed to surround said pilot
thyristor section and auxiliary pilot thyristor section
which comprise said gate means and auxiliary gate means.

Description

Note: Descriptions are shown in the official language in which they were submitted.


:~149i~9
1 48,826
THYRISTOR
BACKGROUND OF THE INVENTION
Field of the Invention:
The present invention is in the -field of semi
conductor devices generally and specifically concerned
with thyristors.
Description of the Prior Art:
Semiconductor devices consisting of a main
thrystor and one or two auxiliary thyristors all contained
within a single body of .sili,con are known.
The function of the auxiliary thyristors in such
devices is to amplify the control current fed in via the
gate electrode. A single auxiliary thyristor suffices for
sorae applications while, for others, two auxiliary thyris-
tors are required. In these latter cases, the auxiliary
'L5 thyristors are connected in cascade, that is, the output
of one is electrical,ly connected to the input of the
other.
As is known, thyristors cannot only be fired by
means of a contro] current, but also by an overvoltage
'~) applied to the main electrodes or by means of a steep rise
in the voltage. This ],ast method is known as dv/dt fir-
ing.
'Ln the case of dv/dt firing, the thyristor can
be destroyed when the load current induced hy the external
switching of the thyristor ri.ses so rapidly that the
thyristor becomes locally overheated before the firing
process has progressed to an appreciable extent. In order
t-o protect the main thyristor from high loading during
7~,f
:` ";
'` ' , ' :
' '
. :
-: . . ' . ' ': ' '' ' , . .

4~ ~ ~ 9
2 48,826
dv/dt firing, it was proposed to so dimension the auxil-
iary thyristor that a dv/dt loading which would be harmful
to I:he main thyristor fi.rst tires the auxi-liary thyrixt.or
whose load current then initiates the firing of the mai
thyristor. This results in ~he controI current to the
main thyristor being spread over a large area, and damage
to the main thyristor due to high loading on a small area
is prevented.
Thyristors which are provided with auxiliary
thyristors sensitive to dv/dt loading can, however, be
fired unintentionally at dv/dt value~, which lie far below
the maxim~m permitted dv/dt values for the thyristor when,
for example, a spurious voltage is fed into the control
line via the firing transmitter during the dv/dt loading.
I5The present invention overcomes these shortcom-
ings of the prior art devices.
SUMMARY OF `rHE INV TION
The present invention is directed to a semicon-
ductor device comprising wi.th a unitary body of semico~-
ductor materi.al a main thyristor and two auxiliary thyris-
tors, said auxiliary thyristors being connected in a
parallel electrical circuit re].ationship and one of said
auxiliary thyristors being so designed as to fire at a
lower dv/dt than said other auxiliary thyristor and said
rnain thyristor.
DESCRIPTION OF T~IE DRAWlNGS
For a better understanding of the prcsent inven-
tion reference should be had to the foll.owing detailed
discussion and drawings in which:
30Figs. 1 and 2 respectively show a fragmentary
cross-section and plan view of a first embodiment of the
present invention;
Figs. 3 and 4 respectively shown a fragmentary
cross-section and plan view of second embodiment of the
3~ present invention; and
Figs. 5 and ~ respectiv~ly show a fragmentary
cross-section and plan view of a third embodiment of the
present invention.

li499~9
3 48,826
DESCRIPTION OF 'rHE PREFERRED EMæODDMENTS
With reference to Figs. 1 and 2 thare ls ~hown a
rragmentary portlon o~ a body 10 of semiconductor material
contalning a thyristor12. Only the mo~t lmportant ele-
ments oi the thyrl~tor are shown. me thyrlstor ha~ a base
region 14 and an emltter reglon 16 to which 18 afflxed an
emitter electrode 18. Aifixed to the base reglon 14 is a
control or gate electrode 20. A first auxlllary emitter
region 22 lles between the control electrode 20 and the
emitter region 16 emltter 22 making electrical ohmic
contact with an auxiliary emitter electrode 24. The iirst
auxillary or pilot emitter 22 belong~ to a first auxiliary
thyristor 26, while the emitter 16 belongs to the main
thyristor 12. Located near the ~irst auxiliary emitter 22
is a second auxillary emitter region 28 which belongs to a
second auxiliary thyrlstor 30. me second auxiliary
emitter 28 is co~pletely covered by the auxlliary emitter
electrode 24. Auxiliary emltter~ 22 and 28 are surrounded
by the main emitter 16.
me auxiliary emitters 22 and 28 are designed in
such a way that, with the second auxlliary emitter region
28, tho ~econd auxillary thyrlstor 30 is more sen~itlve
with respect to dv/dt loadings than the ~ir~t auxiliary
thyristor 26 with the ~irst auxiliary emitter region 22.
This can be achieved by hav~ng a certain ratio between the
dlameters of the auxillary emitters. me stated flring
condition will always be achieved when the following
applles to the dimen~ions o~ the emltters:
r22 _ r2 ~ r3
where r1 and r2 are the respective internal and external
radil o~ emltter reglon 22 and r3 18 the external radlus
o~ emitter region 28 (~or example, r1 = 2mm, r2 m 3 mm and
r~ - 3mm.
In the event of a dv/dt load applled to the
thyrlstor's main electrodes, which could lead to the
~ . . .. . , . , , , .; . .... " .. . - ... .. .. . ~ i . .

6~
4 48,826
destruction of the main thyristor 12, the secondary auxil-
iary thyristor 30 with the second auxiliary emitter region
in the center is fired. The second auxiliary thyristor's
load current then flows in known manner through the auxil-
iary emitter electrode 24 to the main emitter region 16causing the latter to fire uniformly. As a result, the
main thyristor 12 cannot be destroyed. On the other hand,
the first auxiliary thyristor 26 is not fired by the same
dv/dt load because of its different dimensioning, it is
less sensitive with respect to dv/dt loads than the second
auxiliary thyristor 30. Based on the width of the second
auxiliary emitter region 28, the width r2 ~ rl of the
first auxiliary emitter can be freely chosen within wide
limits as long as the condition given above is fulfilled.
By this means, it can be ensured that the first auxiliary
thyristor does not fire on account of dv/dt, except when a
spurious current flows from the control line into the
control electrode 30 during the dv/dt loading.
The embodiment illustrated i.n Figs. 3 and 4
2~ differs from the one shown in Figs. 1 and 2 simply by the
fact that, in the region of the second auxiliary thyris-
tor, auxi.liary emitter electrode 32 is provided with a
clearance or recess 34. There is a p-n junction 36 be-
tween the second au,Yi ~ iary emitter region 38 and base 14.
~r~ Jnner edge ~0 ~f p-n junction 36 extends wi.thin the clear-
ance 34, concentrically with the latter, at the surface of
t:he semiconductor body. The advantage to be gained in
Lhis embodi.ment, by comparison with the first embodiment,
resides in the fact that in this embodiment it is pos-
sible, in principle, to have a linear-form firing region
along the emitter's i.nterior edge whi.le, in the first
arrangement, firing takes p]ace in the forM of a point in
the center, as a result of which the current dens;ties can
become very high and which is unsatisfactory when the
di/dt loadability is taken into account. The above-
mentioned -firing condition is reached for r~ - rl ~ r3
-r~ (r4 ~- inLernal radi.us of 10).
Figs. 5 and 6 show a variant of the embodiment

6 ~
4~,826
illustrated in Figs. 3 and 4. This differs essentially in
that a third auxiliary emitter region 42 is provided,
locat-ed between t,he first and second auxiliary emitter. A
second auxiliar emitter electrode is designated 44 and is
provided with a "nose" 46 which overlaps part of p-n
junction 48 of the third auxiliary emitter 42. The auxil-
iary emitter electrode common to the first and third
auxiliary emitters is designated by 50. The second and
third auxiliary emitters are connected in cascade. That
is, the output of one is connected to the input of the
other. The purpose of this arrangement is rapidly to
unload the especially endangered second auxiliary thyris-
tor by the third auxiliary thyristor. If need be, the
width of the nose can be so adjusted that the second
auxiliary thyristor does not fire prior to the third
auxiliary thyristor but serves merely as a firing-current
amplifier for the third auxiliary thyristor. Thus, with
the structure illustrated in Figs. 5 and 6, the first
auxiliary thyristor is appreciably less sensitive to dv/dt,
Ioadings than the cascade formed by the second and third
auxiliary thyristors.

Representative Drawing

Sorry, the representative drawing for patent document number 1149969 was not found.

Administrative Status

2024-08-01:As part of the Next Generation Patents (NGP) transition, the Canadian Patents Database (CPD) now contains a more detailed Event History, which replicates the Event Log of our new back-office solution.

Please note that "Inactive:" events refers to events no longer in use in our new back-office solution.

For a clearer understanding of the status of the application/patent presented on this page, the site Disclaimer , as well as the definitions for Patent , Event History , Maintenance Fee  and Payment History  should be consulted.

Event History

Description Date
Inactive: IPC from MCD 2006-03-11
Inactive: Expired (old Act Patent) latest possible expiry date 2000-07-12
Grant by Issuance 1983-07-12

Abandonment History

There is no abandonment history.

Owners on Record

Note: Records showing the ownership history in alphabetical order.

Current Owners on Record
SIEMENS AKTIENGESELLSCHAFT
Past Owners on Record
PETER VOSS
Past Owners that do not appear in the "Owners on Record" listing will appear in other documentation within the application.
Documents

To view selected files, please enter reCAPTCHA code :



To view images, click a link in the Document Description column. To download the documents, select one or more checkboxes in the first column and then click the "Download Selected in PDF format (Zip Archive)" or the "Download Selected as Single PDF" button.

List of published and non-published patent-specific documents on the CPD .

If you have any difficulty accessing content, you can call the Client Service Centre at 1-866-997-1936 or send them an e-mail at CIPO Client Service Centre.


Document
Description 
Date
(yyyy-mm-dd) 
Number of pages   Size of Image (KB) 
Claims 1994-01-14 4 171
Cover Page 1994-01-14 1 13
Drawings 1994-01-14 2 44
Abstract 1994-01-14 1 9
Descriptions 1994-01-14 5 185