Note: Descriptions are shown in the official language in which they were submitted.
~513~3
Technical Field
The technical field to which the invention pertains
relates to the art of dual slope analog-to~digital con-
verters for effecting a digital output signal of a measured
analog signal being supplied to the converter.
Background of the Invention
The dual slope type analog-to-digital dual slope con-
verter for effecting a digital output signal from a measured
analog input signal is well known as disclosed, for example,
10 in U. S. patents 3,061,939; 3,316,546; 3,458,803, 3,660,834
and 3,566,397. Briefly, the method of conversion involves
integrating a current directly related to an unknown voltage
for a fixed period of time, followed by the integration of
a standard current related to a reference voltage of opposite
- polarity until the integrator output returns to zero. The
total time period required to null the integrator is directly
proportional to the ratio of the measured current to the
standard current, and, therefore, to the measured voltage.
The integrator, therefore, is a circuit producing a linearly
changing output with time ~usually a ramp) when the input is
some constant voltage and the rate of integrator output
voltage increase is directly proportional to the magnitude
of input voltage. When input voltage is zero, output voltage
is not subject to chan~e but remains zero at whatever output
value was achieved at the beginning of the time period.
Standard operation for such prior art converters has
included integration of the unknown in the same direction
of polarity as the input signal, e. g. positive-to-positive
which is then switched to a reference signal of opposite
polarity that is integrated to zero. This is then detected
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by a comparator of the integrated signals and for large
analog inputs prolonged time periods are required to effect
the zero integration. The digital counts are then accumulated
in a register proportional to the time factor associated
with the unknown integration.
While this basic arrangement has functioned well
with a high order of accuracy, it requires reference switching
and polarity detection which becomes difficult at very low
inputs leading to switching uncertainties. Also, bias
currents associated with these prior devices have added and
subtracted from the slopes in each of its changed directions.
For overcoming these deficiencies, it has been necessary to
utilize precision low offset amplifiers. Despite recognition
of the foregoing, means for effecting their elimination has
not heretofore been known.
Summary of the Invention
This invention is used with analog-to-digital
conversion apparatus for effecting a digital output signal
correlated to an analog signal being emitted from a condition
responsive transducer. More specifically, the invention is
used with an A/D converter of the dual slope type able to
eliminate the reference switching and bias current problems
characteristic of such prior art converters whereby to
enhance the overall accuracy and reliability of such systems.
The invention affords enhanced linearization of the output
signal.
The converter always integrates the unknown analog
input signal in a direction polar opposite to a reference
signal enabling one of the two prior used reference signals
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to be eliminated. At the same time there is afforded the
ability to both measure and verify polarity of the input
signal without regard to the signal level. By using the
integrator in a non-inverting mode, the A/D converter
integrates positively all the analog signal values below a
maximum negative input voltage while accumulating digital
counts proportional to the differences therebetween. A
digital display or other appropriate digital device is then
operated by the count signals received from the converter.
Digital linearization of the count signals is provided for
correcting any encountered deviation from ideal linearity.
This is achieved by a programmed microcomputer reading a
PROM to run a variable frequency clock via the PROM
programming. The clock frequency is regulated to effect a
first phase converter time that corresponds with an even
multiple of the power line frequency. Accumulator counts
will then vary directly with clock frequency.
Specifically, the invention relates to a system for
linearizing the digital output of a dual slope analog-to-
digital converter, operating for a fixed time period in onemode followed by a variable time period in another mode,
comprising a variable frequency clock and means operative
to drive the clock during the fixed time period of the
converter at a frequency comprising an even multiple of the
power line frequency at which the converter is to be used
and to drive the clock during the variable time period at
controlled changes in frequencies per unit of time in
accordance with deviation from linearity of the analog
signal being received by the converter.
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Brief Description of the Drawings
Fig. 1 is a block diagram of converter apparatus;
Fig. 2 is an electronic schematic of a modified dual
slope A/D converter;
Fig. 3 is a timing diagram for the dual slope
converter of Fig. 2 at zero and non-zero signal levels; and
Fig. 4 is the present invention applied to the dual
slope converter of Fig. 2 for affording digital linearization.
Referring first to Fig. 1, there is disclosed a
transducer 10 adapted to continuously emit an analog signal
Va correlated to the measured value of a condition being
measured by the transducer. Transducer 10 can typically be
an,v suitable type measuring instrument from which an analog
output can be obtained and in a preferred use may constitute
a pressure or temperature transducer as disclosed, for
example, in U.S. Patents 3,742,233 or 4,109,147. Analog
signal Va from the transducer, along with a reference signal
Vr of a known regulated voltage as will be explained are both
supplied to A/D converter 12 in accordance herewith to in
turn emit a count signal Vd for any of a variety of applications
such as for operating a digital display 14.
Referring now to Fig. 2, the modified A/D dual slope
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i~S13Q3
converter 12 hereof is comprised of a summing amplifier
16, an integrator 18, a comparator and auto-zero amplifier
20, a sample/hold amplifier 22 and a logic and accumulator
module 24 which for the embodiment being described is of
a commercially available type similar to National Semi-
conductor MM5330 A/D Building Block operative as will be
explained below. Analog signal Va, being supplied from
transducer 10 in correlation to its measured parameter,
is of negative polarity for connection directly through
switch SW-l to summing amplifier 16, while reference volt-
age Vr, being supplied from a regulated voltage source,
is of negative polarity for connection through switch SW-2
to comparator and auto-zero amplifier 20. The output of
amplifier 16 is provided through switch SW-3 to the
positive terminal of integrator 18 while a ~max voltage
is deri~ed from Vr through dividers Rl and R2 for feeding
the negative terminal of integrator 18. By way of example,
if maximum positive voltage at Va = 1.9999 volts, Vmax
would arbitrarily be set at 2.2000 volts and at Va = zero
measurement would be based on 2.2000 volts. Logic and
accumulator module 24 provides the logic for sequencing the
aforementioned switches.
With reference also to Fig. 3, the complete A/D con-
version cycle of transducer signal ~a is shown in which
Va = 0 volts is the solid slope and Va ~ 0 volts for a
measured value not equal to zero has a dashed slope. The
cycle from left ~o right (Fig. 3) consists of three phases
being auto-zero phase III, the integrator reference phase
I for a predetermined fixed time period Tr and the inte-
grated unknown phase II for a variable time period Tx.
~uring phase IIl, comparator and auto-zexo amplifier 20
functions as a high gain zeroing amplifier that with switch
SW-4 closed, drives sample/hold amplifier 22, capacitor C-l
and inverting summiny amplifier 16 through switch SW-3 to
restore the integrator capacitor C-2 voltage to zero volts.
Switches SW-l, SW-2 and SW-5 during this phase are all in
grounded position. Also, because of the characteristics of
amplifier 22, all amplifier voltage offsets are stored on
capacitor C-l where they remain through the integration
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11513~3
cycle serving to eliminate even large offset voltages.
During phase I, in response to a received power line
sync si~nal, switches SW-4 and SW-5 are opened. Refer-
ence voltage Vr is applied through switch ~W-2 to amplifier
20 for simultaneously establishing Vmax via divider Rl
and R2. Vmax is chosen based on the full scale counts
desired. At the same time, Va is connected to the input
integrator 18 via summing amplifier 16 and switch SW-3.
The output of integrator 18 then slews to Va for integra-
tion to begin for a reference period Tr during which timeintegration occurs or a signal value based on the differ-
ential between (Vmax - Va). Time Tr is preferably selected
to be of some even multiple of the local power line fre-
- quency for increasing the normal mode noise rejection of
the converter.
On completion of phase I, phase II is initiated dur-
ing which reference voltage Vr is applied to integrator 18
for the unknown period Tx until the threshold of compara-
tor 20 is crossed in its comparison between the signal
levels of Vr and the integrator output. At such time,
coincident with the comparator output, the digital counts
which accumulated during integration period Tx are
transferred from the counter to the latches, the parallel
output signal of which Vd is applied to display unit 14
or transmitted elsewhere as desired. The latter can be
understood by the following example in which:
Tr -- CO
Cf
Where CO = counts overflow
Cf = clock frequency ~HZ)
assuming third harmonic of 60HZ = .050 sec.
and CO = 18000 then
Cf = 36000 HZ
~here Va equal zero and Vmax is measured,
a complete conversion will occur on
the basis of:
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Tc = Tr + Tx (Fig. 3)
360000 + 360000 = 0.1:Lllll sec
with + 0000 displayed.
For any positive Va less than Vmax the code converter 9's
complements the counter to display the measured value.
In this manner, display 14 yields a linear conversion for
Va less than Vmax.
For effecting digital linearization usable with A/D
converter 12 or with any dual slope standard system, re~erence
is made to Fig. 4 in which there is shown a schematic
circuit therefor including a microcomputer 26, the PROM 28
and a variable frequency clock source 30 connected to
logic and accumulator module 24. During phase I (Fig. 3),
microcomputer 26 reads PROM 28 for receipt of programmed
information to drive clock 30 at a frequency such that Tr
is an even multiple of the power line frequency. Each of
microcomputer 26, PROM 28 and clock 30 are commercially
available from various manufacturers. Microcomputer 26
can, for example, comprise a single chip microcomputer
manufactured by Fairchild Camera and Instrument or Mostek
Corp. under the designation -F3870-- while PROM 28 can be
obtained from either Signetics under their commercial
designation DM74S188 or from Texas Instruments under
their commercial designation -SN74188--. Oscillator 30
is available as a 74LS04 gate with crystal feedback while
the counters are 74LS193 types, both manufactured by
various integrated circuit manufacturers such as National
Semiconductor.
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~513Q3
Phase II is sensed by the microcomputer on
the convert line Co and based on information received
from PROM 28 drives the frequency of clock 30 at
various rates per unit time as programmed into PROM 28.
In this manner, clocking frequencies that are different
between phases II and I do not affect the conversion
time which instead remains constant for a given input
voltage Va. Integrator 18 functions in the same manner
as described above while the counts accumulated during
time period Tx will vary more directly dependent on
the frequency of clock 30. Should Va be a non-linear
response of some linear function being measured, the
final accumulated counts are therefor adjusted in
that manner to yield a linear digital representation
of the measurement.
If, for example, different clocking frequencies
are utilized during phase II than phase I, the
conversion time nevertheless remains the same for
a given input voltage Va since integrator 18 makes
the same excursion. The counts accumulated during
Tx will be more or less depending on the frequency
of clock 30 such that the accumulated counts over the
course of Tx can be varied in direct relation to the
value of Va. Using the previous example and varying
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the clocking frequency a number of times tn) then when
n = s
Tn = Tx = .0122222 and
- Nt = Tn (F2) + Tn (F3) + Tn (~) + Tn (Fs) + Tn (F6)
where Fl = clock frequency during Tr = 360 KHZ
F2 = " " ~l Tx = 350
3 " " = 340
4 " " = 300
F~ = " " " " = 360
6 " " = 450
Nt = 21997 and if the dual slope converter hereof
reaches crossover Tx = .0366666 seconds, three
corrections have occurred and the display will read:
22000 - Tn (Fl + F2 + F3) = 9902 counts
In the same example with a constant clocking frequency
Tx = .0611111 Tn = .0122222
giving an Nt = 21999 and Linear Display =
22000 - 13200 = 8800 counts
Comparison of the above examples shows that in both cases
the total number was essentially the same but the non-
linear accumulation resulted in a 1102 count increase
for a given Va = Tx.
By the above description there is disclosed a novel
modification of an analog-to-digital dual slope type con-
verter able to give a linear digital representation of a
non-linear analog signal representing the measured output
of a condition responsive element. By use of relatively
inexp~nsive non-critical components, the precision elements
required for eliminating the inherent problems of standard
dual slope systems are thereby avoided. When employing
linearization in accordance herewithr ~reater flexibility
is afforded as compared to analog summing techniques
previously utiliæed. Moreover, the linearization attains
the precision of a digital correction that is highly
repeatable and inherently temperature stable with the
ability to tailor the response from one instrument to the
other. Whereas the linearization has been described in
combination with the modified dual slope converter hereof,
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it is not intended to be so limited since it could be
readily utilized with such stand~rd unmodified dual slope
converters of the prior art.
Since many changes could be made in the above con-
struction and many apparently widely different embodiments
of this invention could be made without departing from
the scope thereof, it is intended that all matter con-
tained in the drawings and specification shall be
interpreted as illustrative and not in a limiting sense.
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