Note: Descriptions are shown in the official language in which they were submitted.
5ZS~i~
This application is a division o our Canadian Patent Application
Serial No. 322,004 filed February 21, 1979.
This invention relates to analy~ing electrical circuit boards, e.g.,
to identify an integrated circuit which has failed.
In testing circuit boards it is desirable to be able to identify
individual elements which have failed without having to disconnect the elements
from the circuit. Circuit faults can be detected by voltage and waveform
measurements, but when several elements are connected to a point it is difficult
to identify, e.g., which element has short circuited to ground. Current tracing
and measurement methods may locate the failed element but generally require
successive measurements to be made at various points between elements, which
can be difficult when conductive paths between the elements are short.
It is also desirable to be able to test individual elements by making
the necessary contacts with the circuit at positions on the board which are
readily located by unskilled operators, e.g., on a lead of an element rather
than at specified positions on the lands when the elements are closely spaced or t
the lands occupy both sides of the board.
~ ccording to ~me broad aspect of the invention there is provided,
in a probe for electrically contacting the lead of an IC with a plurality of
~ contact tip portions spaced apart sufficiently to permit measurement of elec- `
trical activity in a lead element therebetween, that improvement comprising a
support having an axis, and a plurality of contact elements carried by said
support, each said element having an operating position, at least one said
element having a rest position with a portion of itself spaced from said sup-
port and being resiliently movable about said axis to an operating position
against said support, said elements in said operating positions having co-
planar contact tip portions, said one element having one leg extending gener-
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ally along said axis and the other leg generally transverse to said axis and
having said tip portion thereon, whereby said one leg acts as a torsi~n spring
when said tip portion is moved between its rest and operating positions.
In a preferred embodiment, the spaced contact tips span a total
distance of no greater than 0.08 inch, so as to reliably fit on the straight
portion of a mounted IC lead. The test current is separate from the normal
operating current of the board and is injected directly into the lead through
a third probe tip, which may contact a point on the lead electrically in
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common with that'contacted by one of the other tips~ The third ti~ contacts
the lead at a point farther from the IC than the othcr two tips, so that the
measured test current is flowinv into the ICo Circuitry is provided to
monitor the electrical contacts between the probe tips and the lead.
An embodiment features providing a probe with at least t~Yo tips
spaced generally as above set forth, injecting a test signal directly into
the lead via the probe, measuring the voltage drop across a lead segment
produced by test current flowina into the IC, also measuring the vol~age
drop across a lead segment produced by test current flowing away from the IC,
and determining the ratio between the internal resistance Rl of the IC on
the lead and the parallel resistance R2 of the remaining IC~s on the node~
which ratio is independent of the resistance of the lead segment. This is
also useful for measurements made on circuit board lands.
E~bodiments feature, in another aspect~ providing a probe having
at least three equally spaced tips arrange~ to simultaneously contact the
straight portion of a mo~ulted IC lead, injecting a test signal througll the
tip nearest the IC and measuring the voltage drop between the other two
tips due to the current component flowing away from the IC through a first
lead segment, injecting a test signal through the tip farthest from the IC
and measuring the voltage drop between the tips closest to the IC due to the
current component flowing into the IC through a second lead segment equal
in length to the first. The ratio Rl/R2 is thus easily and efficiently
determined. In preferred embodiments each tip is a single element tip,
and thc three tips span a total distance of no more than O.OS inchO
In yet another apsect, the invcntion features determining thc total
parallel resistancc R~ at thc nodc b~- injccting a test signal into the lead
and making at lcast one voltavc measurcmcnt thercon, dcterminin, thc ratio
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Rl/R2 by injecting at least one additional test signal into the lead and measur-
ing the voltage drops due to test current components flowing in opposite direc-
tions through the lead, whereby the absolute values of Rl and R2 may then be de-
termined. In preferred embodiments, with the circuit board powered up, and
using the three tip probe, a four step procedure is carried out with a single
placement of the probe: first, using one probe tip, node voltage is measured
without injecting a test signal; second, using the same tip, a dc test signal of
known current is injected and node voltage is again measured, the voltage dif-
ference between the first two steps being the result of the test current flowing
through the combined parallel resistance Rt and enabling determination thereof;
and third and fourth, injecting ac test signals and measuring the voltage drops
across equal length lead segments due to test current components flowing in op-
posite directions, to determine Rl/R2 as described above. Highly sophisticated
diagnosis of circuit board faults is thus made possible.
In yet another aspect the invention features using injected test sig-
nals in the below 10 milliampere range (the range preferably including currents
as low as 0.1 ~a) to produce measured voltages in the microvolt range and below
(the range preferably including voltages as low as 30 nv), all so as not to in-
terfere with normal operation of the powered up board and thus to expose faults
not otherwise easily detected. Preferred embodiments of the signal processing
circuitry capable of accurately handling such low signal levels feature, for the
ac signals, coupling the probe to a synchronous detector through a transformer.
In yet another aspect the invention features monitoring the contact
between the probe tips and the lead during the testing by comparing the signal
outputs of selected pairs of tips and indicating whether the comparison is as
expected. In preferred embodiments a special ac signal, differing substantially
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in frequency from the ac test signal, is injected in 180 phase shifted versions
into two tips, so as to cancel in the probe output if both tips are in good con-
tact with the lead.
Aspects of the invention can also be useful for measurement made on
circuit board lands.
In still another aspect, the invention features estimating whether
there is an active driving IC on the node by determining Rl for at least one
IC on the node, and the R2 corresponding to that Rl, and comparing Rl or R2
(preferably the smaller) to a value K selected to be no smaller than the ex-
pected driver resistance Rd for the type of IC being tested.
In another aspect of the invention, after determining that an activedriver is most likely present on the node, an Rl larger than R2 is selected as
faulty if node voltage is too high, and an Rl smaller than R2 if node voltage
is too low.
In yet another aspect of the invention, the possibility of a shorting
resistance is evaluated by determining whether the ratio Rl/R2 is outside a
range bounded at one end by the ratio Rs/Rd ~and preferably at the other end by
Rd/Rs), where Rsis a selected limit for the expected value of shorting resis-
tance being investigated. In preferred embodiments the TTL and ECL logic ICs,
a range of 0.2 to 5 is used to test for a shorting resistance between an input
IC and the internal supply voltage of the IC, and a range of 0.6 to 1.6 is used
to test for intermediate value shorting resistances causing a node voltage that
should be low but is held high. In the former case, if Rl/R2 is outside the
range 0.2 to 5, Rl is selected as faulty if smaller than R2. In the latter case
~i.e., the test for intermediate value shorting resistances), which is investi-
gated after determining that the fault probably is not in the driver and is not
a shorting resistance between an input circuit and internal supply voltage, an
Rl larger than R2 is selected as faulty if Rl/R2 is within the range 0.6 to 1.6,
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and an Rl smaller than R2 is selected if RL/R2 is outside that range. Finally,
if none of the above tests are positive, an Rl larger than R2 is selected as
faulty if node voltage is intermediate but should be low, and an Rl smaller than
R2 is selected if node voltage is low or intermediate but should be high.
In a preferred embodiment, the signal to noise ratio is improved in a
transformer coupled circuit by inserting, between the transformer and the syn-
chronous detector, a wide band amplifier for amplifying both the information
signal and noise present in the transformer output, without substantial band
limiting, followed by a filter having a passband of width intermediate those of
the amplifier and the synchronous detector and centered on the clock frequency
of the detector; preferably the amplifier has a gain-bandwidth product of at
least 5MHz, the filter passband is no wider than 10% of said clock frequency,
and the synchronous detector has a bandwidth no greater than 15 Hz.
In preferred embodiments the signal to noise ratio in transformer
coupled systems is improved by using coaxial cable for the transformer primary
with the outer shield grounded to provide an electrostatic shield, and using an
output cable from the probe in which four wires are arranged in two twisted
pairs, one tip is connected to a wire in each pair, and the other two tips are
respectively connected to the remaining two wires; preferably, the twisted pairs
are individually shielded, and a switch is provided to selectively connect
either of the wire pairs (and hence two tips) across the transformer primary,
while an ac test signal is injected into an IC lead through the third tip.
In preferred embodiments, the probe features a contact element resil-
iently biased in a rest position with a portion of itself spaced from a support
and movable to an operating position against the support, the
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element tips being coplanar in the operating position; the probe features
contact elements having end portions oblique to an axis of the support and
having peripheral edges at their ends ~or contacting the lead wi-th the axis
parallel to the lead; and two L-shaped torsion spring contact elements and
one beam spring c3ntact element are mounted in grooves in the support.
We turn now to a description of the circuitry and operation of a
preferred embodiment of the invention, in conjunction with the accompanying
drawings, in which:
Figure 1 is an isometric view of the probe, broken away, with an
enlarged portion shown in Figure lA.
Figure 2 is an enlarged view, partly in section, of the front end
of the probe pressed against an integrated circuit lead part of which is
broken away.
Figure 3 is a block diagram showing the probe in conjunction with
signal processing circuitry.
Figures 4-6 are schematics of detailed circuitry used in the
embodiment of Figure 3. Conventional electrical symbols are used, and points
electrically in common are indicated by letters enclosed in circles.
Figure 7 is a schematic of the circuit used to drive the relays
of Figures 3-6.
Figure 8 is a schematic of the power supply filter circuitry.
Figure 9 is a diagrammatic view illustrating how the internal
resistance of an integrated circuit may be determined.
Figure 10 is a flow diagram illustrating the operation of a
preferred circuit analysis system including the embodiment of Figure 3.
Figure 11 is a block diagram of another embodiment.
Figure 12 is a block diagram of another embodiment.
Figure 13 is a diagrammatic view of an alternate probe.
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.
Probe
Referring to Figures 1 and 2, probe 10 has Lexan ~trademark) support
12 forming handle 14 and tapering along axis 15 to portion 16 which is 0.13
inch wide and 0.25 inch long. Portion 16 has reinforcing ridge 18 on its back,
which may be cut off if necessary le.g., to fit between adjacent integrated cir-
cuits) and standoffs 20 and 22 extending 0.010 inch from its end. Support 12
has L shaped grooves 24 and 26 and straight groove 28 extending from sockets 30,
32, and 34 to portion 16, with groove 24 extending to and across the end of the
support. The short leg of groove 26 is spaced 0.030 inch from the short leg of
groove 24 and the end of groove 28 is spaced 0.030 from the short leg of groove
26. The grooves are 0.015 inch wide and 0.015 inch deep over most of their
length with rounded bottoms, and decrease in depth across the short legs of
grooves 24 and 26, and over the last 0.17 inch of groove 28, to zero at their
ends. The grooves are interrupted, between the sockets and portion 16, by rec-
tangular recess 29. Lexan retainer 36, which has recess 37 identical to and op-
posite recess 29, and Lexan cover 38, are screwed to support 12.
Torsion springs 40 and 42 and beam spring 44 ~each of 0.015 inch
cupro-nickel wire) are mounted in block 45, which in turn is fitted into re-
cesses 29 and 37, so that the springs lie in grooves 24, 26, and 28. The springs
are bent at 90 to fit into sockets 30, 32, and 34, which are standard lead
sockets (e.g., AMP, Inc. No. 331810). Wiring cable 52 [containing cables 102
and 104 and wires 45, 48, and 51 shown more particularly in Figure 3) is con-
nected to the sockets and the wires pass between support 12 and cover 38 to ex-
ternal circuitry, being anchored in place by conventional strain relief measures
(e.g., tie-straps passing through holes in support 12 and around the wires).
The springs, as shown in Figure 2, are longer than the grooves so that ends of
the springs cannot be pressed below the surface of portion 16 and contact tips
1~5~566
54, 56, and 58, formed by the circumferential edges of the springs, will in use
(as explained below) contact integrated circuit lead 60. The tips are equally
spaced 0.030 inch apart and, when the tips are fully depressed by the lead 60
~Figure 2), are coplanar and in a straight line. Ends 62, 64, and 66 of the
springs form 30 angles with the face of portion 16 when not depressed. Ends
62 and 64 are each 0.06 inch long (centerline distance), end 66 is 0.17 inch
long. Shafts 68, 70, and 72 generally extend along axis 15. Shafts 6B and 70
are 0.75 inch long, and shaft 72 is 0.64 inch long. Thus, all three springs
have conductive paths of equal length and resistance. The overall probe is 5"
long.
Circuitry
Referring to Figure 3, inputs are provided to probe 10 by test signal
generator 73 and 10 KHz generator 74, whose ~ output 76 is connected directly
to tip 56 through wire 48 and whose - output 78 is connected, as is output 80
of generator 73, to tip 54 through wire 45 or to tip 58 through wire 51, by
DPDT switch 84.
Generator 73 has selectable, positive and negative, 1 KHz square wave,
and dc, current outputs at 0.1, 1.0, and lOma. Referring also to Figure 4, out-
put 80 of generator 73 is provided by positive and negative current gates 86
and 88, which receive inputs from positive and negative current generators 90
and 92, and 1 KHz oscillator 96 and from computer 98 inputs 142.
Test outputs from probe 10 are provided to computer 98 through SPDT
switch 100 along one path consisting of cables 102 and 104, DPDT measurement
select switch 106, transformer 108, amplifier 110, filter 112, and synchronous
detector 114; and along another path comprising input 115 of switch 84 and-am-
plifier 116.
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Cables 102 and 104 are twisted, individually shielded pairs with, as
shown, tips 54 and 56 connected to s~itch 106 by, respectively, wires 46 and 47
of cable 102, and tips 56 and 58 by, respectively, wires 49 and 50 of cable 104.Thus wires 47 and 49, which connect tip 56 and switch 106, are carried separate-ly as one of the wires in the twisted pair in each cable. This cable construc-
tion reduces cross talk and noise pickup.
Switches 84, 100, and 106 are shielded relays. The coil of switch 106
is connected to ground to reduce coil noise in the relay. Transformer 108 is
individually h~u metal shielded, and has a turns ratio of 6:3000; input winding
118 is made of coaxial cable with the outer shield grounded to provide an elec-
trostatic shield. Further shielding is provided by placing elements 106, 108,
110, 112, i34, and 136 together in a Mu metal box, and by filtering the supply
voltages to this circuitry.
Amplifier 110 is a high speed i~npendance matching buffer having an in-
put impedance of greater than 10 Meg ohms and a gainband with product of 6 MHz.
Filter 112 is a bandpass filter centered on 1 KHz and having a bandwidth of 100
Hz.
Detector 114, which functions as a phase sensitive bandpass filter
centered on 1 XHz with a bandpass of 4 Hz, has one signal path from buffer am-
plifier 120 directly to summing point 122 and another through inverter 124 and
chopper 126, which is clocked by the test signal through level shifter 128. The
signal then goes through averager 130 to switch 100. Level shifter 128 shifts
output 80 from a floating test signal to a ground referenced clock.
Amplifier 116 is a dc amplifier with a gain of 1/2.
Probe placement signals are provided to indicator 131 and, through
latch 132, to computer 98 (to confirm that the three contact tips are making
electrical contact with the lead) by gate 133, which has inputs from amplifier
~525~i
110 through 10 KHz detector 134 and 1 KHz comparator 136 which, in turn, re-
ceives inputs from winding 118 and generator 73.
Outputs 138, 140, 142, 144, and 146 from computer 98 control the cir-
cuitry sho~n in Figure 3.
The following table contains the circuit components used in the cir-
cuitry shown in Figures 4-8, except for resistors and capacitors, whose values
are given in Figures 4-8. All resistors are 5%, 1/4 watt carbon resistors un-
less otherwise noted. All capacitors are standard, commercial capacitors;
those with values between 1.6nf and 10nf are film capacitors, those with values
between 33pf and 200pf are mica capacitors, those with values between .01uf and
.22uf are ceramic capacitors, and those with values between 15uf and 390uf are
tantalum capacitors.
Component Table
Ul oscillator, Motorola, Inc. K1114A 10MHz
U2-U5 SN74LS192
U6, U7 SN74LS74
U8-U14, U22-U24 SN74LS02
U15-U20 SN74LS04
U21, U25, U26 SN74LS38
Al-A10, A12, A14-A18 operational amplifier, LM201A
All operational amplifier, LM311
A13 operational amplifier, LM218
Dl-D5, D7, D9-D24, D27 Fairchild, Inc. FDH6626
D6, D8, D25, D26 IN5060
Zl-Z3 6.2v Zener, IN828A
Xl, X2 stabistor, General Electric Corp. STB722
Zl-Q3, Q13, Q18, Fairchild, Inc. S39395
Ql9,
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Component Table Cont'd
Q10-Q12, Q15, Q17, Q20 Fairchild, Inc. S39394
Q7-Q9, Q14, Q27 Motorola, Inc. SS557
Q4-Q6, Q16, Q23-Q25 General Electric Corp. X32D6880
Q21 4 ampere Darlington, 2N6036
Q22 4 ampere Darlington, 2N6039
Q26 FET, 2N4416
TRl-TR4 Selected resistors, 50K-150K
Kl-K3 Relay, General Electric Corp. 3SCV5004Dl
Tl, TZ Custom Choke, 350UH
Transformer 108 6:3000 Transformer; Arnold, Inc.
#6T-5651-Hl ferrite tape core; primary
made of 6 turns 50 ~ coaxial cable with
shield grounded.
In the embodiment of Figure 11, probe 300 has two measuring tips 302
and 304, each having a Kelvin-related forcing tip 306, 308, making contact with
lead 310 of IC 311 on both sides of lead segment resistance 303. Tips 306 and
308 are connected to the output of ac test signal generator 312 through switch
314 which is controlled by the output of switching generator 316. Tips 302 and
304 are connected to the input of synchronous detector 318, which receives a
clock input from generator 312, and the output of detector 318 is applied to
synchronous detector 320 which receives a clock input from generator 316, to
provide dc output 322.
In the embodiment of Figure 12, probe 400 has three tips 402, 404 and
406, equally spaced 0.050 inch apart. Each tip is a resilient, cantilever
spring, bent through a 45 angle, and sharpened to contact lead 408 of IC 410
with their points. The tips are, in the rest position, coplanar with their
points lying in a straight line. Test current source 412, which provides a
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200ma dc test current, is selectively connected to tip 402 or 406 through
switch 414. Measurement circuitry 416, for measuring the voltage between tips,
and monitoring circuitry 418, for monitoring the electrical contacts between
the tips and lead 408, are connected through switch 414 to, respectively, tips
404 and 406 or tips 402 and 404. Circuitry 416 includes sampling relay 420,
transformer 422, and voltage measuring circuit 424, and circuitry 418 includes
pulse generator 426 and pulse detector 428, all of which are controlled by tim-
ing generator 430.
Figure 13 shows an alternate probe with two measuring tips 502 and
504, spaced 0.050 inch apart and a current forcing tip 506 spaced 0.010 inch
outboard of tip 504. Each tip is a rigid needle, and the tips are coplanar
with their points lying in a straight line. If used in the system of Figure 12
~eliminating switch 414), this probe will contact the straight portion of the
IC lead with all three tips simultaneously.
Operation
Referring to Figures 1-3, with normal operating voltages applied to
the board being analyzed, probe tips 54, 56, and 58 are placed against lead 60
of integrated circuit 148 to be tested, with standoffs 20 and 22 resting against
the board and straddling the meniscus of the solder joint between the lead and
the board land. The tips are thus positioned along the straight lead portion
between the meniscus and the curve of the lead into the integrated circuit.
Probe 10 is then moved toward the lead until the springs bottom out against sup-
port 12, bringing the tips into a straight line equally spaced 0.030 inch apart~
so the resistances of lead segments 147 and 149 between the tips are equal. In
being pressed down, the tips dig into and slide along the lead surface, scraping
corrosion from the lead and insuring good electrical contact. The deviation of
tip 54 toward tips 56 and 58, as the probe is pressed against the lead, is neg-
ligible (particularly as a very slight amount of upward play is provided between
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shaft 72 and retainer 36, and the shaft thus bends up slightly to accommodate
any tendency of tip 54 to move towards the other tips), and tips 56 and 58 ro-
tate in planes parallel to tip 54, thereby maintaining the tips at the desired
equal spacing even as the tips wear and increase their contact areas during re-
peated use. Grooves 24, 26, and 28 positively maintain the lateral position of
the tips, contributing to accurate tip spacing.
In the presently preferred embodiment, four testing steps are then
carried out under the control of computer 9S acting through control inputs 138-
146, without physically moving the probe.
In the first step, the voltage normally appearing at tip 58 is mea-
sured, with no test current being injected into the lead, by connecting the in-
put of amplifier 116 to tip 58 through switch 84 and the output of the amplifier
to computer 98 through switch 100. The voltage measured is converted into a
digital number within the computer by an analog to digital converter (not
shown).
In the second step, a dc test current is injected into the lead
through tip 58 by generator 73, and, again through amplifier 116, a measurement
is made of the resulting voltage appearing at tip 58. Referring to Figure 4,
the polarity ~i.e., into or out of tip 58) and magnitude ~i.e., 10, 1, or O.lma)
of the test current is selected by control inputs 142. The polarity and magni-
tude of the current are selected, depending upon the type of element being ana-
lyzed, the signal normally present on the lead, and the total resistance appear-
ing on the node, to not disturb the normal operation of the circuit. E.g., if
5400 series logic circuits are being tested, the current would typically be lma
or lOma.
In the third step, the probe outputs from tips 54 and 56 are con-
nected, through switch 106, to winding 118, and the output of detector 114 is
connected through switch 100, to computer 98. An ac test current is injected
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into the lead through tip 58 by generator 73 (again selected (10, 1, or O.lma)
not to disturb the operation of the circuit), and the voltage appearing between
tips 54 and 56 due to test current flowing into the integrated circuit through
the resistance of lead segment 147 is measured.
The ac voltages appearing between the tips in step 3 (as well as in
step 4 described below) typically range from 30 nv to 10 ~v, and the noise pro-
tection features previously discussed, i.e., the shielding of the relays and
the circuitry, the twisting and shielding of the cabling, and the construction
of transformer 108, together with the circuitry filtering the supply voltages
and the grounding of one end of the switch 106 coil, allow these voltages to be
accurately measured. Accuracy of the ac measurement is also enhanced by the
use of an ac test signal and the specific sequence of transformer 108 as a high
gain, low noise amplifier providing common mode noise rejection; high speed am-
plifier 110 to amplify both the test signal and noise, without substantial band
limiting, to useful levels without distortion which would confuse the character-
istics of each; filter 112 to reduce noisé in preparation for synchronous detec-
tion; and synchronous detector 114, which effectively eliminates from the mea-
surement signal all components not identical in frequency and phase with the in-
jected test signal. Average 130 converts the measurement signal into an inte-
grated dc voltage proportional to the 1 KHz component of the measurement sig-
nal. The gain-bandwidth product of amplifier 110 is preferably greater than 5
MHz. The bandwidth of filter 112 is selected to be as narrow as possible,
preferably no more than 10% of the center frequency, insuring that the 1 KHz
test signal falls within the 3 db points of the passband as the passband drifts
with age and temperature. The bandwidth of detector 114, which is determined
by averager 130, is selected to be as narrow as possible while not requiring an
excessive waiting period for the measurement, and is preferably less than 15 Hz.
In the fourth step, the probe outputs from tips 56 and 58 are con-
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nected, through switch 106, to winding 118, and tip 54 is connected, through
switch 8~, to generator 73. The ac test current is injected into the lead
through tip 54, and the voltage appearing between tips 56 and 58 due to the
test current flowing away from the integrated circuit through the resistance
of lead segment 149 is measured.
In each of the four test steps, the placement of probe lO against the
lead is monitored by two independently operating circuits ~described below) to
insure proper electrical contacts ~i.e., with resistances less than 0.10 ohms)
between the three tips and the lead.
In the first monitoring circuit, output 76 of 10 KHz generator 74 is
connected directly to contact tip 56 while output 78, which is phase shifted
180 with respect to output 76, is connected through switch 84 to tip 54 during
steps 1-3 and to tip 58 during step 4. If, during each test step, the two tips
connected to generator 74 are both making proper electrical contact with the
lead, both outputs will be present in the lead and will cancel each other; if
one of the tips is not making proper contact, only one output will be present
and, being uncancelled, will pass through the probe output to 10 KHz detector
134, which will trigger latch 132, through ORing gate 133, to generate an alarm
output to computer 98. The latch stores the fact of a probe placement error un-
til released by acknowledgement output 146 from the computer. The output of
gate 133 is provided directly to indicator 131, located on probe 10, without
being stored.
In the second monitoring circuit, one input of comparator 136 is con-
nected through switch 84, to tip 58 during steps 1-3 and to tip 54 during step
4, while the other input is connected, through switch 106, to tip 56 during
steps 1-3 and to tip 58 during step 4. If, during each test step, the tips con-
nected to the comparator inputs are both making proper electrical contact with
the lead, the same signal will be present on both inputs ~i.e.~ the signal due
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to normal operation of the circuit, the test signal, if any, and any uncancelledoutput from generator 74); if either tip is not making proper contact, the in-
puts to the comparator will differ and, if they differ by more than 0.10 volts,
comparator 136 will trigger the latch through gate 133, again providing an indi-
cation at the probe.
During test steps 1-3, therefore, the first monitoring circuit checks
tips 54 and 56 and the second circuit checks tips 56 and 58, while, during step
4, the first checks tips 56 and 58 and the second checks tips 54 and 56.
The measurements made in the fourth test steps yield information, re-
lating to the internal resistance of integrated circuit 148, which, as describedbelow, is useful in diagnosing and locating faults in the circuit board. Be-
cause the tests do not disturb the normal operation of the board, faults which
are best detected ~and in some cases can only be detected) under normal opera-
tion conditions (i.e., with normal operating power applied to the board) can be
identified: e.g., resistors and capacitors whose values change, capacitors
which leak, relays and switches which have excessive contact resistance under
normal operating voltages, transistors or integrated circuits having insuffi-
cient gain or excessive leakage currents, and failed transistors, internal to
an integrated circuit, which cause the input or output transistors of the inte-
grated circuit to appear to be open or short circuited.
Figure 9 illustrates one general approach to determining the internalresistance of integrated circuit 148. Resistance Rl represents that internal
resistance while R2 represents the combined, parallel internal resistances of
all other ICs connected to the same node ~i.e., a point within a circuit common
to two or more IC inputs and outputs) as lead 60. l~hen test current I is in-
jected into lead 60 through contact tip 58, component Il will flow into Rl and
component I2 into R2, causing voltage Vx to appear at tip 58, vhere Vx~Il x
Rl~12 x R2, and Rl can be determined if Vx and Il are known. Where a voltage
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is normally present on lead 60, e.g., the normal operating voltage of the cir-
cuit, Vx is found by first measuring the voltage at tip 58 without injecting
the test current and then measuring the voltage while injecting the test cur-
rent, i.e., the first and second test described above; Vx is the difference be-
tween the two measurements ~i.e., the voltage due to the injected test current).Il is determined from the equation Il = Vl/R147 where Vl is the voltage appear-
ing between tips 54 and 56 due to Il flowing into Rl through R147, the resis-
tance of lead segment 147. Vl is determined from the change in the voltage be-
`tween tips 54 and 56 due to the injection of the test current, as in the first
and second test steps, or by injecting an ac current at a known frequency ~e.g.,as in step 3) and detecting the voltage appearing between tips 54 and 56 at thatfrequency. If R147 is known Vl may be calculated.
However, by using information from all four test steps, one can avoid
having to know the resistances of lead segments 147 and 149 ~which may vary overa range of ten to one, depending upon the lead material). The total resistance
appearing at probe 10 (i.e., the parallel combination of Rl and R2) is deter-
mined from the information gained in the first and second test steps by solving
the equation Rt = Vx/I; where I is the test current ~i.e., I = Il ~ I2); Vx is,
again, the difference between the voltages appearing at tip 58 due to the injec-tion of the test current, and Rt = ~Rl x R2)/~Rl + R2). Because R147 and R149
are equal, due to the geometry of contact tips 54, 56, and 58, the equations
Vl = Il x R147 and V2 = I2 x R149 may be solved to give Il/I2 = Vl/V2. Vl is
determined during the third test step by measuring the voltage appearing betweentips 54 and 56 due to Il with the test current injected through tip 58, and V2
is determined during the fourth test step by measuring the voltage appearing be-tween tips 56 and 58 due to I2, with the test current injected through tip 54.
Applying the law of current division through parallel resistances ~i.e., I di-
viding to become Il through Rl and I2 through R2), Il and I2 are expressed as
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,~
~5256Çi
Il-(I) (R2)/Rt and I2~(I) ~R1)/Rt, which gives the relationship Il/I2 = R2/Rl,
and, applying the relationship Vl/V2 = Il/X2, R2/Rl = Vl/V2. Therefore, by
finding Vl, V2, and Vx, and knowing I, the equations Rl/R2 = V2/V1 and Rt =
(Rl x R2)/(Rl + R2) may be solved to find Rl and R2 without requiring that the
resistances of lead segments 147 and 149 be known.
In the most preferred approach, illustrated in Figure 10, the value
of the total parallel resistance present at the probe (Rt), the ratio between
the internal resistance of the integrated circuit (Rl) and the total parallel
resistances of all other ICs connected to the node (R2), and the values of Rl
and R2, are used to locate faults in the board.
If a circuit node is suspected of having a failed integrated circuit
connected to it, the operator places probe 10 on the lead of the IC sclected as
most probably being failed, usually the lead connected to the IC circuit driving
(i.e., providing a signal to) the node, if that output is known, and normal op-
erating voltages are applied to the circuit board.
The first stage in the circuit analysis determines whether there is at
least one effective, active driving circuit connected to the node. The majority
of circuit nodes have one or more driving circuits connected to them and one or
more load, or input, circuits. The internal resistance Rd of a driving circuit
is typically much less than that of an input circuit (e.g., for T~L or ECL logic
circuits a driving resistance is 130 ohms while a load resistance is 1.3K ohms),
so that driving and input circuits can be distinguished through their internal
resistances.
In the first stage, computer 98 directs the circuitry of Figure 3 in
carrying out all four test steps described earlier to determine the total paral-
lel resistance (Rt) appearing at the lead and the ratio between Rl and R2 and,
from these, solves for Rl and R2. The computer then selects the smaller of Rl
or R2 and compares that value to a number K which is selected to be equal to or
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i
-.
~ 2566
slightly greater (to allow for tolerance in the resistance) than the driving
resistance ~e.g., K = 200 ohms for TTL or E.CL logic). Since R2 is the total
parallel resistance of all other ICs connected to the node, it may or may not
include an active driving circuit; e.g., if R2 consists of N or more load resis-
tances, where N is equal to the ratio between a load and a driving resistance
(e.g., N = 10 for TTL and ECL logic), then R2 may be less than K. This case is
not considered, however, as good design practice requires that no driving cir-
cuit` be loaded with such an extreme number of input loads.
If neither Rl nor R2 is less than K, the fault most probably lies with
the IC containing the driving circuit for the node, i.e., there is no active
driving circuit present on the node. The computer indicates that this is the
fault and the IC containing the driving circuit must then be located. e.g., by
referring to circuit diagrams. If an active driving circuit is found ~i.e.,
either Rl or R2 is less than ~), the fault is most probably not a failure of the
driving circuit (e.g., an open circuit) but is a failure in an input circuit,
and it is necessary to apply more sophisticated criteria to determine the prob-
able location of the fault, by proceeding to the second analysis stage.
The second stage of the analysis determines whether the fault is a
shorting resistance between an IC input circuit and the internal supply voltage
of the IC (e.g., in TTL and ECL logic circuits, a shorting resistance to the in-
ternal 1.2 volt threshold voltage of the ICs holding the voltage appearing on
the node below 1.& volts, the logic 0 to logic 1 threshold voltage) by determin-
ing whether the ratio Rl/R2 is outside a range bounded by the ratio of Rs (as
defined below) to Rd, and the reciprocal Rd/Rs. For TTL and ECL logic, the pre-
ferred bounds are 0.2 and 5Ø Rs is selected by determining, for each possible
configuration of shorting resistance, the maximum value that this resistance
could assume and still effectively cause the fault symptom to appear. In gen-
eral, a ~ 20% range around each bound for the range will give useful results.
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6~
It was determined in the first stage that there is an active dTiving
circuit present on the node, so that, e.g., for TTL and ECL logic, the maximum
value of shorting resistance is less than 1/5 of the driving resistance (1/5 of
130 ohmsJ or 26 ohms) if the node voltage is being held below 1.8 volts. If the
fault is located at Rl, the driving resistance will be part of R2 and R2 will be
equal to or less than the driving resistance ~e.g. 130 ohms) so that the ratio
Rl/R2 (26/130) will be less than 0.2. If the fault is located within R2, R2
will be equal to or less than the value of the shorting resistance ~26 ohms) and
Rl will be greater than or equal to a driving resistance ~130 ohms), so that the
ratio Rl/R2 ~130/26) will be greater than 5Ø
Rs is preferably determined by applying conventional circuit analysis
techniques, i.e.~ determining the actual input and driving circuits in the type
of ICs of interest ~e.g., by reference to a manufacturer's product catalog);
assuming a circuit having one driving circuit driving the maximum allowable num-
ber of input circuits; assuming a shorting resistor of unknown value connected
between the input and the internal supply voltage in one driving IC; applying
Thevenin's and Norton's equivalent circuit analysis to obtain a set of equations
relating Rs to the characteristics of the assumed fault; and solving the equa-
tions to find Rs.
In the shortened~ approximation approach typically applied in the en-
gineering field, such an analysis would appear as follows:
Referring, e.g., to the circuit of an SN5400 two input NAND gate shown
on pages 3-6 of the Texas Instruments, Inc. TTL Data Book for Design Engineers,
Second Edition, it is assumed that the multi-emitter input transistor has failed
so that there appears to be a shorting resistor ~Rs) connected between, e.g.,
input A, and the collector of that transistor. Because this collector is held
at two diode forward voltage drops above ground ~through the base-emitter diodes
of the transistor whose base is connected to the collector of the input ~ransis-
- 20 -
::
~5256~
tor, and the transistor whose base is connected to the emitter of that second
transistor), this shorting resistor appears to be connected between input A and
a 1.2 volt internal supply voltage. The output of the gate appears as a 130 ohm
resistor ~Rd) and a diode in series connected to the 5 volt external supply
voltage to the gate when the gate output is trying to raise the node voltage to
a logic "1" (i.e., 1.8 volts). The equivalent circuit thus appears as a series
connection of a 130 ohm resistor and an unknown shorting resistor (Rs), connect-
ed b`etween a 4.4 volt level (5.0 volts minus a .6 volt diode drop) and a 1.2
volt level. The voltage Vn at the junction between the resistors ~i.e., the
node) is thus given by the equations below, where Rs is the value of the short-
ing resistance.
Vn = 1.2v + Rs x~4.4v - 1.2v)
(130 ~ + Rs)
The equation is solved to find Rs for a Vn of 1.8 volts, and Rs is found to be
26 Q, or 0.2 times the 130 ~ driving resistance Rd.
If, there~ore, the computer finds that the ratio Rl/R2 is less than
0.2 or greater than 5.0, the fault is most probably located in the smaller of Rl
and R2, which smaller value contains the shorting resistance (e.g., 26 ohms).
Thus, if Rl is smaller than R2, the computer indicates that the fault has been
located. But if R2 is greater than Rl~ the operator goes to the next lead on
the node (unless he is already at the last lead, in which event the computer in-
dicates that all ICs are good), and repeats stage two.
If the ratio Rl/R2 lies within the limits 0.2 to 5.0, all of the in-
ternal resistances (Rl) on the node are large enough, compared to the driving
resistance, that the fault is most probably not an internal shorting resistance
between the IC input and the internal supply voltage and further criteria must
be applied.
The criteria used in the third stage of the analysis are based upon
6~i
the difference between the voltage actually present on the node and a known
voltage expected to be present if there were no fault. If the voltage present
is some intermediate level (e.g., between a logic "0" and a logic "1") and
should be low (e.g., a iogic "0"), i.e., the driving circuit is attempting to
pull the node voltage down to logic "0" but cannot, then the fault most probably
appears as a shorting resistance higher than the driving resistance between an
IC input and the supply voltage to the IC (e.g., +5 volts for TTL and ECL logic
If Rl is this shorting resistance, Rl will be greater than R2, which contains
the driving resistance, and the computer will so find and indicate the fault has
been located. If Rl is not greater than R2, the operator goes to the next lead
on the node and the test procedure begins again with the second stage, except
that the computer will indicate that all IC's on the node are good if the probe
is on the last lead to be tested.
If the voltage present is at a low or intermediate level (e.g., at
logic "0" or between logic "0" and a logic "1") and should be high (e.g., at a
logic "1"), i.e., the driving circuit cannot pull the node voltage up to a logic
"1", then the fault appears as a low valued shorting resistance (compared to a
driving resistance) between an IC input and ground. Thus, if Rl is less than
R2, which again contains the driving resistance, the computer will so find and
indicate the fault has been located. If Rl is not less than R2, the operator
goes to the next lead and the test begins again with the second stage, except
that the computer will indicate that all IC's in the node are good if the probe
is on the last lead to be tested.
If, however, the voltage present on the node is high and should be low
(e.g., a logic "1" and should be a logic "0"), the fault is not a high resis-
tance short to the IC supply voltage or a low resistance short to ground, but
some intermediate value of resistance and it is necessary to apply an Rl/R2 ra-
tio criterion, as was applied in the second stage of the analysis. The criteri-
- 22 -
~I~SZ5~
on was determined in the same manner as in the second stage; assuming some con-
figuration of shorting resistance, determining the range of allowable values of
resistance for each configuration that would cause this fault to appear and,
from this, determining the corresponding ranges for the ratio Rl/R2. I.e., the
shorting resistance can be part of either Rl or R2, and the other of Rl or R2
will be equal to or less than the driving resistance, as discussed in the sec-
ond stage, so that the shorting resistance is limited to be less than 60% of the
driving resistance, i.e., the ratio Rl/R2 will be between 0.6 and 1.6. If the
ratio lies in the range of 0.6 to 1.6, the fault is most probably a shorting re-
sistance larger than a driving resistance and, if the ratio lies outside the
range 0.6 to 1.6, the fault is most probably a shorting resistance smaller than
a driving resistance. The computer respectively determines whether Rl is
greater or less than R2 and, if this test is positive, indicates the fault
_ 23 -
5~
- located. If the tes~ is negatiYe, then, as. described above, the
operator elther goes to the n~xt lead or the computer indicates
that all IC's on the node are good.
Conventional programming techn~ques can be used to
adapt the flow chart of Figure 10 to an available computer. The
preferred embodiment, using the Teradyne M365C computer,
incorporates circuit path tracing and other features found in the
Teradyne'Li25 Ci,rcui.t Diagnostic System, ~or locating a faulty
node prior to practice'of the pres'ent invention.
In the embodiment of Figure 11, ac test current at
frequency fl from test signal generator 312 is injected into
lead 310 through'switch 314 and tips 306 and 308 alternatelyO
The alternation ~etween the forcing tips is at a rate f2, less
than fl and controlled by th.e output of swi.tchin.g ge.nerator 316.
Voltages mutually phase shifted by 180.thus appe~ alternately
between tips 302 and 304 due to the components of test current
~lowing alternately from tip 308 into resistance Rl of IC 311
and from tip 306 away from Rl and into R2, the combined parallel
resistance of the other ICs on the node. The voltages are
20. applied to the inputs of synchronous detector
-24-
66
318, to provide a square wave output at frequency f2, wherein the magnitudes of
the positive and negative swings of the square wave represent the voltages due
to the test current components flowing into and way from Rl. The output of de-
tector 318 is then synchronously detected by detector 320 to provide dc output
322 whose magnitude represents the ratio Rl/R2 and whose sign indicates which isthe larger, e.g., a positive output indicating Rl is greater than R2 and a neg-
ative output indicating Rl is less than R2. The embodiment shown in Figure 11
thereby determines the ratio Rl/R2 in one combined measurement s~ep, wherein themeasurements are made across a single segment of lead 310, and without having toknow the value of resistance 303.
In the embodiment of Figure 12, probe 400 is placed against the lead
of the IC with the cantilever springs of the probe tips allowing tips 404 and
406 to contact the straight portion of the lead and tip 402 to go around the
bend on the lead. (In some ICs, the straight portion of the lead may be long
enough to accommodate all three tips. But, unlike the case for the embodiments
of Pigures 1-lO, in this embodiment the inequality in lead segment length re-
sulting from having the lead bend in one segment while the other segment is
straight does not affect test accuracy because only orders of magnitude, not
specific values, are being measured). Tip 406 is selected as an injection tip
and connected, through switch 414, to source 412) and a 200 ma dc test current
is injected into the lead. The voltage appearing between tips 402 and 404 due
to test current flowing into the internal resistance of the IC is applied to
measurement circuitry 424 through relay 420 and transformer 422, with the relay
alternately reversing the polarity of this voltage at the input to the trans-
former, so that the voltage at the transformer input appears as a square wave
signal. Measuring circuitry 424 takes a measurement during each half-cycle of
this square wave (thus cancelling any internal offset in the measuring circuit-
ry), and generates output 432 to provide a general indication of the current
- 25 -
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566
flowing into the IC. The presence of a substantial current flow where none was
expected would indicate a short (i.e., too low an internal resistance) in the
IC. Alterna*ively, tip 402 can be selected as the injection tip and tips 404
and 406 as the measuring tips to provide a general indication of whether there
is a short on the side of the probe away from the IC.
The placement of the probe tips is monitored, during alternate half
cycles, by injecting a pulse from generator 426 into the measurement tips at
the start of the half cycles; if the measurement tips are effectively shorted
together through the lead, the pulse is reflected and detector 428 detects the
reflected pulse to provide an indication that the tips are making proper con-
tact.
The two measuring tips and measuring circuitry 416 may be used alone
to gain useful information relating to the condition of IC 410 by applying oper-ating voltages to the circuit board and exercising the IC (i.e., by applying
changing input signals to cause a change in the output at lead 408). The change
in voltage between the measuring tips due to the change in the normal operating
current flowing in lead 408 can be compared to that known to appear if IC 410 isnot faulty.
If the probe of Figure 13 is used, any injected test current must go
through tip 506, which is too close to tip 504 to serve as a measuring tip.
Other embodiments are within the following claims. E.g., contact
springs 208, 210, and 212 of the probe might preferably be made from wire havinga square cross-section, with the contact tips formed at a corner of the cross-
section rather than by a curved edge as appears in the present embodiment, pos-
sibly further reducing the rate at which tip contact area increases with wear,
and providing a sharper tip to dig into the lead.
Further by way of example, in connection with the three stage diagnos-
tic procedure, useful information can be obtained by carrying out stage three
- 26 -
~s~
directly after determining whether an active drive is present, and even by omit-ting the ratio comparison branch of stage three, although such a procedure
yields a less reliable diagnosis.
~'
