Note: Descriptions are shown in the official language in which they were submitted.
1~5~4~ Case 556.2
The present invention relates to a thin film,
field effect transistor, and more specifically to a
thin film, field effect transistor of the type
formed from an amorphous alloy including at least
silicon and fluorine. In this respect, reference
is made to U.S. Patent No. 4,217,374 Stanford R.
Ovshinsky and Masatsugu Izu entitled: AMORPHOUS
SEMICONDUCTORS EQUIVALENT TO CRYSTALLINE SEMI-
CONDUCTORS and U.S. Patent No. 4,226,898 Stan-
ford R. Ovshinsky and Arun Madan, of the sametitle.
Silicon is the basis of the huge crystalline
semiconductor industry and is the material which is
utilized in substantially all the commercial inte-
grated circuits now produced. When crystallinesemiconductor technology reached a commercial state,
it became the foundation of the present huge semi-
conductor device manufacturing industry. This was
due to the ability of the scientist to grow sub-
stantially defect-free germanium and particularly
silicon crystals, and then turn them into extrinsic
materials with p-type and n-type conductivity re~
gions therein. This was accomplished by diffusing
into such crystalline material parts per million of
3~
donor (n) or acceptor (p) dopant materials intro-
duced as substitutional impurities into the sub-
stantially pure crystalline materials, to increase
their electrical conductivity and to control their
being either sf a p or n conduction type.
The semiconductor fabrication processes for
making p-n junction cyrstals involve extremely
complex, time consuming and expensive procedures as
well as high processing temperatures. Thus, these
crystalline materials used in transistors and other
current control devices are produced under very
carefully controlled conditions by growing indi-
vidual single silicon or germanium crystals, where
p-n junctions are required by doping such single
crystals with extremely small and critical amounts
of dopants. These crystal growing processes pro-
duce relatively small crystal wafers upon which the
integrated circuits are formed.
In wafer scale integration technology the
small area crystal wafer limits the overall size of
the integrated circuit which can be formed thereon.
In applications requiring large scale areas, such
as in the display technology, the crystal wafers
cannot be manufactured with as large areas as re-
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quired or desired. The devices are formed, atleast in part, by diffusing p or n-type dopants
into the substrate. Further, each device is formed
between isolation channels which are diffused into
the substrate. Packing density (the number of
devices per unit area of wafer surface) is also
limited on the silicon wafers, because of the leak-
age current in each device and the power necessary
to operate the devices, each of which generate heat
which is undesirable. The silicon wafers do not
readily dissipate heat. Also, the leakage current
adversely affects the battery or power cell life-
time in portable applications.
In MOS-type circuitry the switching speed is
related directly to the gate length with the small-
est length having the highest speed. The diffusion
processes, photolithogrophy and other crystalline
manufacturing processes limit how short the gate
length can be made.
~0 Further, the packing density is extremely
important because the cell size is exponentially
related to the cost of each device. For instance,
a decrease in aie size by a factor of two results
in a decrease in cost on the order of a factor of
six.
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~3~B~
In summary, crystal silicon transistor and
integrated circuit parameters which are not vari-
able as desired, require large amounts of material,
high processing temperatures, are only producible
only on relatively small area wafers and are expen-
sive and time consuming to produce. Devices based
upon amorphous silicon can eliminate these crystal
silicon disadvantages. Amorphous silicon can be
made faster, easier, at lower temperatures and in
larger areas than can crystal silicon.
Accordingly, a considerable effort has been
made to develop processes for readily depositing
amorphous semiconductor alloys or films each of
which can encompass relatively large areas, if
desired, limited only by the size of the deposition
equipment, and which could be doped to form p-type
and n-type materials to form p-n junction tran-
sistors and devices superior in cost and/or opera-
tion to those produced by their crystalline coun-
terparts. For many years such work was substan-
tially unproductive. Amorphous silicon or germa-
nium (Group IV) films are normally four-fold co-
ordinated and were found to have microvoids and
dangling bonds and other defects which produce a
3~
high density of localized states in the energy gap
thereof. The presence of a high density of local-
ized states in the energy gap of amorphous silicon
semiconductor films resulted in such films not
being successfully doped or otherwise modified to
shift the Fermi level close to the conduction or
valence bands making them unsuitable for making p-n
junctions for transistors and other current control
device applications.
In an attempt to minimize the aforementioned
problems involved with amorphous silicon and ger-
manium, W.E. Spear and PO G. Le Comber of Carnegie
Laboratory of Physics, University of Dundee, in
Dundee, Scotland did some work on "Substitutional
Doping of Amorphous Silicon", as reported in a
paper published in Solid State Communications, Vol.
17, pp. 1193-1196, 1975, toward the end of reducing
the localized states in the energy gap in amorphous
silicon or germanium to make the same approximate
more closely intrinsic crystalline silicon or ger-
manium and of substitutionally doping the amorphous
materials with suitable classic dopants, as in
doping crystalline materials, to make them extrin-
sic and of p or n conduction types.
8~
The reduction of the localized states was
accomplished by glow discharge deposition of amor-
phous silicon films wherein a gas silane (SiH4) was
passed through a reaction tube where the gas was
decomposed by an r.f. glow discharge and deposited
on a substrate at a substrate temperature of about
500-600K (227-327C). The material so deposited
on the substrate was an intrinsic amorphous mate-
rial consisting of silicon and hydrogen. To pro-
duce amorphous material a gas of phosphine (PH3)for n-type conduction or a gas of diborane (B2H6)
for p-type conduction were premixed with the silane
gas and passed through the glow discharge reaction
tube under the same operating conditions. The
gaseous concentration of the dopants used was be-
tween about 5 x 10-~ and 10-2 parts per volume.
The material so deposited included supposedly sub-
stitutional phosphours or boron dopant and was
shown to be extrinsic and of n or p conduction
type.
While it was not known by these researchers,
it is now known by the work of others that the
hydrogen in the silane combines at an optimum tem-
perature with many of the dangling bonds of the
~1~ r- ~
silicon during the glow discharge deposition, to
substantially reduce the density of the localized
states in the energy gap toward the end of making
the electronic properties of the amorphous material
approximate more nearly those of the corresponding
crystalline material.
D.I. Jones, W.E. Spear, P.G. LeComber, S. Li,
and R. Martins also worked on preparing a-Ge:H from
GeH4 using similar deposition techniques. The
material obtained gave evidence of a high density
of localized states in the ener~y gap thereof.
Although the material could be doped the efficiency
was substantially reduced from that obtainable with
a-Si:H. In this work reported in Philosophical
Magazine ~. Vol. 39, p. 147 (1979) the authors
conclude that because of the large density of gap
states the material obtained is ". . . a less at-
tractive material than a-Si for doping experiments
and possible applications."
The incorporation of hydrogen in the above
silane method not only has limitations based upon
the fixed ratio of hydrogen to silicon in silane,
but, most importantly, various Si:H bonding con-
figurations introduce new antibonding states which
3~
can have deleterious consequences in these mate-
rials. Therefore, there are basic limitations in
reducing the density of localized states in these
materials which are particularly harmful in terms
of effective p as well as n doping. The resulting
density of states of the silane deposited materials
leads to a narrow depletion width which in turn
limits the efficiencies of devices whose operation
depends on the drift of free carriers. The method
of making these materials by the use of only sil-
icon and hydrogen also results in a high density of
surface states which affects all the above param-
eters.
After the development of the glow discharge
lS deposition of silicon from silane gas was carried
out, work was done on the sputter deposition of
amorphous silicon films in the atmosphere of a
mixture of argon (required by the sputtering de-
position process) and molecular hydrogen, to deter-
mine the results of such molecular hydrogen on thecharacteristics of the deposited amorphous silicon
film. This research indicated that the hydrogen
acted as a compensating agent which bonded in such
a way as to reduce the localiæed states in the
--8--
energy gap. However, the degree to which the lo-
calized states in the energy gap were reduced in
the sputter deposition process was much less than
that achieved by the silane deposition process
described above. The above described p and n dop-
ant materials also were introduced in the sput-
tering process tG produce p and n doped materials.
These materials had a lower doping efficiency than
the materials produced in the glow discharge pro-
cess. Neither process produced efficient p-doped
materials with sufficiently high acceptor con-
centrations for producing commercial p-n junction
devices. The n-doping efficiency was below desir-
able acceptable commercial levels and the p-doping
1~ was particularly undesirable since it increased the
number of localized states in the band gap.
Various methods of fabrication and construc-
tion of thin film transistors and devices have been
proposed wherein the various films of the tran-
sistor are made of different materials having dif-
ferent electrical characteristics. For example,
thin film transistors have been proposed utilizing
nickel oxide films, silicon films, amorphous sil-
icon films and amorphous silicon and hydrogen films
formed from silane as above mentioned. Also, vari-
ous geometrical configurations have been proposed
such as a planar-MOS construction.
The prior deposition of amorphous silicon,
which has been altered by hydrogen from the silane
gas in an attempt to make it more closely resemble
crystalline silicon and which has been doped in a
manner like that of doping crystalline silicon, has
characteristics which in all important respects are
inferior to those o~ doped crystalline silicon. As
reported by Le Comber and Spear and others refer~
enced above, in the silane based transistor devices
the leakage current may be as low as 10-11 amperes,
the saturation current appears to be about 5 x 10-6
amperes, the device switching frequency appears to
be about 104 Hz and the stability is poor since the
material degrades with time.
It has been proposed to make a solar cell
which is essentially a photosensitive rectifier
utilizing an amorphous alloy including silicon and
fluorine in the aforementioned U.S. Patent No.
4,217,374, issued 8/12/80 for Amorphous Semicon-
ductor Equivalent to Crystalline Semiconductors,
Stanford R. Ovshinsky and Masatsugu Izu and U.S.
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~.~f~i3~;3q3
Patent No. 4,276,898, issued 10/7/80 of the same
title, Stanford R. Ovshinsky and Arun Madan.
We have found that these disadvantages may be
overcome by providing a thin film, field effect
transistor formed from a silicon, fluorine, and
hydrogen amorphous alloy in various constructions.
These transistors provide very low leakage cur-
rents, fast switching speeds t high OFF resistance:
ON resistance ratios, and do not degrade with time~
We also provide a new and improved V-MOS thin film,
field effect transistor formed from the above amor-
phous alloy.
According to the present invention there is
provided a thin film, field effect transistor hav-
ing a source region, a drain region, a gate insu-
lator, a thin film deposited amorphous alloy in-
cluding at least silicon and fluorine coupled with
the source region, the drain region and the gate
insulator and a gate electrode in contact with the
gate insulator.
Preferably, the amorphous alloy also contains
hydrogen, such as an amorphous alloy a-Sia:Fb:Hc
where a is between 80 and 98 atomic percent, b is
between 1 and 10 atomic percent and c is between 1
and 10 atomic percent.
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The field effect transistor can have various
geometries including a V-MOS like construction of
the invention and can be deposited on various sub-
strates with an insulator between the active re-
gions of the thin film, field effect transistor anda conducting substrate such as a metal. The tran-
sistors can be deposited on an insulator, a semi~
conductor, an insulated metal or an insulated semi-
conductor substrate. Because of the capability to
be formed on various substrates and the low leakage
and operating current, the transistors also can be
formed on top of one another, i.e., stacked.
The thin film, field effect transistor can
have various desirable characteristics depending
upon the particular geometry chosen and thickness
of the film of amorphous silicon fluorine material
chosen such as, for example, a DC saturation cur-
rent as low as 10-6 amperes and up to or greater
than 10-~ amperes, an upper cut off frequency at
least above 10 MHz, a high OFF resistance:ON resis-
tance ratio of about 107, and a very low leakage
current of about 10-11 amps or less. Further, the
alloy does not degrade with time.
The preferred embodiment of this invention
,~0~
will ~t~ be described by way of example, with re-
ference to the drawings accompanying this specifi~
cation in which:
Fig. 1 is a vertical sectional view of one
embodiment of thin film deposited, field effect
transistor made in accordance with the teachings of
the present invention and having metal source and
drain regions similar to a planar MOS-type tran-
sistor.
Fig. 2 is a schematic circuit diagram of the
transistor shown in Fig. 1.
Fig. 3 is a vertical sectional view through a
second embodiment of a thin film deposited, field
effect transistor similar to the transistor shown
in Fig. 1, having semiconductor source and drain
regions.
Fig. 4 is a schematic circuit diagram of the
transistor shown in Fig. 3.
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~,~o~
Fig. 5 is a vertical sectional view of another
embodiment of thin film deposited, field effect
transistor similar to the transistor shown in Fig.
1, having metal source and drain regions similar to
a V-MOS-type transistor.
Fig. 6 is a schematic circuit diagram of the
transistor shown in Fig. 5.
Fig. 7 is a vertical sectional view through a
second embodiment of a thin film deposited, field
effect transistor similar to the transistor shown
in Fig. 5, having semiconductor source and drain
regions.
Fig. 8 is a schematic circuit diagram of the
transistor shown in Fig. 7.
Fig. 9 is a vertical sectional view through a
thin film deposited, field effect transistor, sim-
ilar in function to the transistors shown in Figs.
1-8 but having a different geometrical construc-
tion.
2Q Referring now to the figures in greater de-
tail, there is illustrated in Fig. 1 a thin film,
field effect transistor 10 made in accordance with
the teachings of the present invention. As shown,
the transistor 10 is formed on a substrate 12 of
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~.~.53~
insulating material which could be a silicon mate-
rial, a layer of polymer material or an insulator
on top of a metal. Deposited on the substrate 12
in accordance with the teachings of the present
invention is a thin alloy layer 14 including sil-
icon and fluorine which can also contain hydrogen
and which can be doped to form an N or P type al-
loy. On top of this alloy layer 14 is a layer or
band 16 of insulating material such as a field
oxide and spaced therefrom is another layer or band
18 of insulating material such as a field oxide.
A channel or opening 20 is formed, as by con-
ventional photolithography techniques, between the
two bands 16 and 18. A source metal conductor 22
is deposited over the band 16 with a portion there-
of in contact with the alloy layer 14 to form a
Schottky barrier contact at the interface between
the source metal 22 and the amorphous alloy layer
14.
In a similar manner a conductor or layer 24 of
drain metal is deposited over the insulating band
18 with a portion thereof in contact with the alloy
layer 14 spaced from the source metal 22. The in-
terface between the drain metal 24 and the amor-
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5,~
phous layer 14 creates another Schottky barrier
contact. A gate insula~or layer 26 of insulating
material such as ga~e oxide or gate nitride 26 is
deposited over the source metal 22 and drain metal
24 and in contact with the amorphous alloy layer 14
between the source and drain metal. On this layer
26 of gate insulating material is deposited a gate
conductor 28 which can be made of any suitable
metal such as aluminum or molybdenum. On the gate
conductor another layer 30 of insulating material
is deposited to passivate the device, which is
identified as a field oxide.
The insulating layers 16 and 30 would be join-
ed before the next adjacent transistor with the
source 22 connected to an external conductor. The
insulating layer 16 forms the insulator for the
next device similar to the insulator 18 of the
transistor 10 shown.
The gate insulator layer 26 and the bands 16
and 18 o~ insulating material referred to as being
a field oxide can be made of a metal oxide, silicon
dioxide or other insulator such as silicon nitride.
The source metal 22 and drain metal 24 can be form-
ed of any suitable conductive metal such as alumi-
-16-
num, molybdenum or a high work function metal such
as gold paladium, platinum or chromium. The gate
insulator can be a nitride, silicon dioxide or
silicon nitride material.
In accordance with the teachings of the pre-
sent invention, an alloy containing silicon and
fluorine which can also contain hydrogen is uti-
lized for forming the amorphous alloy layer 14.
This alloy provides the desirable characteristics
enumerated before which can be utilized for many
different circuits. The alloy layer 14 is pre-
ferably made of a-Sia:Fb:Hc where a is between 80
and 98 atomic percent, b is between 1 and 10 atomic
percent and-c is between 1 and 10 atomic percent.
The alloy can be doped with a dopant from
Group V or Group III of the Periodic Table mate-
rials in an amount constituting between 10 and 1000
parts per million (ppm). The dopant materials and
amount of doping can vary.
The thickness of the alloy layer 14 of amor-
phous material can be between 100 and 5000 Ang-
stroms, one thickness utilized being approximately
1000 Angstroms. The source metal 22 and the drain
metal 24 can also have thicknesses ranging from 500
to 20,000 Angstroms with one utilized thickness
being of approximately 2000 Angstroms. The gate
conductor 28 although described as being made of
metal, can be made of a doped semiconductor mate-
rial if desired.
Depending upon the geometry of the various
layers and thicknesses of the various layers, a
field effect transistor can be constructed as de-
scribed above wherein the leakage current is ap-
proximately 10-11 amperes thereby to provide a high
OFF resistance and a DC saturation current of ap-
proximately 10-4 amperes.
In constructing the thin film, field effect
transistor 10 shown in Fig. 1, the layers of mate-
rial, and particularly the alloy layer 14, aredeposited by various deposition techniques, pre-
ferably by glow discharge.
A conventional schematic gate ~G), source (S~
and drain (D) circuit diagram of the field effect
transistor 10 is illustrated in Fig. 2.
Referring now to Fig. 3, there is illustrated
a planar constructed thin film, field effect tran-
sistor 40 which, like the transistor 10, is formed
on an insulated substrate layer 42. On top o~ the
-18-
~.~.5~
substrate material 42 is deposited, such as by glow
discharge, an alloy layer 44 including silicon and
fluorine which also preferably includes hydrogen
and can be of the N or P type. On this alloy layer
44 are deposited two layers of insulating ma~erial
46 and 48 which are referred to in Fig. 3 as being
made of a field oxide with an opening 50 formed
therebetween. Above the insulating layers 46 and
48 are deposited, respectively, a source alloy
layer 52 and a drain alloy layer 54 which also
include silicon and fluorine and preferably include
hydrogen. The source 52 and the drain alloy 54 are
N or P type amorphous alloys. An N-P or P-N junc-
tion is then formed at the interface where the
layers 52 and 54 make contact with the alloy layer
44.
After depositing the layers 52 and 54, a gate
insulator layer 56 referred to as a gate oxide 56
is deposited over the source region 52, the exposed
portion of the amorphous layer 44 and the drain
region 54. Then a gate conductor 58 is deposited
over the gate insulator 46 and a passivating insu-
lating layer 60 is deposited on top of the gate
conductor 58, identified as a field oxide.
--19--
3~
A conventional schematic gate (G), source (S)
and drain (D) circuit diagram of the transistox 40
is illustrated in Fig. 4.
The difEerence between the transistor 40 and
the transistor 10 is that the drain and source
regions or conductors 52 and 54 of the transistor
40 are made o~ a semiconductor material and prefer~
ably an a-Si:F:H alloy.
In Fig. 5 there is illustrated a new V-MOS
like construction illustrated in a thin film, field
effect transistor 70 made in accordance with the
teachings of the present invention. On a substrate
layer 72 is first deposited a layer or band of
drain metal- 74 which has a central portion thereof
cut or etched away. On top of the drain metal 74
is deposited a thin layer or band of amorphous
alloy 76 which has a central portion cut or etched
away aligned with the cut away portion of layer 74.
Similarly, a layer of source metal 78 is deposited
on the layer 76 and a corresponding central portion
thereof is cut away. Alternately, all the layers
can be etched in one step following the deposition
of all the layers. Then a aate insulator 80 re-
ferred to as a gate oxide is deposited over the
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4~
source metal 78 and into the resulting central V-
cut space 82 and onto the inclined edges of the
layer portions 74, 76 and 78 and over the exposed
substrate 72. Then a gate conductor 84 is de-
s posited on the gate insulator 82 and a layer 86 of
insulating material identified as a field oxide is
deposited over the gate metal conductor 84 as a
passivating layer.
This particular V~MOS like construction with
the open space 80 has the advantage that a very
short distance L is established hetween the source
metal 74 and the drain metal 78 through the alloy
layer 76. The layer thickness or distance L re-
sults in a high operating frequency, and a higher
saturation current than the transistor configu-
ration of Figs. 1 and 3. The leakage current may
increase over the configuration of Figs. 1 and 3.
A conventional schematic gate (G~, source (S)
and drain (D~ diagram of the transistor 70 is shown
in Fig. 6.
In Fig. 7 is illustrated another V-MOS like
thin film, field effect transistor 90 formed on a
substrate 92 with alloy layers 94, 96 and 98 having
silicon and fluorine (N or P type) deposited on the
-21-
substrate 92. The respective layers 94, g6 and 98
have a central portion 1~0 cut or etched away
thereof. Then a gate insulator 102 identified as a
gate oxide is deposited over the edge of the layer
98 and contacts the exposed edges of the layers 94,
96, and 98 and also the exposed portion of the
substrate 92 as shown. A gate conductor 104 is
deposited over the insulator layer 102 and lastly a
layer 106 of insulating material, such as a field
oxide, is deposited over the gate conductor 104.
The transistor 90 operates utilizing the oppositely
biased P-N junctions formed between layers 94 and
96 and between 96 and 98.
The transistor 90 is similar to the transistor
70 as shown in Fig. 5 except that the source region
98 and drain region 94 is made of a semiconductor
alloy, such as a-Si:F:H. The V-MOS like construc-
tion of the invention illustrated by transistors 70
and 90 is advantageously utilized with any depos-
ited semiconductor material, such as but not only asilicon alloy containing at least hydrogen as de-
posited from silane.
A conventional schematic circuit diagram of
the transistor 90 is illustrated in Fig. 8.
-22-
3~
Referring now to Fig. 9, there is illustrated
therein another field effect transistor 110 made in
accordance with the teachings of the present inven-
tion. The transistor 110 is formed on a metal
substrate 111 which has deposited thereon a thin
layer of insulating material 112 which separates
the active components of the transistor 110 from
the metal substrate 111 and yet is thin enough so
that heat generated in the transistor 110 can flow
to the metal substrate which forms a heat sink
therefor.
The thin film, field effect transistor 110 is
formed by deposit.ing a source conductor layer 114
made of met-al or N or P type semiconductor alloy.
A drain conductor 116 is deposited on the insu-
lating layer 112 and also is made of a metal or a P
or N type semiconductor alloy. On top of the con-
ductors 114 and 116 is deposited an intrinsic or
lightly doped alloy layer 118, such as the a-Si:F:H
alloy previously described~
On top of the alloy layer 118 is deposited a
gate insulator 120 which can be a silicon oxide or
a silicon nitride. On top of the gate insulator
120 is deposited a gate conductor layer 122 which
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can be a metal or semiconductor material. A pas-
sivating layer 124 is deposited over the gate con-
ductor 122.
The various transistors 10, 40, 70, 90, and
110 can be formed in a matrix so that either the
source or drain region extends as a Y axis con-
ductor across the deposited substrate 112. Then,
the drain or source region is deposited to form a
segregated drain or source region which is then
connected to an X axis conductor. Then the gate
electrode is deposited so as to extend parallel to
the Y axis to form a Y axis gate conductor. In
this way, the field effect transistors 10, 50, 70,
90, and 110 can be utilized in conjunction with
PROM devices to form the isolating device in a
memory circuit therefor which comprises a memory
region and the isolating device.
The thin film, field effect transistor of the
present invention and the various specific embodi-
ments thereof described herein provide a transistorwhich is very small and yet has very good operating
characteristics as enumerated above. The top in-
sulating layer of the transistors, such as 124 in
Fig. 9, can be utilized to form the insulating
-24-
3~
layer for another transistor to be formed thereon
to provide a stacked transistor configuration and
hence further increase the packing density of the
devices. This is possible because the layers are
deposited and because of the low operating and
leakage current of the devices.
From the foregoing description it will be
apparent that a thin film, field effect transistor
incorporating an alloy layer of a-Si:F:H therein
according to the teachings of the present invention
has a number of advantages.
The planar structures of Figs. 1, 3 and 9 also
can be formed in inverse order to that shown with
the gate on the bottom. The Schottky barriers also
can be an MIS (metal insulator semiconductor) con-
tact. Also, the gate conductor in a device can be
metal, polysilicon or doped semiconductor material
with a different metal or semiconductor drain ma-
terial, instead of both being of the same metal or
semiconductor material.
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