Note: Descriptions are shown in the official language in which they were submitted.
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PIPELINED DIGITAL SIGNAL PROCESSOR USING A
COMMON DATA AND CONTROL BUS
Background of the Invention
. _
The invention relates to a pipelined digital
signal processor which may be more particularly described
as a processor using a common data and con~rol bus.
Digital computers typically include a memory,
input-output circuitry, a controller and an arithmetic
section. The memory provides a source for a computer
program to control the computer and for data to be opera~ed
on by the arithmetic section. The arithmetic section
includes circuits which provide means for manipulating data
in a predetermined manner. The controller provides control
signals for regulating timing of operations and transfers
of data to be operated upon. The input-output circuitry
provides means for transferring information between the
computer and external devices.
To increase computational speed, some digital
computers are arranged for pipelinecl operation. In a
pipelined operation the arithmetic section includes a
collection of specialized circuits capable of working
simultaneously but altogether forming a general purpose
organization. These specialized circuits operate
independently, each performing a specific task in a general
purpose procedure. The pipelined operation divides a
process into several,subprocesses which are executed by the
individual specialized circuits. Successive ones of the
subprocesses are carried out in an overlapped mode
analogous to an industrial assembly line. New operands are
applied at the input to the arithmetic section during each
cycle. Different subsections of the arithmetic section
perform their tasks in sequential order during subsequent
cycles. A resultant is produced during each cycle. Rach
specialized circuit performs its own task at the cyclic
rate.
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Control of a pipelined processor presents partic-
ularly perplexing problems because data and instructions
become stacked up in pipelines during steady-state
operation.
Heretofore a pipelined digital processor has been
designed to transfer data words and instructions from
memory to an arithmetic section and a control section in
respective pipelined streams. Data words are transferred
from memory by way of one bus to the arithmetic section.
Instructions àre transferred from memory to the control
section by way of another bus. These two separate busses
alleviate bus contention and enable the pipelined data
stream an~ the pipelined instruction stream to be
transferred from section to section very rapidly. As a
consequence, the rate of computation is enhanced~
A problem arises, however, when a processor
designer desires to use this pipelined architecture in a
processor to be fabricated as a single integrated circuit
chip. The logic circuitry and the bus structure require-
ments of the processor use so much space on the chip thatthe chip becomes too expensive.
mmary of the Invention
In accordance with an aspect of the invention
there is provided a pipelined digital signal processor
comprisin~ a source for providing a stream of instruction
words for controlling routine processing operations and
for providing a stream of data words; an arithmetic
section for processing one data word with another data
word through selected processing subsections performing
operations represented by an expression, thereby producing
a resultant da~a word; a destination for receiving the
resultant data word from the arithmetic section; control
means responsive to an instruction word (i.e., Ii) from
the source during each processor c~cle for controlling
processing subsections operations during a subsequent
processor cycle, each processing subsection responsive to
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the instruction word for performing an operation relating
to a different expression than the o~her processing sub-
sections during the subsequent processor cycle (i+2); a
common bus selectively interconnecting the source, the
arithmetic section, the destination and the control means
during every processor cycle for transferring the
instruction word from the source to the control meansy for
transferring data words from the source to the arithmetic
section, and for transferring the resultant data word from
the arithmetic section to the destination.
A solution to the problem is incorporated in an
exemplary pipelined digital signal processor having a
com~on data and control bus, The processor includes a
source of instructions and data words. An arithmetic
section processes one data word with another data word
through selected processing subsections performing
operations according to an expression, thereby producing a
resultant data word. A destination receives the resultant
data word from the arithmetic sectionO Control circuits
receive a single instruction during each processor cycle
for controlling all processing subsections operations.
During each processor cycle, each processing subsection
performs an operation relating to a different expression
than the other processing subsections are performing during
that processor cycle. All o the opera~ions controlled by
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the single instruction occur during a single processor
cycle. The common bus is time-shared during every
processor cycle for transferring the single instruction
from the source to the control circuits, for transferring
data words from the source to the arithmetic section and
for transferring the resultant data word from the
arithmetic section to the destinationO
Brief Description of the Drawings
A better understanding of the invention will be
reached by reading the subsequent detailed description with
reference to the drawing wherein
FIGS. 1 and 2, when positioned as shown in FIG. 3
which appears with FIG. 1, form a block diagram of a
pipelined digital signal processor;
FIG. 4 is a timing diagram; and
FIGS. 5 and 6 when positioned as shown in FIG. 7
which appears with FIG. 5, form a processor function chart.
Detailed Description
Referring now to FIGS.l and 2, there is shown the
overall architecture of a pipelined digital signal
processor.
A read only memory 100 stores instructions and
fixed data words. ~nstructions are transferred from the
read only memory by way o~ a common data and control
bus 101 to instruction registers IR-C; IR-L,M,N; and IR~
S,T, 131, 133 and 134 respectively. Parts of instructions
are distri~uted to the instruction registers. Fixed data
words, or coefficient words, are transferred from the read
only memory by way of the common data and control bus 101
to a coefficient register 102. The regis-ter 102 is
labelled REG ~ because the coe~ficients are identified
hereinafter by the symbol x.
- A random access memory 105 stores variable data
words which may be stored therein eikher from an external
source or from the output of the arithmetic section of khis
processor. The variable data words are transferred from
the random access memory by way of the common data and
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control bus 101 to a variable data register 106. ~he register
106 is labelled REG Y because vari;alle data words are ident-
ified hereinafter by the symbol _. By choice of the user,
the random access memory may store coefficients used in place
of fixed data words as well as the variable data words.
Registers 102 and 106, respectively, store a sequential
stream of coefficient words and variable data words which are
operands applied as inpu~s to an arithmetic section 110. These
sequences of operands are processed in a pipeline ashion
through a mul~iplier subsection 112, an accumulator subsection
115 and a rounding and over~low circuit subsection 116. A
rounded output word is produced in a register 118 that is
labelled REG W because rounded output words are identified
by the symbol w hereinafter.
A select output circuit 120 is included within the
arithmetic section for choosing as an output words from the
arithmetic section to the data bus 101 either the variable
data word y stored in register 106 or the rounded output word
w stored in register 118. The rounded output word _ is a
resultant of some process perormed by the arithmetic section.
The chosen Olltput word can be transferred from either the
register 106 or the register 118 by way of the common data
and control bus 101 to a writeable destination, such as in
the random access memory 105.
As previously montioned, instructions for the digital
signal processor are stored in read only memory 100. During
state 3 of each processor cycle, shown in FIG. 4, a single
instruction automatically is read ou~ of read only memory
from a location having an address produced by an address
arithmetic unit, or section~ 12~. The address from a progr~m
counter re~ister PC in the address arithmetic section is
applied by way of an address bus latch 145 and an address bus
12~ to the address circuitry of the read only memory. Read
only memory responds during each processor cycle by sending
the single instruction thus fetched by way of the common data
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and control bus to the various control field, or
înstruction, registers IR-C, IR-L,M,~, and IR-S,T
associated with different sections of the processor.
Each instruction, or opcode, used in the digital
signal processor includes a plurality of control fields, or
control messages, each of which is giYen a designation such
as 1, m, n, s and t to be used hereinafter. The control
field register IR-L,M,N associated with arithmetic
section 110 receives some of the fields, such as
instruction fields 1, m and n, respectively associated with
control of multiplying r accumulating and rounding
operations. The control field register IR-S,T, associated
with the address arithmetic section 124, receives
instruction fields s and t which relate to control of
address register modification for controlling the fetching
of operands x and~y and the storing of the output word
chosen by the selector circuit 120.
The address arithmetic section 124 includes two
sets of registers 141 and 142, an address bus latch 145, an
adder 147 and an adder latch 150 interconnected by some
busses.
One set of reyistors 14l, including reyisters RX~
RY, RD, and PC, is arranged to store memory addresses. An
address stored in register RX can be used for accessing a
coefficient word stored in a location in either random
access memory or read only memory. An address stored in
register RY can be used only for accessing a variable data
word stored in a location in random access memory. An
address stored in the register RD can be used for writing a
resultant data word into a destination, such as a location
in random access memory. An address stored in the program
counter register PC is used for accessing the next
instruction or fixed data word from the read only memory~
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The second set of registers 142 is arranged to
store variable increment values to be used for incrementing
automatically addresses stored in registers RX, RY and RD.
Alternatively, the stored addresses may be incremented by
one of a set of fixed value increments.
Operations of the digital signal processor are
controlled by two types of instructions. Normal
instructions are used most of the time. I'hey control the
performance of arithmetic operations during signal
processing. Another type of instruction, used
occasionally, is called an auxiliary instruction. One
specific auxiliary instruction controls the loading of an
address register or an address increment register in the
address arithmetic section~
It is assumed that a start up sequence of
instructions is stored in the read only memory starting at
an initial address and that a reset circuit sets the
proaram counter register PC to the initial address.
Following the reset operation, typically there is a
sequence of instructions for storing additional addresses
in the address registers RX, RY and RD and increment values
in increment registers RI, RJ and RK. I'hese reyisters are
set by auxiliary in~tructions. ~rdinarily the values
store~ in the registers RI, R~ an~ RK are retained therein
throughout a program while the values in the registers RX,
RY and RD are modified from time to time during the
execution of a sequence of normal instructions.
After the processor is reset and the address and
increment values stored, the processor can run a valid
3~ program for processing digital signals. Most of the
instructions used ~or processing signals are normal
arithmetic instructions.
Information in each of the registers RX, RY, RD,
PC, RI, RJ and RK can be set ~o any specific value hy an
auxiliary instruction. For example, a first instruction to
load address register RY specifies that some proc~ssor
register is to be loaded or set~
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In this first instruction, a control field c
contains the required information. This control field c is
stored in an instruction register IR-C during the
instruction fetch cycle.
A fixed data word, associated with the first
instruction and loaded into the address arithmetic
section 124 during the processor cycle in which that
instruction is decoded, provides information identifying
which address register is to be loaded and fixing the ~,
increment value to be loadedO The control field and value
field are transferred from memory by way of the common data
and control bus 101 to the control field register XSR 185
and the value field register XSL 186.
Whlle the first instruction is being executed,
15 the control field in the register XSR is decoded in a ~ -
decoder 157 to select the proper address register. From
register XSL the value to be loaded into the address
reg(ister RY is applied to the registers 141 and 142 through
a selector circuit 158 and a bus 160 in the execution cycle
of the first instruction.
A second instruction to load increment
register RI specifies that a processor register is to be
loaded or set. ~s in the just described example of set-ting
the address register RY, a fixed data word similarly
associated with the second instruction provides a control
field to identify the register to be set and a value field
to establish the value to be loaded. The fields of the
fixed data word are applied from the register XSR through
the decoder 157 and the bus 137 to determine the increment
register selected in the set of registers 142 and from the
register XSL through selector 158 and bus 160 to establish
the value to be loaded in the selected increment register
during the execution cycle of the second instruction.
During the processin~ of both normal and
auxiliary instructions~ control fields s and t from the
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ins~ruction'are s ored in the instruction register IR-S,T
when that instruction is fetched. These fields are decoded
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in a decoder 152 during the next processor cycle with the
decoded information being latched in an AAU control
circuit 154. This decoded information is applied over a
bus 135 to the sets of registers 141 and 142 during the
instruction execute cycle, or second processor cycle, after
the fetch. Both an address register and an increment
register or a fixed increment are selected by the
information on bus 135. The address is applied to the
address bus latch 145 and to the input of an adder 147.
The increment value simultaneously is applied to the other
input of the adder 147, which increments the address and
stores it for one machine state in an adder latch 150.
During the following machine state, the incremented address
is applied by way of a bus 136 to the set of address
registers 141.
Simultaneously during the procéssing of a normal
instruction, part of the information in the fields s and t
is applied through a single machine state delay in a delay
circuit 15~. This delayed information provides selection
information for determining which of the address
registers 1~1 is to be written after the just described
addressing operation. In the following machine state, the
delayed information is decoded in a decoder 157 and applied
over a b~ls 137 ~o the address registers 141. At this time,
the incremented address stored in the adder latch 150 is
written into the selected address reyister thus modifying
the address after the addressing operation.
During the processing of an auxiliary register
set instruction, the above described operation for writing
a post modified address back into an address register may
be preempted by the register set operation. Preempting is
accomplished by the decoder 157 in response to information
~ applied thereto from logic circuit 122 by way of a
; path 138, AAU control circuit 154 and delay circuit 1550
When the register set instruction preempts the
writing of an address register, the information for
selecting the address register is applied from register XSR
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through the decoder 157 and bus 137 to the address register
set 141. Simultaneously from the register XSR, information
is applied through decoder 157 and bus 137 for selecting
information on bus 160 in lieu of information on bus 137.
The address arithmetic section 124 transmits
addresses by way of the address bus latch 145 for accessing
locations in memories 100 and 105, generates new addresses
in the adder 147 and sets the address registers RX, RY, RD
and PC.
Referring now to FIG. 4, the diagram shows that
addresses are transmitted to memory as a series of four
addresses being transmitted during each processor cycle.
One of the addresses is transmitted during each of four
machine states during each processor cycle. The first
address transmitted during the first machine state is the
address stored in the program counter register PC. As
indicated in FIG. 4, this address is transmitted
automatically during the first machine state of each
processor cycle. The second address transmitted during the
second machine state is the address stored in register RD
or in register RX. The third address transmitted during
the third machine state is the address stored in
register RX or in the program counter register PC. The
fourth address transmitted during the fourth machine state
is the address stored in register RY.
Each address transmitted by the address
arithmetic section is latched in the address bus latch 145
during the mentioned machine states of the processor cycle. Il
~r/ Also during~those machine statesl the addresses are
incremented in the address arithmetic unit adder 147 by an
increment value that is read out of 0112 of the increment
registers RI, RJ and RK or in the case of the address from
register PC, the address is incremented by +1. These
incrementing operations are accomplished during the same
machine state that the address is latched.
Identification of the selected address and
increment registers is accomplished by applying the
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appropriate control fields to the instruction register
IR-S, T prior to the addressing operation so ~hat the
appropriate coding is applied to access circuitry for both
the address and the increment registers during the machine
state that the address is to be transmitted. Both the
address and the value of the increment are read out and
are summed by the adder 147. The resulting incremented
address is stored in the adder latch 150 while the address
is being transmitted from the address bus latch 145.
Coding for identifying whichever address register
was selected is transferred through the delay circuit 155
to the decode register circuit 157. Delay and decoding
are designed so that the incremented address stored in the
adder latch 150 can be written into the address register
from which the transmitted address was fetch~d. Thus the
transmitted address is post-modified or post-incremented
during the processor cycle when it is transmitted to the
memories 100 and 105.
Turning now to FIG. 2, the arithmetic section 110
is organized for pipelined operations. Coefficients words
x and variable data words y are operands received ~rom the
memories by way oE the common data and control bus 101
into coefficient word register 102 and the variable data
word regi~ter lQ6. During every machine state 1, one
coeffici~nt word x is fetched over the common data and
control bus 101 into the coefficient word register 102;
as shown in FIG. 4. During every machine state 2, one
variable word y is fetched over the common data and
control bus 101 into the variable data word register 106,
as shown in FIG. 4O The rounded output words w also are
operands for some operations and are stored in the register
118~ A new operand is received into each of those registers
during every processor cycle of a normal instruction.
The arithmetic section 110 includes three sub-
sections which are independently controllable in response to
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different control fields 1, m and n. During the fetch cycle
of an instructiont the fields 1, m and n are stored in an
instruction register IR-L,M,N. In the next processor cycle,
those fields are decoded in a decoder circuit 113 and the
result stored in register REG F 188. During the following
processor cycle, this information is transferred to an AU
control circuit 114 for supplying control signals to various
subsections of the arithmetic
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section. This latter processor cycle is the execution
cycle o~ the instruction. The control signals provide
information relating to which choices are to be made from
processing options available in each of the subsections.
The multiplier subsection 112 typically generates a product
of two operands during each processor cycle. In a typical
multiplication, one operand is the coefficient ~ord x and
the second operand is either the variable data ~ord y or
the rounded output word w.
Coefficient word ~ is a 16-bit word. These
sixteen bits are taken into the register 102 from the most
significant bit lines of the common data and control bus.
A selection circuit 162 scans the sixteen bits of the
coefficient word, from the least significant bit to the
most significant bit, four bits at a time during each of
the four machine states in every processor cycle. Another
selection circuit 163 concurrently selects either a 20~bit
variable data word y or a 20-bit rounded output word w.
Multiplication based on Booth's algorithm well
known in the art is performed. Thus a Booth logic
circuit 165 responds to the successive 4-bit nibbles to
produce control signals ~or the generation oE partial
products.
The output from the Booth logic circuit 165
during ever~ machine state is latched into a register 1~60
This output is applied to a circuit 168 which produces the
partial products by data selection.
These partial products are accumulated by adding
to prior sums and carries. An adder 170 sums the partial
products with the prior sum and carry information storing a
resulting 36-bit intermediate operand, or product word p,
in a product register P 191. Associated registers S 190
and C 189 respectively store the sum and carry information
produced during each processor cycle.
Because the arithmetic section is arranged for
pipelined operation, the product register P 191 receives a
new intermediate operand, or product word, p during every
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processor cycle of normal instructions. This product word
p is applied by way of a bus 172 as an intermediate operand
to the input of the accumulator subsection 115.
In the accumulator subsection, the product word _ is
added with a 40-bit resultant output word _ that may be
shifted by a circuit 174 prior to application as an input to
an adder circuit 175. The adder circuit 175 produces sum
and carry information which is stored in register 177. The
sum and carry information is stored in register 177 during
every processor cycle. Carries are res~lved by carry-look-
ahead logic in adder 178. Owtput from adder 178 is applied
to an input of a logic circuit 180 together with the result-
ant output word a to generate the next subsequent value of
the 40-blt resultank output word a to be stored in register A.
Such a resultant output word is produced and stored in
register A 192 during each processor cycle of a normal in-
struction.
A portion of the resultant output word a is applied as
an input to the rounding and overflow circuit subsection 116
in 10-bit slices. These slices are clocked through a rounding
circuit 182 and an overflow logic circuit 18~ to thb 20-bit
rounded output register W in three consecutive machine stat~s
of each processor cyc].e. In tlle fourth machine state; State
3 shown undor processor cycles i~l and i~2 in Fig. 4 the
value in the register W may be corrected for overflow if the
value in the register A is too large to be represented in the
20-bit register W 118. Then during $tate 0 of the next
processor cycle, shown in Fig. 4, the rounded output word
can be transferred through the common data and control bus 101
to a destination, such as a location in the random access
memory 105 where it is stored.
The three subsections ~multiplier, accumulator and
rounding) of the arithmetic section accomplish their basic
operations in one processor cycle each. Outputs of the sub-
sec~ions are stored in registers every processor cycle so thatthe next subsection in line has a stable input to commence
the next subsequent processor cycle.
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Control of the arithmetic section 110 and of the
address arithmetic section 12~ is accomplished by a
pipelined stream of instructions applied from the
memory 100 through the common data and control bus 101. As
previously stated with respect to FIG. ~a single~
instruction is read out of memory during'each processor
cycle of operation. Such an instruction includes several
instruction fields, or control messages, 1, m, n, s and t.
Fields _~ m and n are transferred through the common_
bus 101 to the register IR-L,~,N for controlling the
subsections of the arithmetic section 110. Fields s and t
are transferred through the common bus 101 to the
register IR-S,T for controlling selection and
incrementation of addresses stored in the registers RX, RY,
RD and PC.
A fuller appreciation of the arrangement for and
operation by pipelined control of processing may be
achieved by the following discussion of a specific example
of operation.
A complete normal assembly language instruction
includes all of the information required to perform a
desired arithmetic operation. Assembly langua~e
instructions for the digital signal processor are designed
to represent the control for access to the memory and the
control for operation of the arithmetic subsection and of
the address arithmetic subsection. The arithmetic
subsection continuously performs multiplication and
addition operations. The normal arithmetic section
operations are characterized by the following general
expressions:
x.f(y) + fa(a~ --> a{ --> w}
~(w) + fa(a) ~~> a{ --> w}, where
_ is a 16-bit wide coefficient word usually fetched from
read only memory. The coefficient word x also could be
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fetched from random access memory or from an
input/output circuit 200 and ordinarily has a value for
all arithmetic operations.
y is a 20-bit wide data word normally fetched from rando~
access memory. Such a data word also could be fetched
from the input/output circuit 200.
a represents the 40-bit wide contents of an
accumulator register A 192. In the accumulator
register A 192, the least significant thirty-six bits
are used to accumulate the product of a 16-bit by 20-
bit multiplication~ The four most significant bits
provide overflow protection for the accumulation
operation.
w is a 20-bit wide rounded or truncated output of the
accumulator. The least significant bit of the rounded
output w corresponds with the bit that is fourteenth
from the least significant bit of the contents a of the
accumulatorO This correspondence of bits is consistent
with an assumption that the data word y and the rounded
output w are integers and that the coefficient word x
usually is restricted within the bounds -2 < x ~ 2.
f describes a function of either the data word y or the
rounded output w. Such function can be the actual
value, the sign, or the absolute value of eithex one of
the variables y or w.
fa generally describes a function of the contents a of the
accumulator, such as a, -a, O, 2a, etc.
The variables x, y~ w and _ are contained in arithmetic
section registers X 102, Y 106, W 118 and P l91
respectively.
The aforementioned general expressions imply that
three operations are to be performed by the processor.
(l) One of the products p = x.f(y) or p = x-f(w) is
formed and is stored in the product register P located
at the output of a multiplier.
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(2) An accumulation of a resultant word a = P -~ fa(a)
is accomplished in the accumulator.
(3) Then if required, the resultant word a of the
accumulator is rounded and the rounded output word w
is written into the rounded output register W.
Each of these three operations is completed during one
processor cycle of the digital signal processor. Typically
during the operations, the coefficient word x has a value
and a multiplication forms the product ~. Also typically
during each c~clel all three types of operations are
performed concurrently by different subsections of the
arithmetic section. For some instructions one or more of
the three operations may not occur. The operation
performed by one subsection during one processGr cycle is a
partial evaluation of a different general expression than
the expressions concurrently being evaluated in the other
subsections~
Assembly language instructions are converted to
machine language instructions which are stored in the
memory for actually controlling the digital signal
processor. Because the operations are dependent upon one
another and because all of the operations occur
concurrently within the processor, it is important to know
at all times what is stored in various registers and what
operation is to be performed thereupon.
To avoid confusion regarding which values of the !~
product word p and which values of the contents a of the
accumulator are involved in any processor operation, the
following order of operations is recommended when writing
assembly language expressions representing them.
p <-- x f(y)
{w <-- a} a <-- P + fa(a) or
p <-- x.f(w)
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Then as the reader proceeds from left to right, the proper
values of the product word p and of the con~ents a of the
accumulator are more apparent. The proper values are the
results of the last preceding operation which determined
C 5 those values Thus the value of the contents a of the
accumulator,to be rounded into the rounded output w or to
be used in any function ~a(a), is the contents a of the
accumulator at the end of the last previous accumulation.
Similarly, the value of a product word p to be used in a
current accumulation has a value determined in the last
previous multiplication operation.
Because of the reasons given in the foregoing
discussion of the order of processor operations, it is
important that the infor~ation contained in the assembly
language instruction be presented to the processor in
proper order. Information presented in the following order
is acceptable to the processorO
(1) A choice of destination is made. I'he word to be
written to the destination is chosen from either the
rounded output word w or the data word _. The chosen
word can be written into the random access memory or
into the input/output circuit. The speci~ic
destination of the select:ed word is given.
(2) As required by the instruction, there is a choice
of whether or not to move the resultant word a into
the rounded output w.
(3) One accumulation operation is selected from a
group of operations having a general expression
a = P ~ fâ(a).
(4) Specify a multiplication operation producing the
product p = x-f(y~ by indicating the source XSRC of
the coefficient word x, the nature of the function f,
and the selection of the data word y, together with
the source YSRC of the data word y. ~lternatively
specify a multiplication operation producing the
product p = x-f(w) by indicating the source XSRC of
the coefficient word x, the nature of the function f,
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and the selection of the rounded output _ rather than
the data word y.
The following exceptions apply to the above-
mentioned left-to-right rule. When the rounded output w is
selected for the multiplication, the value of the rounded
output _ is the value determined by the last rounding of
the resultant word a a~ performed in a preceding
instruction. If data word y is to be written and a source
for data word y~specified, the first step in execution of
the instruction moves the data from the specified source
into the data register Y. Thereafter any writing of this
new value for data word y can occur.
The following Table I summarizes the normal
assembly language instructions that a programmer would use
for preparing an assembly language program. The syntax of
a language called C is used as the assembly language which
is described in a text entitled, The C Programming Language
by B. W. Kernighan et al, Prentice-Hall, Inc., 1978. Each
complete instruction is formed by choosing four statements,
one statement from each column of Table I starting with the
lefthand-column and working toward the right. In the two
leftmost columns, the word NOTHING is lisked as a valid
choice. When the word NOTHING is selected as a part oE a
co~plete instruction, the corresponding space in the
instruction is left blank. Every complete assembly
~J ~a~a~ ~instruction is terminated by a semicolon.
TABLE I - NORMAL ASSEMBLY LANGUAGE INSTRUCTIONS
NOTHING NOTHING a=p p=XSRC*YSRC
DEST=y w=a a=p+a p=XSRC*w
DEST=YSRC a=p-a p=XSRC*c
DEST=w a=p+2*a p=XSRC*abs(QWRC)
a=p~8*a p=XSRC*abs(w)
a=p+a/2 p=XSRC*c*sgn(YSRC)
a=p+a/8 p=XSRC*C*syn(w)
a=p&a
'''
: . .
' '-:~ ,' '' ' , "' ;
. , , , I
- . , - !
BODDIE-l
~q~ 3
- 18 -
In Table I the symbol DEST means a destination
statement and is to be replaced in the assembly language
instruction by one of the following statements.
DEST
*rd+-ti
*rd++j
* d++k
obu~
where e~g~, *rd++i means that rd, which is the address of
the location in random access memory pointed to by the
contents of register RD, is post incremented by the
contents i of register RI. Interpretations of differen~
ones of the foregoing destination statements are explained
in more detail subsequently.
Also in Table I, the symbol X5RC means a
statement for the source of data word x, and the
symbol YSRC means a statement for the source of the data
word y, Each of those two symbols in Table I is to be
replaced, in any ~ssembly language instruction, by one of
the statements in the Eollowing two columns:
XSR_ YSRC
x(old x) ~ry++i
VALUE (immediate x) *ry++j
*rx++i *ry+~k
*rx++j ibufy
*rx++k
*rx
*rx--
ibufx
*(rom~rx++i)
*(rom+rx++j)
*(rom+rx++k)
&LABEL
. .,
BODDI E -1
1 9
~d Ys~
In the forego;ng columns headed XSRC' the symbol
VAIUE represents a number that appears as an argument
(mathematical~ of an instruction, i.e., the 16-bit word
immediately following the opcode in the read only memory.
5 Such argument is addressed by the address stored in the
program counter regi~ster PC. In other fetches from memory,
the coefficient word x is addressed by the contents rx of
the register RX. The notation *(rom~rx...) is used to
indicate that the con~ents rx of ~he register RX point to
10 read only memory rather than the random access memory. The
symbol &LABEL represents that the value read from memory
source x is an address associated with a label in -the
program. Other expressions presented in the foregoing two
columns for the sources of the coefficient word x and the
15 data word y are presented in more detail subsequently.
With respect to forming complete assembly
language instructions from the information presented ir
Table I, some caution ~s suggested. If the expression
DEST = YSRC is deslred in an instruction includlng the
20 expression YSR~ from the rightmost column, then the
expression DEST = y must be used in place of the expression
DEST 3 YSRC. If the rounded output w ts to be used in the
righkmost column, the expresslon DEST = YSRC cannot be
selected from the le~tmost column. Additionally, NOT~ING
25 should be selected from the leftmost column when the
assembly language instruction ~s a normal instruction in
which the source of the coefficient word x is located in
random acc es S memory.
'''' :
:,
- , . , . . ~ : ~ ,
BODDI 1~ -1
- 20 -
In the preparation of a program, a programmer
will first write out a series o-f general mathematical
expressions or operations desired to be performed.
These may take, for example, the form
x f(w~ + fa(a) --~ a{ --~ w}
,
10 Such a general mathematical expression is translated by the
programmer into an assembly language statement which
takes the following form:
s n m l,t
; *rd++j=w w=a a=p+a p=*rx++i **ry+~k;
where
; 1 means an instruction fleld for controll~ng the
formation o~ a product.
li
,.
. . .-
.
, ,
,
. - ' . :
BODDIE-1
- 21 -
m means the instruction field for performing an
accumulation.
n means an instruction field for controlling a transfer
operation Erom register A to register ~ with the
required rounding.
s represents an instruction field identifying a write
destination. In this example the destination is a
memory location specified by the address stored in
register RD. That address is post-incremented and the
result stored in the register RD.
t means an instruction field to fetch information from an
address stored in an address arithmetic unit register,
post-increment that address and store it back into that
same register.
The next step performed by the programmer is to
skew (spread or distribute) in time the assembly language
statement as follows:
Time s ~ m l,t
i _ ~ r-~r~
~.. A. . _ _~ . _ _ ~
i-~l _ ~ W a _ a=p-~a ~ _
*rd~+j=w _ _ ___ _ _ _
...... ~ _ _
The resulting skewed assembly language sta~ement,
which appears diagonally on the time line of the leftmost
column, is stated together with skewed assembly language
statements representing other general mathematical
operations. When these skewed assembly language statements
are stated together, the resulting pieces of different
statements which appear in the same row, or during the same
interval such as interval i, form an assembly language
instruction. In the assembly language instruction, ~he
different pieces of information in the same interval are
separate fields of that assembly language instructionO
- . :
BODD I E -1
L3L e~5
- ~2 -
Each of these fields controls a separate subsection of the
processor for performing a step in the process of
evaluation, as described by a portion of one of the general
mathematical expressions
An assembler program, which runs on a general
purpose computer, operates on each assembly language
instruction by moving the source fields two processor
cycles earlier in the program than the rest of the fields
in that same assembly language instruction. This moving of
10 the source fields is done to every assembly language
instruction in the program. The resulting time line for
the foregoi~g assembler statement, as skewed by the
programmer and the assembler will appear as follows:
Time s n m 1
i-2 ~ ttj y'~r~tt~ = =
20 i _ ~ p=x*y
i~1 _ _ a=p~a
i~2 w=a
_ _ ____
i~3 *rd~ w ~ _ _
Referr;ng now to FIGS. 5 and 6, there is shown a
time line dia~ram indicatiny how data ts processed in the
digîtal signal processor. In general, the diagram presents
the flow of data through various subsections of the
processor during the evaluation of one general mathematical
30 expression together with parts of other mathematlcal
expressions.
Before attempting to describe the operations
represented we will first define symbols used throughout
the time line diagram of FIGS. 5 and 6.
35 Ij is a machine language instruction fetched from read
on1y memory during a processor cycle, or interval,
_ and decoded within the processor during a
~.,~, ,
.. , . . i - .
,
, .
13ODDI E -1
t~'Si,23~;~
- 23 -
processor cycle, or interval, i-~l. In general the
instruction Ii affects operation of sections of the
processor during a processor cycle, or interval,
i+2. As previously mentioned each instruction
contains the fields, or control messages, 1, m, n,
s and t.
Ii(t) represents the field t in the machine language
instruction Ii for controlling the fetching of
operands xi+3 and Yi+3- These fetches take place
during the interval i+3.
Ii(l) represents the field 1 in the machine language
instruction Ii for controlling the computation of a
product, or intermediate operand, Pi~2 during the
interval i+2. The product Pi~2 is a function of
the operands xi+l and Yi~l-
Ii(m) represents the field m in the machine language
instruction Ii for controlling the accumulation of
output from, or desired resultant word, ai+2 during
the interval i+2. The resultant word ai~2 is a
function of the last prior resultant word ai+l and
a product Pi~1 previously computed.
Ii(n) is a field n in the machine language instruction
for controlling the transfer of a rounded owtput
word wi~2 during interval i~2. Rounded output wi.~2
is a function of the last prior rounded output w
and khe resultant word ai+l of the accumulator.
Ii(s) is a field in the machine language instruction for
controlling the storing of the rounded output word ,~
wi+l and the modification of register stored
: 30 addresses ui+2 during the interval i~2. The
modified addresses are a function of the prior
address ui+l and field Ii(s). The updated memory
state Mi+2 is a function of the field Ii~s), the
; prior memory state Mi~l, register stored addresses
ui+l and the rounded output word wi~l.
Ii(S~t) is a combination of fields s and t within the
; machine language instruction. The fields control
. ,
~ 't
,' ' ~' ' ' '
,: . i' `
,, ' ' ~ ` ' , ~
, '
:~ :
'
BODDIE-1
3'~
- 2~ -
the modification of register stored addresses ui+2
during the interval i+2. The modified addresses
ui+2 are also a ~unction of the address ui+l.
Xi and
5 Yi are operands fetched from memory during the
interval _, under control of the field t of the
instruction Ii_3 fetched from memory during the
interval i-3. Instruction Ii_3 is decoded during
interval i-2 and controls processing during
interval i-l wherein the addresses for operands xi
and Yi are produced. As previously mentioned these
operands are accessed from memory during interval
i. They are processed through the multiplier
during the interval itl under control of the field
1 of the instruction Ii 1~ which is fetched during
the interval ii 1 I'his produces the intermediate
operand or product Pi+l-
Pi+l represents the product formed by the multiplier
during the interval i+l. This product is an
intermediate operand which is used as an input to
the accumulator for its operation occurring during
the interval i~2. Product Pi+l is formed ln
register P under control of the field Ii-l(l). The
multiplier and multiplicand are the operands xi and
Yi-
ai+2 represents the contents o the accumulator during
the interval i+2. This is the desired resultant ~ :
word ai+2 for the expression being evaluated. The t
: word ai+2 is~an input for the rounding and output
circuit subsection for the interval i+3. The
rounding operation occurs under the control of the
field Ii+l(n)-
wi+3 represents rounded output word w which is available
in the register W and which can be stored into
writeable memory during the interval i+4 under the
control of the field Ii+2(S)-
. ,, ,J
-, " ,,: ~ :
,., '
BODDIE-1
25 -
In the diagram of FI~S. 5 and 6/ there is shown
all of the processing activities of various processor
subsections of the digital signal processor together with
time in processor cycles. Each column in the chart
represents a different processor cycle, or time interval,
of the processorO Information in each column is closely
related to some machine language instruction. Each row
represents activities of a different processor subsection
performing its assigned functions during operation of the
digital signal processor.
Since each row of the chart represents a
different activity, we shall define those activities. The
first row below the processor cycle headings indicates
storage activities, i.e., memory fetches and stores. The
second row presents the times at which instructions are
decoded within the digital signal processor. The third row
shows the computing of the product _ by the multiplier
subsection of the processor. The fourth row presents the
accumulating of the resultant word a by the accumulator
subsection of the processor~ Row five present~ activities
of the rounding and overflow subsection of the processor,
which produces the rounded output word w. The sixth row
discloses activities associated with modifying addresses
used for fetching data for the arithmetic processes.
The processing of the aforementioned general
arithmetic expression can be traced through the various
sec~ions and subsections of the digital signal processor by
reference to FIGSo 5 and 6.
A first step in the processing of a general
arithmetic expression is the fetching of operands for a
multiplication. As previously mentioned, information
relating to this fetch operation is placed by the assembler
program into an interval earlier than the information
associated with control of the multiplication operation.
As a result of this assembler program functionr every
machine language instruction includes a control field for a
fetch operation that fetches information from memory for
,
.
,
BODDIE-l
- 26 -
processing to be controlled by a subsequent rnachine
language instruction.
As an example of processing an instruction,
consider processing a general expression having information
relating to fetch operations ~or its operands included
within an instruction fetched during the interval i-3 of
FIG. 5. This instruction Ii 3 is shown in an emphasized
box and is labelled with a subscript identifying the
instruction as the instruction fetched during interval i-3.
Each instruction shown in the processor function chart is
similarly designated in accordance with the interval during
which the instruction is fetched ~rom memory. Also each
instruction, shown in FIGS. 5 and 6~includes several fields
of control information. ~ e~ ~ese fields 1, m, n, s
and t are shown in parentheses associated with the
instructions in the first row representing the fetching and
storing operations. A separate field or separate fields of
an instruction are shown in other rows of the chart, e.g.,
Ii(l) in the row for computing products and Ii(s,t) in the
row for modifying addresses.
During the interval i-2, the just fetched
instruction Ii_3 is decoded by the processor, as shown in
the emphasized box in the second row representing the
decoding of instructions.
A fetch operation for the operands x and ~,
identified by the instruction Ii 3~ begins during the
interval i-l. The fetch operation begins usin~ an address
specified in the instruction field Ii 3(t~. When that
address is used, it is modified and stored back in the
addrass arithmetic section as a function of the instruction
field Ii 3(s,t) and the prior state ui 2 of the registers
in the address arithmetic section. This modification of
addresses is shown in the emphasized box under the interval
i-l. Fetch of those operands x and y is concluded during
interval i when the specific operands xi and Yi, identified
by the instruction Ii_3, are read out of memory and are
transferred by way of the common data and control bus
'~ .
BODDIE-1
- 27 -
respectively to reyisters REG X 102 and REG Y 106. 'l'hese
fe-tch operations are shown in the emphasized box under the
interval :L. 'l'he operand xi typically is read out of read
only memory and operand Yi typically is read out of random
S access memory.
~ rhe address pointers, or the addresse~ stored in
registers ~X and RY, which were updated in the prior
interval i-l are used for accessing the operands from
memory durirlg the interval i.
The first aritnmetic operation to be performed on
the operands xi and Yi occurs during interval i+l. At this
time the multiplier subsection responds to the instruction
field Ii-l(l) for computing an intermediate operand, or
productl Pi+l, as shown in the emphasized box under
interval i+l. Such product Pi~l is shown as a function of
the operands xi and Yi and of the instruction field
_l (1) .
Instruction Ii_l, which includes the field
Ii-l(l) is fetched from memory duriny -the interval i-l, is
decoded during interval i and controls sections of the
processor during interval i~
'l~he next step in eva:Luating the genercll
expression is processed in the accumulator during interval
i~2. 'l'his is shown in ~ . 6 in the ~ourth row
~5 representing the accumulation of the resultant word a in an
emphasized box under the column designated interval i~2. A
resultant word ai+~ is shown to be a func-tion of the prior
resultant word ai+l stored in the accwnulator, the just
described interme~iate operand, or product, Pi~l, and of
the instruction field Ii(m).
If specified by the programlner and after the
result is accumulated duriny interval i-~, that result is
rounded and is stored in the rounded output register W.
This rounding operation is shown under the interval i+3 in
an e~phasized box in the fifth row re~resenting rounding of
the output. The specific rounding operation occurs during
interval i+3 where t~e rounded output wi~3 is shown as a
......
: ..
BODDIE - 1
,r~3;~
~ 28
function of the last prior rounded output wi+2 of the
rounded output register W 118, the just described resultant
word ai+2 of the accumulator, and of the instruction field
Ii+l(n)
A final step in processing the general expression
is a writing of the rounded output wi+3 into memory during
interval i+~. This is shown in the emphasized box in the
firs~ row of the chart under the interval i+4. ~riting a
new memory state Mi+4 is a function of the memory state
Mi~3 for interval i~3 of the last prior address register
state ui+3, of the last rounded output wi+3 just described,
and of the instruction field Ii+2(s) which was fetched
during interval i+2 and decoded during interval i+3.
Rounded output wi+3 conta.ined in the rounded
output register at the end of interval i+3 is transferred
by way of the common data and control bus either to the
random access memory or to a buffer in the input/ol~tput
circuitry during interval i~4.
At the same time that the memory write operation
occurs during interval i+4, the address arithmetic section
registers are updated based on information in the
instruction fetched during interval i+2. The information
used is included in the fields ~i+2(s,t) of the instruction
Ii+2 that is fetched during interval i~2 and is decoded
during interval i+3.
During the interval i-~2, it is noted that -the
instruction Ii which was fetched during interval i controls
the multiplier subsection, the accumulator subsection and
the rounding and overflow subsection of the arithmetic
section. This results from the instruction Ii being
fetched in interval i, decoded in interval i+l and used for
~ I o ~ ~e_ '~ S-~ ~ c~ G~\ ~'"
control during interval i+2. No parts~remain for
controlling subsections of the arithmetic sec~ion during
subsequent intervals, as in prior pipelined control
arrangements~ Most of the column representing interval it~
is emphasized with heavy lines so that the reader readily :
can find several fields of the instruction Ii for
. ,,.j
: . :
. . , : .' '
::
. ~
BODDIE-1
~J~
.... ~ !
- 2~ -
controlling subsections of the arithmetic section during
interval i+2.
Operands for the multiplier ope~ation were
fetched d~ring the interval i+1 which follows interval i.
The resulting product Pi+2 is formed during the next
interval i~2.
A resultant word ai~2 which is formed durin~ that
same interval i+2 is a function of an earlier resultant
word ai+l and an earlier product Pi+l. This resultant word
ai+2 is a resultant word evaluated for a different general
expression than the general expression being evaluated by
forming the product Pi+2. This concept can perhaps be
better understood by the realization that the emphasized
boxes forming a diagonal from the top of the column
designated processor cycle i down to the fifth row in the
column designated processor cycle i+3 relate to the
evaluation of one general expression. A similar diagonal,
shifted one interval to the right in each column, relates
to the evaluation of another different general expression.
Typically in a signal processing program,
instructions are executed~ in sequence, up to a point where
the program counter PC, is set to the address value in the
program store which is the location of the instruction of
the beginnin~ of the sequence. Thus the program will
operate contlnuously in a loop executing the same sequence
of instructions repeatedly. Furthermore, fixed cdata words
will be stored at memory locations where addresses are
~ \o~o~i~S
interleaved with 14~ n of instructions in the program
sequence. In this way, as shown in FIG. 4, the address in
the program counter register PC is used to address a fixed
data word cluring state 2 of processor cycle i+1. The
program counter then is incremented by the fixed increment
+l or is used to address an instruction, Ii+2, in state O
of processor cycle i~2. Again the program counter is
incremented by the fixed increment, +1, and used to address
the next fixed data word in state 2 of processor cycle i+2.
Continuing, the program counter is incremented by +l and is
- .
, :
~' " ' . ' '
'.
BODDIE-l
- 30 -
used to address instruction, Ii+3, in state O of the
processor cycle i+3 and so on until the end of the
instruction sequence. At that time the program counter is
set, by an auxiliary register set instruction, to the
address of the first instruction in the sequence.
The foregoing is a description of the arrangement
and operation of an embodiment of the invention. The .scope
of the invention is considered to include the described
embodiment together with others obvious to those skilled in
the art.
.
. ~,,
, ,, ., , , . - :
.
,
'
