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DlGlTAL TlME BASE WlTH COHERENT
RATE SWITCHING
Background of the Invention
The present invention relates to sampling clock
circuits in general, and in particular to a sampling
clock control circuit to provide coherent switching be-
tween sampling clock rates.
In electronic instruments such as digital process-
ing oscilloscopes and transient digitizing oscilloscopes,
10 high speed analog electrical pulses are converted to
digital representations to facilitate storage, analysis,
and display. Generally, the conversion to digital repre-
sentations is accomplished by sampling the analog pulses
at a fixed rate and then quantizing the samples by means
15 of an analog-to-digital converter. A sampling clock hav-
ing a plurality of selectable clock rates may be provided
to operate the sampling circuit at different rates for
input signals having different frequencies or transition
times. This permits faster signals to be sampled at a
20 faster rate, and slower signals at a proportionately
slower rate so that a maximum of information may be
obtained from the analog signal without exceeding avail-
able memory space. However, for wide pulses, where the
data changes at high rates on the leading and falling
25 edges and changes very little, if at all, over the flat
portions of the pulses, it has heretofore been necessary
to operate the sampling clock at the highest expected
rate in order to acquire the entire waveform. This re-
sults in inefficient use of sampling circuits and memory
30 space for the flat portions of the pulses.
In particular, for radar pulse analysis, it would
be desirable to divide the waveform into precise time
intervals and sample the data during each interval at a
rate commensurate with the expected rate of change of
35 data within each interval. However, switching between
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clock rates has heretofore been incoherent, which would
result in unpredictable time relationships between samples
acquired at different rates and thus yield a stored and
displayable waveform of arbitrary time dimensions.
Summary of the Invention
In accordance with the present invention, a digital
time base capable of coherently switching from one clock
rate to another is provided for generating sampling clock
pulses.
Because the timing characteristics and general shape
of certain waveforms or pulses to be acquired are known,
the waveform may be divided into predetermined intervals,
and for each interval a sampling rate may be selected
commensurate with the expected rate of change of the
lS waveform within the interval~ With both the time
intervals and the sampling rates known, the number of
samples to be taken during each interval may also be
determined, taking into account the fact that the total
number of samples taken along the entire waveform is
2~ limi~ed by the maximum available waveform memory space.
In azcordance with one aspect of the invention there
is provided a digital time base for providing sampling
clock pulses, comprising means for providing a plurality
of predetermined sampling rates; a base clock for producing
base clock pulses at a predetermined frequency; means
coupled to said sampling rate means and to said base clock
for dividing the frequency of said base clock pulses to
produce sampling clock pulses substantially coincident
therewith in accordance with respective predetermined
sampling rates; and control means for providing a pre-
determined number of sample clock pulses for each said
predetermined sampling rate, said control means selecting
a next successive sampling rate after all of the predeter-
mined number of sample clock pulses for the preceding
sample rate have been produced and prior to the next
successive base clock pulse.
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In accordance with another aspect of the invention
there is provided a digital time base with coherent rate
switching, comprising a base clock for producing base
clock pulses at a predetermined frequency; a variable-
modulus counter coupled to said base clock for dividingthe frequency of said base clock in accordance with
respective ones of a plurality of predetermined count
moduli; and means for switching the count moduli such that
such switching takes place between a divided base clock
pulse and a next succeeding undi~ided base clock pulse.
The digital time base sampling clock comprises a base
clock which operates at a predetermined fixed frequency, a
synchronous counter string which divides the base clock
rate in accordance with predetermined sampling rates, and
a clock gate which passes a sampling clock output pulse
only upon coincidence of a counter output pulse and a base
clock pulse.
The predetermined sampling rates and corresponding
numbers of samples are stored in a memory. A counter
counts sampling clock output pulses, and when the number
of counted pulses matches the stored number for a parti-
cular sampling rate, the next sampling rate and its
corresponding number of samples are selected. This
selection is substantially contemporaneous with the last
sampling clock output pulse, so that the synchronous
counter string and pulse counter are conditioned by the
new information before arrival of the next base clock
pulse.
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Therefore, switching from one sampling rate to another
during the course of waveform acquisition is coherent
because no unpredictable or unknown time gaps appear
between sampling clock pulses.
It is therefore one object of the present invention
to provide a digital time base with coherent rate switch-
ing.
It is another object to provide a sampling clock
that is capable of coherently switching from one sampling
rate to another during the course of waveform acquisition.
It is a further object to make more efficient use
of waveform memory space by sampling at rates commensu-
rate with expected rates of change of the waveform.
It is an additional object to provide a digital
time base for a waveform acquisition system in which
sampling rates and numbers of samples acquired for each
sampling rate are programmable.
Other objects and advantages will become apparent
to those having ordinary skill in the art upon a reading
of the following description when taken in conjunction
with the accompanying drawings.
Brief Description of the Drawings
FIG. 1 is a block diagram of a digital timebase in
accordance with the present invention;
FlG. 2 is a compacted idealized waveform of an
analog signal to be digitized at different rates; and
FiG. 3 is a timing diagram illustrating coherent
rate switching.
Detailed Description of the lnvention
Referring now to FlG. 1, there is shown a block
diagram of a time base for an acquisition system in which
analog signals are applied via an input terminal 10 to a
waveform acquisition circuit 12, which may suitably in-
clude well-known sample-and-hold and analog-to-digital
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converter circuits utilized by conventional digital oscil-
loscopes. The acquisition circuit 12 samples the input
waveform in accordance with sample clock pulses provided
by a base clock 14 and a sample clock gate 16 in the
digital time base circuit. An address counter 18 is
advanced by the sampling clock pulses and provides ad-
dress signals for storing digital representations of ana-
log samples in a waveform memory 20.
While waveform memory systems require both acquisi-
tion and readout circuitry, the present invention isconcerned only with the acquisition cycle, and, there-
fore, the readout circuitry is omitted to clarify the
description. It is presumed that readout for display
purposes is within the purview of those having ordinary
skill in the art and may be implemented using convention-
al techniques.
A time base control circuit includes a N counter
22, which divides the base clock rate by a preset count
modulus value from a sample-rate memory 24. The base
clock 14 may suitably be a crystal-controlled oscillator
which produces clock pulses at a fixed frequency, for
example, 100 megahertz. The N counter 22 may be any of a
number of commercially-available counters which count
down a presettable number of clock pulses and produce a
terminal count output at the end of each countdown cycle.
In this particular embodiment, a synchronous string of
counters is employed to provide a variable-modulus count-
er which is capable of dividing the clock signal from one
to 10,000 in steps of N=A XlOB, where 1 <A <10 and 05B
3, A and B both are integers. The sample rate memory 24
may suitably be a random-access memory (RAM) operated as
a first-in-first-out (FIF0) device controlled by ar ad-
dress counter 26. The address counter 26 also controls a
number--of-samples memory 28, which also may suitably be a
RAM operated as a FlF0 device. A number-of-samples count-
er counts clock pulses from the-sample clock gate 16. A
digital comparator 32 compares the count output of count-
er 30 with the contents of the addressed section of
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memory 28, and when there is a match, the comparator
issues a signal ~hich is applied via an advance gate 34
to the address counter 26, which advances one count and
selects the next sample rate or count modulus in memory
5 24 and the next number of samples in memory 28. l~hen the
terminal count of counter 30 is reached, such counter
issues a signal which is applied via a reset gate 36 to
reset the system.
Operation of the overall acquisition system may
best be understood in terms of an example. FlG. 2 shows a
compacted idealized waveform of an analog pulse to be
digitized. The characteristics of this waveform have been
chosen to illustrate a wide pulse having comparatively
fast leading and falling edges. Suppose that this wave-
form is to be applied to input terminal 10, and suppose
further that the available memory space of waveform memo-
ry 20 is 1000 storage locations, and that the clock rate
of base clock 14 is 100 megahertz. The waveform of FIG. 2
may be broken into three segments having respective dura-
20 tions of 2 microseconds, 20 milliseconds, and 600 micro-
seconds. These three segments are defined by breakpoints
BPl, BP2, BP3, and BP4. Segment BPl-BP2 is to be sampled
at a 100 megahertz rate, and 200 samples are to be taken.
Segment BP2-BP3 is to be sampled at a 10 kilohertz rate,
25 and 200 samples are to be taken. Segment BP3-BP4 is to be
sampled at a one megahertz rate, and 600 samples are to
be taken. This will provide 1000 samples to completely
fill the memory 20 and also provide complete information
relative to the waveform. It is assumed for this discus-
30 sion that BPl is the trigger point. The first step is to
load the predetermined data relating to the sample rates
and numbers of samples for each rate into the time base
control system.
Initially, the system is reset. This is accomplish-
ed by applying a logical low voltage to one input of the
reset gate 36, which is an AND gate, via an input
terminal 40. The other input, which is the terminal count
output of counter 30, has a logical high voltage applied
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thereto. The output of reset gate 36 goes low, resetting
the address counter 26, the number of samples counter 30,
the memory address counter 18, and a trigger flip-flop
42. After resetting the system, a logical high is ap-
plied, for example, through a pull-up resistor to a
suitable supply voltage, to input terminal 40 and to the
reset gate 36, allowing the output thereof to go high.
Similarly, a logical high is applied via input terminal
44 to the advance gate 34, which is also an AND gate, and
a logical high is also applied from the comparator 32 to
the other input of advance gate 34, holding its output
high.
Next, the sample-rate data and number-of-samples
data, which may be in the form of predetermined data
words, are loaded into respective memories 24 and 28.
This is done by placing first the data relating to
segment BP1-BP2 on the load lines and applying a load
pulse to an input terminal 46. Then the address counter
26 is advanced one count by application of a low-going
pulse at input terminal 44. Then the data relating to
segment BP2-BP3 is placed on the load lines, and the
process is repeated until all of the sample-rate and
number-of-samples data are loaded. After the hereinabove-
described loading process, the system is again reset to
return the address counter 26 to its initial position.
The reset pulse, in resetting the trigger flip-flop 42,
disables the memory address counter 18 and number-of-
samples counter until the system is activated by applica-
tion of a trigger pulse at an input terminal 48. Thus,
even though the time base is running at the first rate,
any samples taken by the waveform acquisition circuit 12
prior to the system being triggered are just thrown away.
A trigger signal may be derived from the input
analog signal in the manner employed by conventional
oscilloscopes. For example, the analog signal may first
be processed by a preamplifier, wherein a triggering
signal is picked off and then compared with an adjustable
voltage level to generate a trigger signal of any desired
point on the waveform which represents the analog signal.
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In such a case, the analog signal is applied from the
preamplifier to the waveform acquisition circuit via de-
lay line to give the time base circuits time to be
activated so as not to lose any of the analog signal. The
trigger signal is applied via input terminal 48 to the
clock input of flip-flop 42, allowing the Q output there-
of to go high, enabling the address counter 18 and the
number-of-samples counter 30. As mentioned previously,
the timebase is already operating at the first rate, or
100 megahertz, since the base clock signal is divided by
one. The terminal count output of counter 22 is a logic
low, and the sample clock gate 16 is accordingly an OR
gate which passes negative-going sample clock pulses when
both of its inputs are low. The address counter 18 and
number-of-samples counter 30 begin to count the sampling
clock pulses, and acquired samples are stored in address-
ed memory locations of waveform memory 20. When the 200th
sample clock pulse is counted by counter 30, the output
of comparator 32 goes low, pulling the output of advance
gate 34 low, advancing the address counter 26 one count,
selecting in memories 24 and 28 the sample-rate data and
number-of~samples data pertaining to time segment BP2-
BP3. The base clock 14 has a clock period of 10 nano-
seconds at 100 megahertz, and the foregoing comparator
switching, address counter advance, and memory output
update occurs in less than 10 nanoseconds so that the N
counter 22 is updated with the new rate before the next
base clock pulse arrives. Thus, at breakpoint BP2, the
sample clock pulse output from sample clock gate 16 is
coherently switched from a one-megahertz rate to a 10-
kilohertz rate, and no undetermined time gaps are presen~
in the stored waveform.
This process repeats between BP2 and BP3, where
waveforrrl acquisition circuit 12 acquires 200 rnore sam-
ples, and at breakpoint BP3 the sample clock pulse outputfrom sample clock gate 16 is coherently switched from a
10 kilohertz rate to a one megahertz rate. Between BP3
and BP4, 600 more samples are acquired, filling the
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memory. At breakpoint BP4, the number of samples counter
30 reaches its terminal count, producing a low output
which is applied to the reset gate 36 to reset the system
as described previously.
A graphic illustration of the coherent rate switch-
ing can be seen in the timing diagram of FIG. 3. Differ-
ent rates from those discussed above have been chosen to
facilitate an understanding of the coherent rate switch-
ing concept. Between BP1 and BP2, the base clock is
divided by one, and a sample clock pulse is produced for
every base clock pulse. At BP2, the rate is switched, and
the base clock is divided by five, with the first sample
clock pulse appearing coincident with the fifth base
clock pulse following BP2. Thus, the switching is coher-
ent because there are no undetermined or unknown time
gaps in the sample clock output. At BP3, the sample clock
rate is coherently switched again, and the base clock is
divided by two. Note that the sample clock pulses are
coincident with base clock pulses, and that the break-
points occur on sample clock pulses.
It will therefore be appreciated that the aforemen-
tio~ed and other desirable objects have been achieved;
however, it should be noted that the particular embodi-
ment of the invention which is shown and described herein
is intended as merely illustrative and not as restrictive
of the invention.
