Note: Descriptions are shown in the official language in which they were submitted.
s ~ n
;I'his inven-tion appli.ca~tion :is rel,ltecl to My o-thL3.r
Canaclian pa-te.r,-t applicatlon -title~d "D:[GITA~ ASE/r`L~ QUJ~J`~C~
LO~ D ~OOP" :~iled J~me 15, 15,32 bearing -the serial num~er
405,177.
~ D 0~ T~ rMV~ T~N
. . . . ~
This invention rela~tes -to a digi-tal p~nase locked
loo.o ancl ci.rcuits especially aclap-tecl-to use -thereoi.
BACI~GROUNG OF T~E IM-v'r~NT10 f
A phase locked loop i.s a circuit -tha-t permits -the
input and ~eedback signalsq. phases comparing -to con-trol -the
frequerlcy and phase Olr' an oscillator in the loop. A phase-
:~requency loched loop con-tols the oscillator's ou-tput by
conparirlg phases and ~requenies OI inpu-t and feedback signals.
~rhus it provides an adap-tive action of the input si.gnal's
frequency. Normally, most phase locked loop circui-ts provide
static phase error zero or some ~ixed value (such as 90 or
130 degrees) which is desired in cJock recovery circui-t. On
-the other hand, a lo-t of applications such as :~requency
syn-thesizer, PCM synchrorlization, -tone generator, tone decoder,
F~.q demodulator and other frequency manipulation circui-ts do
not mat-ter with static phase error. In -thls inven-tion, a
special phase-~requenc~ cletector is applied to compare phases
and :Lrequencies. Due to the nature o~ the circuit, i-t provides
a s-tatic phase difference if the centre frequency is no-t tuned
properly. It is sufficient :~or applications involing :~requency
traeking only. II' a s~atic phase error zero or 180 degrees is
desired, the local oscilla-tor frequency must be irnplemented
accuratly corresponding -to the input source and -the number of
up-down counter's stages normally should be lim.i-ted.
The presen-t invention also behaves as o-~her all
digital -transi.-tion phase loc'~ed loop circ-ui-ts -that ou-tpu-t sig.nal~s
--2~
s l n
ji-tter depends on the accurac,y and -,-'requency oJ7 the local
samplin~; clock.
The present invention, due to its dig;ta:L :form
na-ture, -the accuracy is no-t a:~ec-ted by power suppl,y and
temperat-ure variations. Low end o:f locking :Lrequency appears
-to be less -than 1 Hz. The high end of locking frequency
~epends on local clock frequency, percentage o:f jitter and
counter maximum i`requency response. I~ -the clrcuit i s
implemented in TTII logic :~orm, a loclcing frequency about
500 KHz appears to be possible i:~ cer-tain ji-tter is assumed.
Higher locking :~requency may require other high speed logic
device such as EC~ gates.
SUI-.'nUA~- OF THE I~ N''LON
According -to the -presen-t invention, there is a
di:~:~eren-tial latch converting input and feedback signals
into non-ove~lapin~ pulses ~or the up-down counter's inpu-ts.
The up-down cou~nter has parallel out2uts connected -to a
frequency rate mul-tiplier. The input o:~ -the :frequency rate
mul-tiplier ~s from a fixed local frequency source. The
output o~ -the rate multiplier is connec-ted to the clock
input o~ a counter. The out-put of the counter is connected
to one input o~ -the di:f:feren-tial latch as -the Ieedback signal.
The input signal is connected -to the o-ther inpu-t,o-~ the
di:fferen-tial latch.
The inpu-t sign2.1 c~uses the up-down coun-ter to
count up, -t'ne ~alue o:F which controls -the rate o:~ frequency
output from the rate rnultiplier. The :.eedback siglal cal,lses
the up-dwon counter to coun-t down. The up-down counter is
thus caused',to courl-t down ~Dy the feedback signal; and up by
-the input signal. ~ny varia-tion in phase or :frequency between
,~ ~.,,
~ ~ ~T ~1 9 1 ()
-t~o inpu-t signals to -th~ up~clwon eoun-ter cavse~ a comPensation
:-requeney ehange :,~rom t1lte rate mllltiplier ou-tpu-t. I'he
di F~eren-tial 1G7tC1t is also used to resolve the arbri-trat;on
condition when both in~?u-t and :~eedbacX signals slrnul-taneous
arrive same time. During s-teady sta-te, -the uo-down counter
counts arouncl a value v/i-th u-o and down by one bit. Thus -the
average ~alue o:f'-the up-dv~To:Q counter is tran~la-ted into an
average ,requeney out-l?u-t ~rom the rate rnultiplier. The
i`ollo,~in~- coun-ter smoo-ths -the ji-tter and ou-tpu-ts -the averaged
avelor-n as the :~eedback signal.
:~n general, -the in~en-tion com-prises an u-o-clown
coun-ter for up countirtg input irequency signal, a varlable
digital :~requency osc;.lla-tor coupled to the up~dwon eoun-ter
For reeeiving a coun-t signal Lrom the up-down coun-ter and for
generatjrtg an ou-tput signal having a :~'requency rela-ted to the
eount o~ up-clown coun-ter, and a cireui-t l~or applying the
ou-t~u-t signal to tne u3?-down coun-ter so as to c~,use the up-
down cotmter to count downt in re~onse -there-to, there')y
s-tabili ing -tite :'requency o:l" -the variable irequenc~J oscillator.
A be-tter unclers-tandil-t$ oi'-t'he invertion will be
ob-tained by reference -to -the detailed description below, in
conjunction with -the ~ollowing drawings, in whieh:
~igure 1 is a bloeh schernat:ic ol a basic :f'orm o
-the inven-tion,
~ igure 2 is a de-tail schernatic of a di~`~erential
la-teh, and
9~(1
~ 1igure 3 is an alternative block scherna~ c o-L
the inven-tion.
,~ rroI~ 0:1~ T~ ~ 3~ S
Turning now -to `~ ure l, a source o:f' input slgnal l
~:/hich is in-tended -to be stablllzed or locked is appliod via
one inpu-t 20 o~ a di~ eren-tial latch 2. One outpUt Z2 of
di~Perential la-tch 2 is connec-ted -to coun-t up lnpllt CU oi
up-dv~on counter 3. The parallel ou-tputs lO ol coun-ter 3 are
connected -to correspondlng multiplier ra-ti.o lnputs O:f' rate
r,lultiplier ~. Mormally, the ~ate multiplier ma~ be replaced
b~T a prograliLmable counter if -the reqvirement o~ t-ter is
not considerecl. Since the co~n-t ra-tio o:E` programmbale coun-ter
can be jamme(l in onl~r at theeA~:P clividing c~cle or i-t will
cause a random ;ohase di~scontinuit~J, -t~e rate mul-tiplier o:L~ers
bet-ter per:E'ormance concerning wai-ting jit-ter or a quantization
nolse of' the ou-tput signal~s phase. Output of local oscillator
7 is connected -to the clock input C of the rate multiplier 8.
The output O o:E the rate mul-tiplier 8 is connec-ted to the
clock inpu-t C o~ counter 9. I'he output Q o:~ coun-ter 9 is
connec-ted to the other input o~ di:~eren-tial la~tc'rl via circuit
path 21 as a feedback slgnal. rrhe other output o,1~ di-~:Perentlal
latch 2 is connec-tecl -to coun-t clown lnput ~D oI' up~down counter
3 via circuit pa-th 23.
In opera-tion, an lnou-t signal, which can be generated
by an oscilla-tor or deri~ed ~rom another source which is to be
stabilizecl or locl~ecl , is a;oplied to the up count inpu-t o~ up-
down coun-ter 3 through di-~,'eren-tial la-tch 2. The operation o:~
t~le di:~:E'erent~al latch wlll be descrlbed in more detail later.
The counter coun-ts up with -the in,,ou-t signal and the counts down
down ~.vith -the :E'eedhacl~ slgnal.
~ ~6~9~'~
The re~ul-tlng coun-t s:ignal is applied in parallel
to -the :E`requrncy rate .rlul-tplier ~ he :r'recLuenc-~J sutput o:~'-the
local oscillator 17 is mu~-tiplied b~J -thi.s count ratio -,ignal as
a :i'rac-t;on o:~ -total mavirnur!l count. i.e. :[:r -the count si,~r.na] is
hal:~-the ma~imui.l cou:n-t ratio o:~ -the up-clol/.7n, -the I~requenc~ outpu-t
o:,~ the ra-te mul-t;Jl?l;.e~ l be 7nal:i~ the ~'requenc~ 03- the local
oscillator 7. r~hen the ou-tput s.ignal ~rom ra-te mul~t:i~?lier ~ ls
div;dec': by coun-ter ~) to average the ji-tter and increase -the
signal to noise ra-t;o ;.n -the outpu-t? The out??ut o-.~ coun-ter 9 is
a?plied -through cli:1"~eren-tial la-tch 2 -to -the down coun-t input CD
o:~' counter 3 ~ria dl:L',erential latcl~ 2. As a resul-t, u-?-Z.own
co~m-ter 3 ;s causecl to colm-t clo~m a-t -the :!~reqllency ou-tpu-ted -rom
cou-ll-l;er ~.
In the stable concli~tion, the 1eecLbac~ requency is
tile same as -the in~u't i'requency signal. Consequently~ -E'or
every i.nput pulse appliecl -to -the v-o coun-t -ter.minal o:1 counter 3,
there :is a pulse appliecl -to th.e down coun-t -terminal. The resu]-t-
ing coun-t output signal :Frorn up-down counter 3 con-trols the rate
mul-tiplier as a var;able oscillator -to genera-te a s~table output
signal.
:rnmled-i-ate~ -t will 'oe observed tha-t the stead~J
state coun-t signal :~rom u~-duron counter 3 se-t to be hali''-the
rilaximum coun-t ra-tio will provide equal positive and nega-t:ive
linear dynamic range during Prequency -tracking. i.e. The :L~requ-
ency outpu-t :~rom local oscillator 7 should be twice -the :Frequency
ou-tpu-t ~rom ra-te mul-tiplier S. ~rom -this condition, i-t can
also be obser~ed -tha-t -the local oscllla-tor :1~requ.ency should be
auproxima-tely equal to 2"-~i's~ here '?l is the locking :-~requenc~J
(~'requcncy :~rom re:i"'erence source l) and ~ is -the coun-t ra-tio o-E'
counter 9. rf zero phase error is desired, the local oscilla-tion
91~
:t'requeney shou]cl be exac-tly eclv.a1 ^to 2~ eourse, a -person
skilled in -the ax-t vnclerstandingr this inven-tion wi]:L ?rovide
loc~ing :For alnost ~'ull range or :r-~requency whieh the ra-te
mul-tiplier ou-tpu-t can provideO -r~ a narrow band ~tracking is
clesired (suel~ as ~ nocle,l clemodu.lation), an op-tional ra-te
multi~lier 11 m2y be inserted in the circui-t as sl~o~;m in :~igure
1. This eonnec-t~on is as a easeacle aclcli-tion mode. The ou-tput
o:-' ra-te multiplier 11 is eonneetecl to eascade inpv.~t o" ra-te
inulti?lier ~3. F~a-te mu1-ti-plier 11 provides mini~ l'requency
out?u-t -Lron rate mul-tiip:!ier 13. The re:L~inement addi-tion L`requeney
rate is providecl by rate mul-tiplier 8. The strue-ture eonnee-tecl
as described'provides .a'narrow band trael~ing without a long ehain
o:'-' up-do~.7n eounters. OT~ eourse, -tlnis op-tional ra-te mul-tiplier 11
e.en also be a progra~mnable eolmter or -traditiona] ripple eounter.
Coneerning aequisi-tion, -thi~s inven-tlon provicle, limit-
ation o-~' eoun-ting when the system is out ol~ loek. The earry C
output o:~ the eoun-ter 3 is connected so as to prese-t the eoun-ter
-to i-ts highest coun-t. Tf'~t'Qe input ~requeney is very mueh larger
than the feedback frequency, a earry signal is genera-~ed and sets
the coun-ter so that all counts are set a-t high le~el. The borrow
output of the up-down counter 3 ls eonneeted through an inverter
6 -to rese-t the eoun-ter -to low. There~''ore, if' the input frequeney
is very much lov~er than the :~eedback f'requeney, a borrow signal
is generated, whleh rese-ts all the eoun-ts to low level.
It shoulcl be noted tha-t up-down eounters recluire
edge triggering, and since both the up and clown counts may not
be low a-t -the same time, -the dif:~eren-tial latch 2 eircui-t ls
u-tilized to elimina-te any missing eloek inpu-ts, retaining either
one o~ the two inputs high a-t any given time and to resol-ve an~
r~ce problem.
~, ~,
,.. ..
Turning to figure 2 consider:ing now -the operation
Or -the di:~feren-tial la-tch. .~n -th:is embodimen-t the di-Flerent:i.al
latch u-t~lizes :îour :~lip-:f~~Lops 1007 1017 102 and 103. The DATA
D and ~:ET ~ -teri~incls o~ l.ip-L`]o?s 100 and 102 are connec-tecl -to
a source o:~` po-tential ''V(hlgh~, c~nd.-the DA~A D and CLOC~ C
-term-nals o r' Plip~ lops 101 and 103 are simi.larly connec-tecl.. The
ou-t~u-t o:L~ l;p-:llop 100 -t~le Q outpu-t o:L~ lp~ lop 133~ OU-tpllt
o:i AIID gra-te ]11 and -the out-ou-t o:l~ ri-~r~D gate 106 are connec-ted
to corresponding in-puts o:~`rlAND gate l0LI. The outpu-t o~ fAllD
~a-te 10~ is connected -to an inpu-t o:F N~i~lD ga-te ].39 and the S
terrdinal O r flip-ilop 101. The i~ ou.-tou-t o r lip-:flop lOO is
connected -to -the inp-ut o E' delay aevlce 113. Delay device 113
is used to guaran-tee -the low pulse ~.vidth generated :from Q Olltpll-t
o-~ flip~ lop 101 The ou-tput Or -the deLay device 113 and the Q
output ol~:L~lip-I-'lo-o 100 are colmec-ted -to inpu-ts of 0~ ~ate 114.
The ou.-tpu-t oC 0;~ ga-te 111~ is connected to `~ terminal ol :~lip-
:Llop 101. The ou-tput O~r ]';~AND ga-te loL~ and the Q Ollt-OU-t o:~P :Llip-
:.lop 102 are co~mected -to the inpu-ts of NAiMD ga-te 106. The Q
OU-tpllt o~ i',p-:Plo-o 101 and ou-t~ut of AND gate 111 are connected
to inpu-ts o-P NAMD gate 10~ 9 which has i-ts outpu-t cormected -to -the
terininal oi` flip-~lop 100. The outpu-t o~ NAITD gate 10~ -the
Q ou-tput o:E':E'lip-:E'lop 100 the Q ou-t;ou-t o:E':~lip-flop 102 and
the ou-tpu-t o:~`'NAMD gate 112 are connec-ted -to -the inputs o:E` NAMD
gate 109. The ou-tput of NAMD ga-t~ 109 is connected -to one i.npu-t
o.~ AMD gate 111 via dela-~ devi.ce 110 and -the o-ther inpu-t o~ AND
~;ate 1].1.
T}le l~ OU-tpll-t o~ ~lip--Plop 101 the l~ outpu.-t o:
ilip-:Llop 102 -the ou-tpu-t o~' LND ~a-te 111 ancl~the ou-tPu.t of'
NAND ga-te 10& are connected to inpu.ts of NAMD gate 112. The
ou-tpu-t o:~ NAND gate 112 :l.s connected -to input oP NAND gate 10
.,
~," .:,
~ ~191~
and -to -tl~e '' -termina1 o:~ flip-:-'lop 103. The Q ou-tpu-t O:L` i~lio-
:~lo-p 102 :is connecte~l -to -t'~le jnput o:,~ clela~ device 11~. ~e1a:y
clevice 115 is usecl ~o guaran-tee -t'ne 107~'/ pu.lse ~,l7idth genera-tec7
i'rom Q ou-t,out o:f :Fli-j?-:l'lop 103. r~'ne oU-t-Pu-G o:~ -the delay device115 and the Q ou-tpu-t o:~ lip-:i~lol? 102 are connec-ted -to inputs o:L'
Q~ ~,ate 116. The ou.-t,?u-t o- 0R ga-te 116 is connec-ted -to l-'.-cerr,~inalo:P :Llip-:~107? 103. The ou.-tpu-t o-i' MAND ga-te 112 and -the Q outpu.~t
o:F fli-p-flop 100 are com~ec~ted -to the inPutS of ~AMD gate 13~8.
rl'he Q out,ou-t o:,~ L lip-~lo? 103 anc,. the out-?ut o:~ A'~TD gate 111 are
col~nec-ted -to i.nputs ol L~ML~ gate 107. T~le output of~ which is
connec-ted to the I~ terrl~inal of llip-13.op ].02.
In operation, assurning -that a positive edge appears on
t~le .input signal lea,d 20, causing the ou-t,?u-t o,~ li;p-:-lop 130 -to
go higrh, i:~ -there is s:imul-taneously a low level signal on the Q
outpu-t o~ lip-:Llop 102, there ~i~ill be a low ou-tpu-t :Lrom I~JA~
gate 10~ and tl~us Q ou-ti)ut O:l~ ~li,p-l~lop 101 is se-t -to lo~ ue
-to -the low level of~ Q ou-t,out o~ p-flop 101, -the :E'lip-:i~lop 100
is rese-t ~through AND gate 1O~J The low level Q outpu-t o:~ flip-
flo~ 100 delayed b3~ dela,y clev:i.ce 113 will rese-t the :-lip-.~lop
101 again. Thus a narroT,I lo~ level pulse ls genera-ted a-t the Q
ou-t~u-t o~ lip-flo,o 101. Tllis lo~ level Pulse ls a-~plied to
COWlt up i1~pU-t ~'U o:~ -the u-p-do~-rn cou-n-ter through circui~t path 22.
The clela3r clevice 113 ls used.-to guaran-tee minirQum lovj leve7. pu.lse
~id-th.
Similarly, -the presence o~ a :f'eedback posi-ti~e edge
appears on signal pa.-th 21, causing -the outpu-t ol :f'l:ip-:f'lop 102
-to go high, iI' -there is s:imultaneously a low level on the Q
ou~t,~ut O:f' ~lip-L`1o p 100, tllere will be 2 l 0~/V level outpu-t f-'rom
MAN~) ga-te 112 and thus Q ou-tput O-r :~li-o-~'lop 103 is se-t -to lo~v.
Due to -the low level of Q ou-tpu-t o~ i p- f~lOp 103, the fljp~ lop
1(~2 is rese-t -through A!lD gate 107. ~he low level Q outpu-t of'
. . .
~ ~191~
I'`lip-,''lo-,o lV2 delave-:! b,y cle]ay c~ev;.ce ].1~ l rf-ese'G -the ~
l~1OO1O3. Tllis 10~J le~el pulse is applîed to coun-t clown ;.npu-t
~3 of tlne up-d~ion counter through circu.it 23.
A-t -the inter~Jcll T;~hen a Posi-tiYe edge ls aoplied to
clock C input 0~ Llit)-rlorp 102 ~throug~ circlli-t pa-th 21 ~;ligh-tl-J
la-ter ~th~an the orle applied -to :flip-J~lop 100 through circu.1-t path
2C~, ancl e:i-t~ner i~, Outp-l.t o~ ~lip-:~-lo-p 100 is ~igh or '~ outpu~t ol''
:L1:I-P~ 1OD 101 is 101~/, -the 1OW level signal requirecl -to set j~lip-
:~lop 103 is prohabited by r~AND ga~te 112. .~'lip-:.~loP 102 will
latch the high signal until t~e genera-tion o:F a low level pulse
a-t Flip-:~Flop 101 is co~l-oleted. A-t -this -time, a low level signal
outpu-t :.rom ML~ND ga-te 112 se-ts -t~e :~Flip-.~lop 103 ancl ano-ther 10W
level pu.lse generat:ion c~fcle is carried ou-t at the Q ou-t-put o:~
flip-:Flop 103. Similarly-, if a posi-tive edge is applied to flip-
i~lop 100 clock input C sligh-t1~f later -than the one applied to
:flip-:~'lop lQ2, a low level pulse will be genera-ted at -the Q output
o:~ :Lllp-:~lop 103 ,irs-t and -then ano-ther low level pulse will be
generated a-t the Q outpu-t o~ l:E'ip-:l~lo-p 100 a~-terwards.
In an opera-tion o~ both posi-tive ec!ges arriving Fli,p-
:Flops 100 and 102 a-t al:fnost same time, the ou-tpu-t o:f NAl\~D ga-te 111
is connectecl-to -the inputs o:~ ~MD gates 105 and 107 and is used
to ~e-t both input signals a-t ~lip :~lops 100 and 102 i:f a latch
up race condition occurs. Dela~J device 110 is used to provide
temporary disable o~ any illegal set pulse -to ~li.p-:L'lop 101 or 103
hich is clue to rese-t timing o~fset of l~ip-~lops 100 and 102
~eneratecl ~ro~l r`~AI`~D ga-te 10/l or 112 during the -time -that NAND gate
109 Ol,ltpUt rese-t-ting ac-tion is in progress. The abo~e s-ta-ted
di:~erential latch is lor illustra-tion purpose only although a
simplier circuit is possible.
Similar -to other phase locked loop circuits, parameters
used in a loop design depend on the loop bandwid-th~ jitter
requirement and locl~ing frequenc~t. In a success~ul prototy-?e,
the loc];lng J~requency inpu-t source 1. was 1 KHz, the up-down
coun-ter 3 was a ~r bi-t bjnary one, the :''requency ra-te
.
I ~619~0
m7ll-t:i7?1ier 8 ~as aLso a ~il bi-t one and -the ji-t-'cer ~il-ter cou-n-ter
9 ~.as a i~ k7it one (~., equals -to .2~6). T,ocal oscil:L2-tor 7 has a
512 ~ ïz out-pv-t. ,~ prei~erred selcc-tion o~ ra-te mul-tipl!er was
C,.0~7 CDII Oo~. O-ther logic devices ~.~ere iinplernented i.n C;rAOS :,rorm
also. ~osi~t:ivs pO}l su-???l~ and YV sol,7rce vrere selec-te(l -to be 5
volts. Dela~? devices 113,.113 and 115 were 2~!J -ITS cli~g;tal -'c,rpe.
T.c has 'oee~n :!'ov.ncl-t'Qat ~t7~ne inven-tio1 clescri'oed
aoove has a~ e~-tre:i-.qelvr wicle bloc~injg range and cap-ture range.
Tlle s-t-ruc-ture opera-tes as a ~requency and phase coMParator, o,.
a tv,i~e s~?'nich has been loundi not -to lock onto harmonics O ~n -the
inpu-t signal. It has a i'asi-t ac~lvis;-tion -time also due -to -t7ne
dc:~:inecl nonlincar s-ta-te ~len -ths sysitem.is ou-t oi.' locL.
A highly s-ta'ole all digi-tal ,ohase-:~r.'reyuenc~ lockecl
loop has been described, w1lich can be used ln a varie-ty o:~
c7,,ppl:icatlons as d.escribed abo~e. Numerous other embodimen-ts or
changes in desi.gn may now be :.nacle bVi a person sLrilled in the
art understancling this i.nven-tion. A11 are considered to be
~ri~thill -the spere and scope o:i~ -the in~en-tion as ds~ined in -the
clair,ls appended here-to.
,
I :~B1910
S'UPPl,El'.!EN'~A~ DI~JC~OS'[Jf~'~
~. ... ~
Al-though the circuits described in -the princir~al
disclose works well and reaclily locks on to an e~ternal :~Areq~.-
ency source, an addition oF circui-ts will provi.de the inven~tion
slightly more :rAlexible ancl ellmina-te an~ arginal clock pulse
genera-ted :~rom rate mul-tiPlier ~ ~4n applica-t;.on example ol the
invention is also described.
Turning now to :LAigure 39 the circui-t sho~,vn is -~n~
other al-ternative o:~ ~igure 1. A source o~ inpu-t signal 1
which is in-tended to be s-tabilized or lockecl is applied via
signal pa-th 24, op-tional AND ga-te 12 and one input 20 o? a
di~ erential la-tch 2. One ou-tput 22 o:P di.~ eren-tia] latch 2
:is connec-ted to cou.nt-u-p in-put CU of u-P-down counter 3. The
parallel ou-tputs 10 or` counter 3 are connec-ted -to corresponding
mul-tiplier rat:io inputs o-. ra-te multiplier 8 -through la~tch l~.
~10rmally, the ra-te ~ultiplîer r.tlay be replaced by a programmable
counter. Since the coun-t ratio o:P progra:~nmahle counter can be
jarLmed in only a-t -the end o~ tl~e di~iding cycle or it w.ill
cause a randorn phase discontimlity, the rate multiplier of~ers
better -,~er:L'orinance concerning waiting ,jl-tter or quant.zation
noise of the phase signal OUtpll-t :~rom coun-ter 9. Outpu-t o~
local oscillator 7 is connected -to t~e clock i.npu-ts C o-~ t~ne
rate multiplier ~, op-tional ra-te mul-t.iplier 11 and la-tch 1~.
I`he output Q o~ coun-ter 9 is connected to -the other inpu-t o~
di:~:Leren-tial latch 2 via circuit path 26, op-tional AND gate 13
and circui-t pa~th 21 as a :Feedback signal. The other outpvt o~
di~Aeren-tial latch 2 is connected to count down input CD o.~
up-dowll counter 3 ~ia circui-t path 23~ The output o-r optional
logic control 'EMA~Iæ' 27 is connected -to inputs o~ optional
AND gates 12 and 13 ~ia signal pa-th 25. Mormally, logic contro:L
-12~
1 ;~ 8 1 '~
27 ovtpu.t is hi.gh -to enable signals :l-ro-rn source 1 and coun-ter 9
routing to di~ eren-tial latcl~ 2. l:F tlne loss o:P signal :FrorQ
source 1 is de-tec-ted ex-ternally, log:ic con-trol 2f~ ou-t-?ll-t wi.ll be
set to low to disable .~llr-ther phases comprision. Thus ra-te
r,lulti.,~lier ~ will con-tinue -to genera-te -the same :Lrequency ra-te
as proportional -to the counter 3 last la-tched value.
A high e3~ficient tone decoder or MFSK(multi ~requ-
ency shi~t key) demodu.lator can be designaed -to apply -this
phase-:~requency loop. Since the sta-ted loop has an extended
linear phase comparator, i-t represen-ts tha-t -the dif'~erence
bet~een -two innuts may be :~rom zero to rnultlples o:~ raclians
~hile -the 100l? is still in linear locking rllode. -[~lor an ex~am!)le 7
each speci.:.ic count value outpu-t may represen-t a -tone (-~requency).
Thus di:L:,r'eren-t.speci:~ic coun-ts may represen-t d.;~:~eren-t -tones.
a democlulator is designed to provide count up inpu-t having
~ ) radlans di~:~erence than the :Fee~d,~back count-down input
wherl ever~ particular tone is recei~.red ~ steacly state, the
value o:~ the up-down counter excep-t -the leas-t signi:Picant bi.t
can be sensed as a M.~`SK binary encoded va],ue. ~ is an integer
including zero. I-t is ~luivalent -to have a rnulti level frequen-
cy modula-tion compara-tor. The noise ~rorn -the transmission line
~` and sligh-t of':~set .~requency :~rom -the -transrni-t-ter will be
translated as jitter ancl sta-tic phase error. I L' -the phase error
does not exist -the boundary o:~P plus and r!linus ~ radians~ i-t
will-not a~l~ec-t the level.cutting cleclsion~ Thus a~mu-tuall~r
independent tone (~requency) decoder can be ob-tainecl.
,~ ; -13-
