Note: Descriptions are shown in the official language in which they were submitted.
l9~g
The invention concerns a low resistance line especially auitable
for use in integrated circuits having relatively large capacities.
Such lines are used, for example, as bit lines for semiconductor
memories. The problem occurs that bit lines of memories with rather large
memory capacities in general are so long that as a result of the line resistance
of approximately 20 to 30 Ohms/square and the line capacitance during read-in
and read-out of the information which is to be stored, delay times must be
taken into ac¢ount which also determine the access time of the memory.
BRIEF SUM~ARY 0~ THE INVENTION
The invention is based upon the problem of providing a line having
extremely low ohmic resistance. This is attained according to the present
invention by means of the measures hereinafter described.
The advantage which was aimed for with the invention especially
consists in that the resistance of the double line structure which is formed
out of the oppositely doped region and the contacting strip is significantly
smaller than the customary diffused lines. A further design of the concept of
the invention, in the case of which a transfer gate is arranged next to the low
resistance line, which transfer gate is self-adjusting in its lateral position
with respect to the line edge.
Thus, in accordance with one broad aspect of the invention, there
is provided a low resistance line comprising a strip-shaped region which is
provided on the interface of a doped semiconductor body, the strip-shaped region
being doped opposite to the doped semiconductor body, characterized in that
above said region, a strip of highly doped polycrystalline silicon, which con-
tacts said region is located, in which said low resistance line comprises a bit
line of a dynamic one-transistor memory cell, and characterized in that it is
arranged in a predetermined spacing to a memory electrode which is formed out
of highly doped polycrystalline sillcon, a transfer gate being provided whlch
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covers said region and said memory electrode at least on their boundary sides,
and which is electrically insulated against the same and against said interface
of said semiconductor body.
In accordance with another broad aspect of the invention there
is provided an integrated circuit semiconductor memory structure, comprising, a
doped monocrystalline body of a first conductivity type, an insulating thick
oxide layer covering said monocrystalline body and including a row of thin
oxide regions~ first and second strip-shaped apertures extending through said
oxide layer and spaced apart from one another, the thin oxide regions branching
off alternately from said apertures, first and second bit lines each comprising
contacting strips of doped polycrystalline material of an opposite, second
conductivity filling respective strip-shaped apertures, and further comprising
redoped regions in said body below said strips having said opposite, second
conductivity, memory electrodes carried on said thin oxide regions, being form-
ed by parts of a strip of doped polycrystalline material arranged between said
bit lines on said insulating thick oxide layer, an insulating layer covering
said bit lines and said memory electrodes, electrodes carried on said insulat~
ing layer and laterally extending alternately from the redoped region~of one of
said ~it lines toward the other over said thin oxide regions, each of said
electrodes including a portion adjacent the associated bit line defining a
transfer electrode, a further insulating layer covering said electrodes, a
plurality of third apertures extending through said further insulating layer
to said electrodes, and word lines on said further insulating layer contacting
said electrodes through said third apertures.
BRIEF DESCRIPTION OF THE DRAWINGS
.
The invention will be explained more closely in the following
with the use of the drawing.
Figure 1 shows a view from above upon a low reslstance llne which
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~ 3 6 ~ 8
is designed according to the invention,
Figure 2 shows a cross section through the line according to
Figure 1, and
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Fi.gure 3 sh~ws a view from above onto aeveral one-transistor mem~
ory cells ~hich are driven with lines aesigned according to the invention.
DESCRIPTIO~ OF THE PREFERRED EMBODIMENTS
In Figure 1, a highly doped monocrystalline semiconauctor body 1
is sho~n, which on that portion of its periphery which lies p~rallel to the
drawing plane is covered with an electrically insulating layer 2. The semi-
conductor body 1 consists by way of example of p-dopea silicon, while the in~
sulating layer preferably is maae of SiO2. A strip-shaped contact hole 3 is
provided which is etched out of the layer 2. A strip ~, which is ~orrned on
the insulating layer 2, is made of highly doped polycrystalline silicon, the
lateral limits of which in Figure 1 are indicatea by a solid line, within the
contact hole 3, i8 directly adjacent to the interface of the semiconductor
body 1. Beginning ~rom the contacting surfaces of these two parts, a strip-
shaped semiconductor region 5 is doped opposite to the semiconductor body 1,
in the present case is n+ conducting, and extends parallel to the inter~ace,
the lateral limits of which are also indicated. by means of a solid line.
Figure 2 shows a cross section along the line II-II of Figure 1.
Besides the semiconductor body 1, the layer 2 ~hich is designed as a thick
field oxide layer, the strip 4 which contacts the interface o~ 1 and the re-
doped semiconductor region 5, underneath the thick layer 2. A zone 6 whichis directly next to the interface of the semiconductor body 1 can be seen,
which zone 6 is doped more strongly than the semiconductor body 1, and has
the same kind of conductivity. Such a zone can be designated as field im-
plantation or ~ield diffusion. It serves the purpose of de~initively limit-
ing the redoped region 5 in a lateral direction.
Together with a contacting strip 4 out of highly doped polycrystal-
line silicon, the redoped region 5 represents a double line structure, the
resistance in Ohms o~ which is significantly umaller than that o~ a customary
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diffusion line. The strip 4 i8 connected via a conne~tion line 7 (Figure 1)
with a lead 8, in a practical manner.
In Figure 3, four one-transistor memory cells 10 through 13 are
represented which are integrated upon a monocrystalline semiconductor body 9
and which are arranged in a row. Eac~l cell is associated with a somewhat
rectangular shaped thin layer region (gate oxide region) 141 tbrough 144 of
the electrically insulating layer 14 which covers the semiconductor body 9.
The upper ends o~ the regions 141 and 11~3 are reduced in width and open out
in a strip-shaped contact aperture 15, in which the layer 14 is etched away
to the interface of the semiconductor boay 9. The lower ends o~ the regions
142 and 144, which are also reduced in width, open out in a correspondingly
designed strip-shaped contact hole ~6. Above the contact holes 15 and 16 and
the parts o~ the insulating layer 14 which directly surround these are placea
strips 17 and 18 out of highly doped polycrystalline silicon, which are ad-
~acent in the region of the contact holes 15 and lÇ directly to the inter~ace
of the semiconductor body 9. Underneath the contact holes 15 and 16 there
are located strip-shaped semiconductor regions, which are doped opposite to
9, which regions are indicatea hatched in Figure 3. For purposes of a simple
representation, in Figure 3, their lateral boundaries coincide with the lim
its of the contact holes 15 and 16.
~ etween the line structures 15, 17, and 16, 18, which serve as bit
lines, and which are designed according to the Figures 1 and 2, a wide coat-
ing 19 is applied upon the insulating layer 14, which consists of highly
doped polycrystalline silicon. Within the individual gate o~ide regions 141
through 144, this in each case defines memory electrodes which are components
of memory capacitors. One of the memory capacitors is designated wit,h the
numeral 20 in Figure 3, and is represented hatched. ~ re~ion 21 nelgh~oring
the capacitor 20~ which region 21 is also hatched in Figure 3, represents a
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transfer channel, via which charge carrieru proceed from the line structure
16, lô which serves as a bit line into the capacitor 20, and the reverse.
The transfer channel is covered by a transfer gate which consists of a fur-
ther electrically conducting coating which is applied insulated with respect
to the strips 17, 18 and the coating 19, which coating also is ~ormed out of
highly doped polycrystalline silicon. For a better overvie~7, this coating is
only represented for the memory cells 10 and 11 and is characterized in its
lateral dimensions by means of the dot and dash line 22. Of the coating 22,
in each case only those parts function as transfer gate electrodes which lie
above the zones of the individual memory cells which correspond to the sur-
face 21. ~he transfer gate electrodes which are associated with the memory
cells 10 and 11 are selected via a word line 23, which is placed over an in-
sulating layer which covers the coating 22 and which contacts the coating 22
by means of a contact hole 24 which is provided in this insulating layer.
~he bit lines 15, 17 and 16, 18 are connected via connection lines with read-
and regenerating amplifiers 25 and 26, which serve for the reading out and
regeneration of the information contained in the memory cells as well as
which serve for the reading in again of the regenerated information. For ~he
reading in of information, otherwise, further leads 27 and 28 of the bit
lines 15, 17 and 16, 18 serve.
The coating 19 is finally connected via a lead 29 to a predeter-
mined potential which permits space charge regions to arise under the regions
141 through 144, into which space charge regions, in the conducting state of
the associated transfer channels in each case~ charge carriers which stem
from the bit line penetrate, in a manner which is essentially known, so that
inversion surface barrieræ form. Because of the low re~iutance of t~e ~it
line structures 17 and 189 the transit time of the electric signals which
represent the information from the individual memory cells 10 through 13 to
1 9~ 8
, ..
the reading and regenerating amplifier 25S or respectively~ 26 i8 small that
in relationship to other processes which are relevant for the access time of
a memory~ it is negligible. The transfer gate electrodes which consist of
the parts of the coating 22 which are loc ted over the reeions 21 of the in-
dividual regions 141 through 144 fill the space between the strips 17 and 18
on the one side and the border zones of the coating 19 on the other side such
that they axe self-adJusting with respect to these parts. Therefore, between
the transfer gate electrodes and the parts 17, 18 and 19, no fissures can
arise, the siæe of which could be influenced by the precision oP adjustment
of masks.
In the manufacture of a low resistance line according to the Fig-
ures 1 and 2, one proceeds by covering a doped semiconductor body 1 at an
interface with an electrically insulating layer 2. This layer 2 is provided
with a strip shaped contact hole 3, in the region of which the material of
the layer is removed up to the interface of the semiconductor body. FO11O~J-
ing this, a coating of polycrystalline silicon is applied on the whole sur-
face, which coating is ad~acent to the interface of the semiconductor body 1
within the contact hole 3. In a following doping process, as by a diffusion
or implantation of doping substances, the necessary doping of the polycrys-
talline coating is set. Simultaneously, however, the doping materials whichare used proceed through the coating in the region of the contact hole 3 into
a zone of the semiconductor boay which is hereby redoped, so that a region 5
which is oppositely doped arises, which region proceeds from the contact sur-
~ace of the polycrystalline coating and of the semiconductor body 1. Final-
ly, by means of a photolithographic step which is known, the strip 4 ~Figure
1) is formed by means of etching away of the unnecessary parts of the coat-
ing. With the increasing of the quantity of doping substances which pene~
trate into the region 5, its lower boundaxy is pushed rox~ard lnto the lnte-
3,~ 8
rior of the semiconductor body 1, so that the~ region 5 obtains a larger cross
section and thus has a lower re~istance. In the case of this method of pro-
duction, it is a great advantage that the aoping of the polycrystalline coat~
ing can be dimensioned so large without difficulties that the zone 5 becomes
su~ficiently low in resistance. Other reaoping regions of the semiconductor
body 1 are not generated uith this doping process, so that it does not need
to be broken off because o-f possible smaller dimensions which are desired for
other redoping regions.
The semiconductor memory which is represented in Figure 3 is made
essentially in the followine manner: The doped simiconductor body 9 is first
provided on an interface with an electrically insulating layer 14, which dis-
plays thin layer regions 141 through 141~, whereas outside of the same, it is
designed as a thick oxide layer. Strip shaped contact holes 15 and 16 are
provided in the layer 14. Following this, a coating out of polycrystalline
silicon is applied which in particular extends over the whole surface, which
coating is directly ad~acent to the interface of the semiconductor body 1~
insiae of the contact holes 15 and 16. In a following doping process, dif-
fusion or implantation of doping substances, the necessary doping of the
polycrystalline coating is set. Simultaneously, however, doping substances
proceed into the region of the contact holes 15 and 16 through the coating
into zones of the semiconductor body 9, which are thereby redoped. In this
manner, underneath the contact holes 15 and lS, semiconductor regions arise
which are doped oppositely to the body 9, which regions display a large cross
section in the case of correspondingly stronger doping of the coating and are
therefore of low resistance. Photolithographic steps follow, with which both
the strips 17 and lo as well as the coating 19 which forms the memory elec-
trodes are formed by means of removal of the unnecessary parts of the coat-
ing. ~he structure which is obtained up till now is, following this, covered
~ 6 -
1 ~ 5 8
Nith a further electrically insulating layer, fvr example, out of SiO2, over
which a further coating out o~ polycrystalline silicon is applied especially
over the whole surface. Out of the latter, after a preceding doping7 by
means of further photolithographic steps, the gate structures are formed
Nhich are characterized individually in Figure 3 with 22~ which gate struc-
ture fit in self-adjustingly between the border zones Or the parts 17, 18
and 19 and which cover these over at least on the boundary side. An insulat-
ing layer which is additionally applied~ which covers the structures 22, is
provided with contact holes 24, in which word lines 23 which are placed over
them, ~or example, out of aluminum, contact the structures 22. Finally, the
strips 17, 18 and 19 are provided with connection lines.
It will be apparent to those skilled in the art that many modifica-
tions and variations may be effected without departing from the spirit and
scope of the novel concepts of the present invention.
