Note: Descriptions are shown in the official language in which they were submitted.
1 16~
75, l f
PE~C)Tf,~ [ION_(,IRC ~ [ f (.)l~
NTF,CI A'~ F, ~_C I ~(,tJI'II DV~GI'S
Backyround of he Invention
The present invention relates to a protectinn circuiL for
integrated circuit devices.
In-tegrated circuits are often damaged hy vultaqe transients
which overload one or more individual devices contain~d withirl th~
integrated circuit thereby melting or otherwise destroying the
device. Heretofore, various devices and circuits have heen employcd
for protective p-urposes on integra-ted circuit structures in ord~r to
prevent their destruction by such transients. In the past, diodes
and transistor circuits have been used for internal transient protect;ion.
While such devices provided some measure of protection to the integrated
circui-ts in which they were included, additional protection has been
desired .
Summary of the Invention
The present invention relates to a protection circuit which
provides transient protection for an integrated circuit. The protection
circuit comprises a silicon controlled rec-tifier (SCR) which is
constructed as a two terminal device, preferably as a part of the
integrated circuit which is to be protected. The protection circuit
comprises a PNPN structure in which an insulating layer overlies
the N type region which is intermediate -to two P type regions. A
conductive layer overlies the insulating layer and makes con-tact to
the N type region at the end of the PNPN s-tructure, thereby acting
as the gate of the P channel MOS (PMOS) transistor while simultaneously
acting as one of -the two terminals of the pro-tection circuit. Thus,
if there is a transient which is negative with respect to the P t~lpe
region at the end of the PNPN structure, the PM~S transistor will
be turned on and the protection circuit will act like a diode through
which the current can flow without harm to the protected circuit.
Brief Description of the Drawing
FIG. 1 is a cross-sectional view of the preferred
embodiment of -the present invention; and
FIG. 2 is a schematic model of the invention.
Detai!ed Description of an Exempl~lr~_odime_t
Referring to FIG. I, a cross-sectional view of the proteclion
circuit 10, in accordance with the pre~erred embodiment of the
1 161~BB
present invention, is shown. Thc protection Cilcuit lU is comprise~
of a substrate 12, which is P ~ype silicon materiai in the r)referre(i
embodiment o~ the invention. An N- epitaxial layer L~ forms a I~N
5 junction 16 with the P type substrate 12. A f' type region l8 is
formed within the N type epitaxial layer l9, forming a PN junction 2f)
with the layer 14. An N~ region 22 is formed within the E) Iype
region 18, and it forms a PN junction 24 wil:h the P type region 18
A P-~ region 32 extends from the surface ot` the device 10
10 to make ohmic contact to substrate 12. The P+ region 32 preferably
surrounds the device 10. A conductor 34 contacts the P+ region 32.
An insulating layer 26 overlies the surface of the device 10.
In the preferred embodiment of the invention, the insulating Layer
26 is comprised of silicon dioxide. A conduc-tive layer 28 over]ies the
15 insulating layer 26, overlying -the area where the N- type r egion 1~1
is adjacent the surface of the device 10, and at least partially
overlying the P+ region 32 and the P type region 18. l:'he conductive
layer also extends through an aperture 30 in the insulating layer 26
to make contact to the N+ region 22. The conductive layer 28 and
20 the conductor 34 are typically comprised of aluminum, bwt they may
be comprised of any other suitable material, such as a trimetal system.
Referring now to FIG. 2, a schematic representation 100 of
the protection circuit 10 of FIG. 1, is shown. In the schematic
representation 100, the protection circuit comprises a PNP -transistor
25 Q1, an NPN transistor Q2, a P channel insulated gate field effect
transistor (IGFET) Q3, and a pair ol capacitors C1, C2. 'rransistor
Ql models -the P, N-, P regions 32, 14, 18 of FIG. 1. Accordin(lly,
the emitter, base, and collector of transistor Q1 are referred -to
using reference numerals 132, 114 and 118, respectively, in the
30 schematic represen-tation 100. Similarly, the transistor Q2 represents
the N-, P, and N+ layers 14, 18, 22, respectively, of FIG. 1.
Accordingly, the collector, base, and emitter of transistor Q2 are
represented by the reference numerals 114 (which is also the base
of transistor Q1), 118 (which is also the collector of transistor Q1),
and 122, respectively.
Similarly, the IGFET Q3 includes a drain 118, a source
- 132, and a gate 128 which is also a terminal of the protection circuit
100. The capacitors C1 and C2 model the jwnction capacil:ance ol Lhe
PN junctions 20 and 24 of the strwcture shown in F'lG. 1. 'l`he Iwo
l 1~13~
7'" I fj~J
terminals 128, 13~ of the schematic represenlcllion 1()~ currespon(i to
the two meta~ interconnects 28, 3~, respectively.
The protection circuit is similar in operation ~o a silicon
5 controlled rectifier (SCR) except that it is constructed as a Lwo
terminal device which includes a P channel rGF E~'[' . Also, the
protection circuit is designed to be triggere(l by either a high voltage
across the two terminals 12~3, 134 or by a high rate of change of
voltage (dv/dt) across the two terminals 128, 13~. Acccrdingly,
10 the protection circuit differs from a conventional SCE~ in that a
conventional SCR is a three terminal device which is designed to
avoid triggering based upon either the vo] tage between its anode
and cathode or upon the rate of change of voltage hel:ween its anode
and cathode.
In prac-tice, the cond-uctor 3a, (terminal 13~1) is connected
to ground potential, whereas the conductor 28 (terminal 128) is
connected across the circuitry which is designed to be protected.
Accordingly, if terminal 128 goes negative with respect to ground at
a high rate, the protection circuit will be -turned on (terminals 128
20 and 134 will be electrically connected together) causing excess
current to be passed to ground. Unlike the present protection
device, a conventional SCR would have a low value resistor across
capacitor C2 which would prevent such firing. In the event that
there is a slow change of the voltage on terminal 128, a very small
25 current, on the order of nanoamps, will flow through transistor Q2
without causing the circuit to latch, because the total loop gain is
selected to be less than ]. When the voltage on terminal 128 is
negative enough, ~GFET Q3 will turn on causing transistor Q2 to
turn on thereby providing sufficient loop gain to insure that -the
30 to-tal loop gain is greater than 1. Again, the pro-tection circuit will
pass excess current to ground
In order to manufacture the device of the present invention,
one starts with a semiconductor substrate, preferably of P type (100)
silicon having a resistivity of about 10 to 30 ohm-cm. An N type
35 epitaxial layer having a resistivity of about 1000 ohms/square is then
grown to a thickness of between about 10 and 12 microns. Next, a
layer of photoresist is applied over the surface of the device.
I'he photoresisl: is tlefined using a photomask and dev( lop~
to form openings through which a suit.lt)lt P type (lopanl, such as
. 31~968
, ~
boron nitride, is deposiled and dirlused l;o form Ihe l'-~ isolaliorl
regions 32. I'he P+ isolatk)n regions 32 have a surface concluctivify
of about 5 ohms/square, and they contac~ the substrate l2 after
5 diffusion. Nex-t, a new photoresist layer is applied and defined usiny
a second photomask to form an opening where the P ~ype re0ion l8
will be formed. A suitable acceptor impurity is deposited (either
directly or by ion implantation), and it is diEfused to ~orm the P type
reyion 18 to a depth of approximately 2.l to 2.2 micrometers. rlhc
10 P type region 18 will preferably have a surface resi~tiviî:y ol about
200 ohms/square.
In a similar manner the N+ region 22 is formed using 3
third photomask and photolithographic step. t)onor impurities are
deposited and diffused to form the region 22 with a surface resistivity
15 of approximately 2-5 ohms/square.
Next, the oxide layer 26 is grown and openings are defined
and formed therein using another photolithographic step.
Finally, a conductive layer 28 such as an aluminum layer,
is applied to the surface of the device. The conductive layer 28 is
20 defined using a fourth photolithographic step, therehy completing the
formation of the device 10.
