Note: Descriptions are shown in the official language in which they were submitted.
t 162327 Case 556~4
This is a division of copending Cana~ian Patent Application
Serial Number 366,713, filed December 12, 1980.
The present invention relates to a diode and a
ROM or EEPROM device utilizing same. More specif-
ically, the present invention relates to a diode
which utilizes an amorphous alloy including silicon
and fluorine. In this respect, reference is made
to U.S. Patent No. 4,217,374 Stanford R. Ovshinsky
and Masatsugu Izu entitled: AMORPHOUS S~MICON-
DUCTORS EQUIVALENT TO CRYSTA~LINE SEMICONDUCTORSand U.S. Patent No. 4,226,898 Stanford R. Ovshinsky
and Arun Madan, of the same title.
Silicon is the basis of the huge crystalline
semiconductor industry and is the material which is
! utilized in substantially all the commercial inte-
grated circuits now produced. When crystalline
semiconductor technology reached a ~ommercial state
it became the foundation of the present huge semi-
conductor device manufacturing industry. This was
due to the ability of the scientist to grow sub-
stantially defect-free germanium and particularly
silicon crystals, and then turn them into extrinsic
materials with p-type and n-type conductivity re-
-gions therein. This was accomplished by diffusing
into such crystalline material parts per million of
donor (n) or acceptor (p) dopant materials intro-
--1--
` ` 1 162327
duced as substitutional impurities into the sub-
stantially pure crystalline materials, to increase
their electrical conductivi~y and to control their
being either of a p or n conduction type.
The semiconductor fabrication processes for
making p-n junction crystals involve extremely
complex, time consuming, and expensive procedures
as well as high processing temperatures. Thus,
these crystalline materials used in rectifying and
other current control devices are produced under
very carefully controlled conditions by growing
individual single silicon or germanium crystals,
and where p-n junctions are required, by doping
,
such single crystals with extremely small and crit-
ical amounts of dopants. These crystal growing
processes produce relatively small crystal wafers
upon which the integrated memory circuits are form-
ed.
In wafer scale integration technology the
small area crystal wafer limits the overall size of
the integrated circuits which can be formed there-
on. In applications requiring large scale areas,
such as in the display technology, the crystal
wafers can not be manufactured with as large areas
,...................... .
1 162327
as required or desired. The devices are foemed, at
least in part, by diffusing p or n-type dopants
into the substrate. Further, each device is formed
between isolation channels which are diffused into
the substrate. Packing density (the number of
devices per unit area of wafer surface) is also
limited on the silicon wafers, because of the leak-
age current in each device and the power necessary
to operate the devices, each of which generate heat
which is undes;rable. The silicon wafers do not
readily dissipate heat. Also, the leakage current
adversely affects the battery or power cell life-
time in portable applications.
Further, the packing density is extremely
important because the cell size is exponentially
related to the cost of each device. For instance,
a decrease in die size by a factor of two results
in a decrease in cost on the order of a factor of
six. A conventional crystalline ROM utilizing two
micron lithrography has a bipolar cell size of
about .3 to .5 mil2 or a MOS cell size of about .2
to .3 mil2.
In summary, crystal silicon rectifiers and
integrated circuit parameters are not variable as
1 162327
desired, require large amounts of material, high
processing temperatures, are only producible only
on relatively small area wafers and are expensive
and time consuming to produce. Devices based upon
amorphous silicon can eliminate these crystal sil-
icon disadvantages. Amorphous silicon can be made
faster, easier, at lower temperatures and in larger
areas than can crystal silicon.
Accordingly, a considerable effort has been
made to develcp processes for readily depositing
amorphous semiconductor alloys or films each of
which can encompass relatively large areas, if
desired, limited only by the size of the deposition
equipment, and which cou~d be doped to form p-type
and n-type materials to form p-n junction rec-
tifiers and devices superior in cost and/or opera-
tion to those produced by their crystalline coun-
terparts. For many years such work was substan-
tially unproductive. Amorphous silicon or ger-
manium ~Group IV) films are normally four-fold
coordinated and were found to have microvoids and
dangling bonds and other defects which produce a
high density of localized states in the energy gap
thereof. The presence of a high density of local-
..j
~ 162327
ized states in the energy gap of amorphous siliconsemiconductor films resulted in such films not
being successfully doped or otherwise modified to
shift the Fermi level close to the conduction or
valence bands making them unsuitable for making p-n
junction rectifiers and other current control de-
vice applications.
In an attempt to minimize the aforementioned
problems involved with amorphous silicon and germa- !
nium, W.E. Spear and P. G. Le Combe~ of Carnegie
Laboratory of Physics, University of Dundee, in
Dundee, Scotland did some work on "Substitutional
~oping of Amorphous Silicon", as reported in a
paper published in Solid State Communications, Vol.
17, pp. 1193-1196, 1975, toward the end of reducing
thé localized states in the energy gap in amorphous
silicon or germanium to make the same approximate
mor~ closely intrinsic crystalline silicon or ger-
manium and of substitutionally doping the amorphous
materials with suitable classic dopants, as in
doping crystalline materials, to make them ex-
trinsic and of p or n conduction types.
The reducticrl of the localized states was
accomplished by glow discharge deposition o~ amor-
J 162327
phous silicon films wherein a ~as o~ silane ~SiH4)was passed through a reaction tube where the gas
was decomposed by an r.f. glow discharge and de-
posited on a substrate at a substrate temperature
of about 500-600K (227-327C). The material so
deposited on the substrate was an intrinsic amor-
phous material consisting of silicon and hydrogen.
To produce a doped amorphous material a gas of
phosphine (PH3) for n-type conduction or a gas of
diborane (B~H6) for p-type conduction were premixed
with the silane gas and passed through the glow
discharge reaction tube under the same operating
! conditions. The gaseous concentration of the dop-
ants used was between about 5 x 10-6 and 10-2 parts
per volume. The material so deposited included
supposedly substitutional phosphorus or boron dop-
ant and was shown to be extrinsic and of n or p
conduction type.
While it was not known by these researchers,
it is now known by the work of others that the
hydrogen in the silane combines at an optimum tem-
perature with man~ of the dangling bonds of the
silicon during the glow discharge deposition, to
substantially reduce the density of the localized
1 162327
states in the energy gap toward the end of making
the electronic properties of the amorphous material
approximate more nearly those of the corresponding
crystalline material.
D.I. Jones, W.E. Spear, P.G. LeComber, S. Li,
and R. Martins also worked on preparing a-Ge:H form
GeH4 using similar deposition techniques. The
material obtained gave evidence of a high density
of localized states in the energy gap thereof.
Although the material could be doped the efficiency
was substantially reduced from that obtainable with
a-Si:H. In this work reported in Philsophical Maga-
p zine B, Vol. 39, p~ 147 ~1979) the authors conclude
that because of the large density of gap states the
material obtained is". . . a less attractive mate-
rial than a-Si for doping experiments and possible
applications."
; The incorporation of hydrogen in the above
silane method not only has limitations based upon
the fixed ratio of hydrogen to silicon in silane,
but, most importantly, various Si:H bonding confi-
gurations introduce new antibonding states which
can have deleterious consequences in these mate-
rials. Therefore, there are basic limitations in
.~
1 162327
reducing the density of localized states in these
materials which are particularly harmful in terms
of effective p as well as n doping. The resulting
density of states of the silane deposited materials
leads to a narrow depletion width which in turn
limits the efficiencies of devices whose operation
depends on the drift of free carriers. The method
of making these materials by the use of only sil-
icon and hydrogen also results in a high density of
surface states which affects all the above para-
meters.
After the development of the glow discharge
deposition ~f silicon from silane gas was carried
! out, work was done on the sputter depositian of
amorphous silicon films in the atmosphere of a
mixture of argon (required by the sputtering de-
position process~ and molecular hydrogen, to deter-
mine the results of such molecular hydrogen on the
characterist~cs of the deposited amorphous silicon
film. This research indicated that the hydrogen
acted as a compensating agent which bonded in such
a way as to reduce the localized states in the
energy gap. However, the degree to which the lo-
calized states in the energy gap were reduced in
--8--
1 162327
the sputter deposition process was much less than
that achieved by the silane deposition process
described above. The above described p and n dop-
ant materials also were introduced in the sput-
tering process to produce p and n doped materials.These materials had a lower doping efficiency than
the materials produced in the glow discharge pro--
cess. Neither process produced efficient p-doped
materials with sufficiently high acceptor concen-
trations for producing commercial p-n junction
devices. The n-doping efficiency was below desir-
able acceptable commercial levels and the p-doping
was particularly undesirable since it increased the
number of localiæed states in the band gap.
Heretofore various semiconductor materials,
both crystalline and amorphous, have been proposed
for utilization in rectifying type devices such as
a diode. Also it has been proposed to make a semi-
conductor or a photoconductive rectifier utilizing
an amorphous alloy including silicon and fluoride.
U.S. Patent No. 4,217,374, issued August 12, 1980
for Amorphous Semiconductor Equilvalent to Crys-
talline Semiconductor, Stanford R. Ovshinksy and
Masatsugu Izu and U.S. Patent No. 4,226,898, issued
1 162327
October 7, 1980 of the same title, Stanford R.
Ovshinsky and Arun Madan.
As will be described in greater detail here-
inafter, the diode of the present invention con-
tains the amorphous alloy including silicon andfluorine disclosed in the applications indentified
above in a specific construction of a diode having
at least two regions with at least one region con- ;
taining the amorphous alloy in combination with ROM
or EEP~OM device constructions.
A typical ROM device includes a matrix of X
and Y axis conductors which are insulated from each
1 other and which have a memory circuit at and cou-
pled between each cross over of an X axis conductor
over a Y axis conductor. Each memory circuit in-
cludes a memory region and an isolating device such
as a transistor or a diode. Typically, such tran-
sistors and diodes have been formed in semicon-
ductor substrates with permanently open contact
points or permanently closed contact points for
establishing logic 1 or logic 0 bits of information
which are stored in the ROM device. Such a ROM
device is programmed during the manufacture there-
of.
--10--
1 1~2327
EEPROM ~electrically erasible programma~le
read only memory) devices have been proposed where-
in a vertically disposed memory region or cell in
the memory circuit is vertically coupled at and
between an upper X axis conductor and a lower Y
axis conductor in a memory matrix. These devices
follow from the storing of information with phase
change switch devices first invented by Stanford R.
Ovshinsky, as for example, disclosed in U.S. Patent
3,271,591.
We have found that these disadvantages may be
ovércome ~y providing a diode having at least first
and second abutting regions forming a junction
therebetween wherein the ~irst region is made from
an amorphous alloy including silicon and fluorine.
We also provide ROM and EEPROM devices utilizing
these diodes as isolating means for coupling the
memory regions thereof to the cross over points of
a memory matrix. The packing density of the ROM
and EEPROM devices, utilizing two micron lithog-
raphy for reference, is on the order of .1 mil2 per
cell. Also, the devices and diodes are all thin
film deposited and have low leakage currents allow-
ing the structure to be stacked upon one another to
further increase the packing density.
`~ ~62327
,
Further, according to the invention, there is
provided in an EEPROM device having memory circuit
means at each cross over point of a conductor of a
first group of conductors extending in a f~rst
direction over a conductor of a second group of
conductors extending a second direction traversin~
the first direction, the first group of conductors
being insulated from the second group of conduc~ors
and each memory circuit means being coupled to and
between a pair of crossin~ over conductors at one
of the cross over points and including isolating
means, the improvement residing in the isolating
means including a diode having at least a irst
region and a second region, the regions abutting
each other to form a junction therebetween and the
first region being made of the amorphous alloy
including silicon and fluorine.
Preferably, the amorphous alloy also contains
hydrogen and such amorphous alloy is a-Sia Fb Hc,
where a is bewteen 80 and 98 atomic percent, b is
between O and 10 atomic percent and c is between O
and 10 atomic percent.
The first alloy region is doped with an N
dopant material chosen from an element of Group V
; - 12 -
I 162327
.
of the Periodic Table, e.g., phosphorous, arsenic
or others by an amount constituting between a few
parts per million (ppm) and five atomic percent and
preferably between 10 to 1000 parts per million.
The second region can be a metal, metal alloy,
a metallic like material having a high barrier
height on the first region so as to create a Schottky
barrier.
Alternately, the second region also can be an
1~ amorphous alloy includin~ silicon and fluorine and
preferably also containing hydrogen~ The second
alioy region is doped with a P dopant material
chosen from an element of Group III of the Periodic
Table, e.g., boron, aluminum or others by an amount
constituting between a few parts per million and
five atomic percent, and preferably between 10 and
1000 parts per million. Also, the first region
could be a P type region with the second region
being an N type region.
The packing density utilizing two micron li-
thrography for reference in the thin film ROM and
all thin film EEPROM is on the order of .1 mil2 per
cell. Further, due to the all thin film deposited
structure and the low leakage current the devices
can be stacked upon one another to further increase
., .
- 13 -
` . J 162327
the packing density. The devices can be formed on
various substrates including insulated metal which
is utilized as a heat sink for the devicesO
The preferred embodiments of this invention
will now be described, by way of example, with
reference to the drawings accompanying this speci-
fication in which:
Fig. 1 is a fragmentary plan view of the de-
posited film side of a substrate which forms a
support for an all deposited film ROM device in-
cluding a diode made in accordance with the teach-
ings of the present invention.
Fig. 2 is a sectional view through the memory
circuits of the ROM device shown in Fig. 1 and is
taken along line 2-2 of Fig. 1.
Fig. 3 is a schematic circuit diagram of the
memory circuit shown in Fig. 2.
Fig. 4 is a fragmentary plan view of the de-
posited film side of a substrate forming a support
for an all deposited thin film EEPROM device in-
cluding memory circuits, each of which include a
diode constructed according to the teachings of the
present invention.
- ~4 -
~ 162327
Fig. 5 is a sectional view through two memory
circuits shown in Fig. 4 and is taken along line 5-
5 Of Fig. 4-
Fig. 6 is a schematic circuit diagram of the5 memory circuit shown in Fig. 5.
Fig. 7 is a sectional view through a second
embodiment of deposited thin film ROM device in-
cluding a Schottky diode device made in accordance
with the teachings of the present invention.
Fig. 8 is a schematic circuit-diagram of the
memory circuit shown in Fig. 7.
Referring to ~igs. 1 and 2 there is illus-
tratea thereln a ROM device 10 including two dedi-
cated memory circuits ll and 12 each of which in-
cludes a thin film diode or rectifying device 14tFig. 2) constructed in accordance with the teach-
ings of the present invention. The memory circuit
11 is a closed circuit which includes the diode 14
which is coupled through an ohmic contact region
such as a platinum silicide region 16 to an upper X
axis conductor 18 and to a lower Y axis conductor
20.
The memory circuit 12 also includes a diode 14
which is connected on one side to another Y axis
l 162327
conductor 20' and on the other side is open cir-
cuited by reason of a region of insulating material
21 disposed between the upper surface of diode 14
and the X axis conductor 18 as will be described in
greater detail below.
In the construction of the ROM device 10,
there is deposited on any suitable substrate 22
having an insulating top surface 25, parallel con-
ductors 20 and 20' which form the Y axis conductors
and which form a compatible interface with the
diode 14. The conductors or bands 20 of conductive
material may be made of aluminum, chromium, molyb-
denum, an alloy of titanium and tungsten (Ti-W) or
the like. Also, the conductive bands 20 may in-
clude a bottom layer 23 of a highly conductivematerial like aluminum and an upper layer 24 of a
refractory barrier-forming material like molybdenum
or Ti-W. The conductive layers 23 and 24 may be
formed by conventional vacuum deposition, photo
resist masking and etchant techniques.
Next, spaced layers 26 and 28 of amorphous
semiconductor alloy including silicon and fluorine
are deposited over the conductor bands 20 to form
the thin film diodes 14 at each cross over point in
- 16 -
I 162327
the matrix of X and Y axis conductors 18 and 20 in
the ROM device 10. Each such P-N junction diode 14
may be formed from doped N+ and P+ amorphous alloy
layers 26 and 28 as shown.
An insulating layer 30, such as silicon diox-
ide, is applied over the entire substrate 22 so as
to form the insulating region 21 above the diode 14
- ln the memory circuit 12. However, wherever it is
- desired to store a data bit which will be indicated
by a low resistance condition coupled through the
diode 14, an opening 31 is formed in the insulating
layer of silicon dioxide.
The platinum silicide or ohmic contact region
16 can be formed on the outermost amorphous silicon
layer 28, where the opening 31 had been formed in
: the insulating layer 30, such as by applying plati-
num over the exposed portions of the amorphous
alloy layer 28. The rectifier diodes 14 then can
have a conductor band 32 formed thereover of a
barrier-forming material such as molybdenum or the
Ti-W allo~. Subsequently, a band of aluminum is
deposited over the conductor band 32 to form the X
axis conductor 18. Alternately, the conductor 18
can be deposited over the layer 28 and the in-
sulator 30 without the barrier 32.
- 17 -
1 162327
~,
~ rom the foregoing description, it will be
seen that the memory region of each memory circuit
11 and 12 is a predetermined conductive path or a
predetermined insulator path between the Y axs
conductor 20 through the diode 14 to the X axis
conductor 18.
Also, it will be apparent that the memory
regions are formed by depositing a thin film of
insulating material 30 on one region 28 of each
diode 14-followed by depositing a thin film band
(band 32 and/or 18) of conductive material to form
the X axis conductor 18. For a conductive path
' memory region, the insulating film layer 30 is cut
or etched away such a~ a,t 31 in the area above the
one region 28 of a selected diode 14 before the
thin film conductive band is deposited so that the
conductive path is a direct contact o~ the con-
ductive band 18 with the first region 28 of the
selected diode 14.
Also, it is apparent, that each memory circuit
11 or 12 coupled to and between a pair of cross,ing
over conductors 18 and ~0 includes not only a con- -
ductive path or insulator path memory region but .
also the diode 14 having a first region 26 and a
., .
- 18 ~
I 162327
second region 28 which abut each other to form a
junction therebetween and with at least the first
region 26 being made of the amorphous alloy in-
cluding silicon and fluorine. In the illustrated
5 embodiment in Fig. 2 the second region 28 is also
formed of amorphous alloy including silicon and
fluorine.
Also, in each memory circuit 11 and 12, the
. memory region is aligned with the regions 26 and 28
14 f the diode 14 and all of the regions are iuxta-
posed and are situated on a line substantially
perpendicular to, and extending between each pair
of cross-over conductors 18 and 20 at the cross-
over thereof to provide a very small center-to-
center distance between adjacent memory circuits 11and 12 thereby to provide a very high packing den-
sity of memory circuits 11 and 12 in the ROM device
10 on the order of .1 mil2.
In accordance with the teachings of the pre-
sent invention, the amorphous alloy includiny sil-
icon and fluorine also preferably contains hydrogen
and is preferably an a-Sia:Fb:Hc alloy, where a is
between 80 and 98 atomic percent, b is between 0
and 10 atomic percent and c is between 0 and 10
-- 19 --
l 162327
atomic percent.
The alloy layers 26 and 28 can be between 500
and 20,000 angstroms, one thickness utilized being
1000 angstroms.
The first region or layer 26 can be doped with
an N type dopant material chosen from an element of
Group V of the Periodic Table such as phosphorous
or arsenic in an amount between a few parts per
million and 5 atomic percent and preferably in an
amount constituting 10 to 1000 parts per million.
Alternatively, the first region 26 can be doped
with a P type dopant material chosen from an ele-
ment of Group III of the Periodic Table such as
boron or aluminum in an amount constituting between
a few parts per million and 5 atomic percent and is
preferably doped in an amount constituting 10 to
1000 parts per million.
Alternatively, the second region 28 can be a
metal, a metal alloy or a metallic like material
having a high barrier height on the first region 26
so as to create a Schottky barrier. There also can
be an insulator layer forming an MIS (metal insu-
lator semiconductor) interface.
; - 20 -
` ` 1 162327
Further, as another alternative, the second
region 28 can be doped with a material chosen from
an element of Group III of the Periodic Table or
with an element of Group V of the Periodic Table.
Still further, one of the regions could be made of
a material dissimilar to the amorphous alloy such
as to form a heterojunction rectifying device.
In any event, with the thin film diode 14
having at least one region made of the amorphous
alloy included in the memory circuit 11 a ROM de-
vice 10 is provided which has a low resistance and
high conductivity in the forward biased direction
and a very high resistance in the reverse biased
direction.
~5 A schematic circuit diagram of the closed
memory circuit ll and the open memory circuit 12 is
shown in Fig. 3 of the drawing.
Referring now to Figs. 4 and 5, there i5 il-
lustrated therein an EEPROM device 50 and more
specifically, two memory circuits 52 thereof which
are made in accordance with the teachings of the
present invention. As shown, each memory circuit
52 includes a memory region 56 made of a reversible
resettable memory material as will be described in
- 21 -
~ 162327
more detail hereafter connected ;n series with a
thin film diode 58 between an upper X axis con-
ductor 60 and lower Y axis conductors 62 and 62'.
Referring to Fig. 5, it will be readily appar-
S ent that the memory region S6 and the diode 58 arejuxtaposed to each other on a line substantially
perpendicular to the crossing over conductors 60
and 62 such that the memory circuit 52 formed by
each of the memory region 56 and diode 58 have a
minimum cell area thereby to provide a maximum
packing density of memory cells or memory circuits
56 in the EEPROM device 50.
In the construction of the EEPROM device 50, a
substrate 64 such as a metal substrate is provided
on which a layer of insulating material 66 is de-
posited such as by thin film depositing technique.
v Then parallel bands of conductive material such as
metal are laid down to form the Y axis conductors
62.
In accordance with the teachings of the pre-
sent invention, the P-N junction diode 58 is made
of layers of amorphous alloy conductive film 68 and
70 deposited on top of the Y axis conductor bands
60. The isolating diode S8 is formed from success-
- 22 -
I 162327
fully doped N+ and P+ layers or regions 68 and 70
of amorphous alloy. After these layers have been
deposited a layer 72 of insulating material such as
silicon dioxide material is deposited over the
5 substrate 66 and the layers 62, 68 and 70 thereon.
Next, an open space 74 is cut or etched out of
the layer of insulating material in the area above
the upper layer 70 of the diode 58. Preferably, a
platinum silicide or ohmic contact region 76 is
formed in the upper layer 70 which is exposed through
the opening 74 in the manner described above for
forming region 16 in ROM device 10.
Then, a thin film of phase change reversible
amorphous material is deposited to form memory
region 56. Next a thin layer 80 of refractory
barrier-forming material like molybdenum or a Ti-W
alloy is deposited on the insulating layer 72 and
over the memory region 56. Next, a thicker layer
60 of conductive material such as aluminum is de-
posited in a band over the refractory barrier-
forming layer 80 to form the X axis conductor 60.
The platinum silicide region 76 can form an ohmic
contact or a Schottky barrier interface with the
doped outer layer 70.
I 162327
As provided in the construction of the ROM
device lQ described above and in accordance with
the teachings of the present invention~ the diode
58 has at least the first region or layer 68 and a
second region or layer 70 which abut each other to
form a junction therebetween with the first region
68 being made of the amorphous alloy.
The second region or layer 70 can also be made
of the amorphous alloy and which can be doped with
a different dopant material than the material with
which the layer 68 is doped. Alternatively, region
70 could be made o a metal, a metal alloy or a
metallic like material having a high barrier height
on the first region 68 so as to create a Schottky
barrier, when the first region 68 is doped with a
dopant material chosen from an element of Group V
of the Periodic Table. Such a metal can be from
the group consisting of gold, platinum, palladium
or chromium.
Also, the second region 70 can be made of a
material dissimilar to the amorphous material o
the first region 68 such as to form a heterojunc-
tion. The first region can be N or P doped and the
second region can be P or N doped.
.~
- 24 -
` ` ~ 162327
A preferred amorphous alloy is a-Sia:Fb:Hc,
wherein a is between 80 and 98 atomic percent, b is
between 0 and 10 atomic percent and c is between 0
and 10 atomic percent. The dopant material also
can be chosen from elements of Group V of the Peri-
odic Table such as phosphorus or arsenic and can
constitute between a few parts per million and 5
atomic percent of the region 68 or 70 and prefer-
ably 10 to 1000 parts per million.
The second region or layer 70 can then be the
amorphous alloy as is the first region 68. Then,
such material can be doped with a dopant material
chosen from an element of Group III of the Periodic
Table and can constitute between a few parts per
million and S atomic percent of the region 70.
Such a dopant material can be boron or aluminum and
constitute 10 to 1000 parts per million of the
region 70. It will be apparent, of course that the
doping of the regions 68 and 70 can be reversed if
desired. Also, in accordance with the teachings of
the present invention, the regions are laid down as
- deposited thin films.
The memory regions 56 are aligned with the
regions 68 and 70 of t~e diode 58 and all of these
- 25
.` ` 1 162327
regions are juxtaposed and situated on a line sub-
stantially perpendicular ~o and extending between a
pair of cross~over conductors 60 and 62 at a cross-
over thereof to provide a very small center-to-
center distance between adjacent memory circuits 52thereby to provide a very high packing density of
such memeory circuits 52 in the EEPROM device 50.
Also, both the memory region and the diode region
are thin film depositions.
Further, the memory regions 56 comprise a
reversible, phase change material which can be set
in a highly conductive state or a highly non-con-
ductive state. More specifically, the memory re-
. gion 56 is formed of a material which is initially
amorphous and which can be changed by a set voltage
and current to a crystalline conductive state and
then reset by a reset voltage and current to an
amorphous insulator state. One preferred material
from which memory region 56 can be made includes
german;um and tellurium such as Ge20Tego~ This
material has a good reversibility of up to 106
cycles, a maximum processing temperature of approx-
imately 200C, a maximum storage temperature of
100C, a threshold voltage of 8 volts, a SET resis-
.. . ..
- 26 -
I 162327
. .
.
tance of 300 ohms and OFF resistance (at 175C) of
approximately 104 ohms.
The memory region can comprise a memory struc-
ture situated between one of the conductors 60 and
62 and one region 68 or 70 of the diode 58 with the
memory structure comprising first, second and third
regions. The first region is adjacent to the one
conductor 60 or 62 or to the one region 70 or 68,
whichever is adapted to be coupled to a positive
vol~age source.
The second region is situated between the
first and third regions and the third region is
adjacent the one region 70 or 68 or the one con-
ductor 62 or 60, whichever i8 adapted to be coupled
lS to a negative line of the voltage source and com-
- pletely separates the second region from the con-
nection to the negative line.
The second region is formed of a tellurium
based chalcogenide which has higher electrical
resistance in its amorphous state and lower elec-
trical resistance in its crystalline state and can
be switched from one state to another upon appli-
cation to the conductors of an electrical signal of
appropriate value.
.`` ``` 1 162327
. , .
The first region is formed of a material hav-
ing a higher percentage of tellurium than the sec-
ond region. The third region is formed of a mate-
rial having between 25 and 46 atomic percent ger-
manium with the remaining material being substan-
tially tellurium.
Preferably, the third region contains approx-
imately 33 atomic percent germanium and the second
region can contain between 10 and 25 atomic percent
germanium and preferably between 15 and 17 percent
germanium.
Also, preferably, the first region contains at
least 90 atomic percent tellurium.
A schematic circuit diagram of the EEPROM
memory circuits 52 is illustrated in Fig. 6 of the
drawing.
- Fig. 7 illustrates a ROM device 100 similar to
that illustrated in Fig. 2 with a Schottky barrier
rectifying device in a closed cell 102. An open
cell lC4 can be formed substantially indentical to
the cell 12 except for the diode 14 as shown in
Fig. 8. The device 100 is formed on a substrate
106 which has an insulating layer 108 formed there-
on. Bottom or Y axis conductors 110 are formed on
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` I 162327
the layer 108 as before described~
Referring to the cell 102, a heavily doped
amorphous alloy contact layer 112 is formed on the
conductor 110. An intrinsic or slightly doped
alloy layer 114 of the same conductivity type is
formed on the layer 112.
An insulator layer 116 is then formed over the
cells 102 and 104 with an opening 118 etched or cut
through the layer 116 for each closed cell 102. A
Schottky barrier 120 is then formed on the alloy
114, such as the barrier 16 described in Fig. 2. A
top X axis conductor 122 is formed over the cells
102 and 104 as previously described. The Schottky
barrier 120 then forms the cell rectifying device
instead of the P-N junction described in Figs. 2 or
5.
A schematic circuit diayram of the ROM closed
cell 102 and open cell 104 is illustrated in Fig. 8
of the drawing. The open cell 104 does not have a
rectifying device 120 since the insulating material
116 is deposited on the alloy layers.
Both the ROM device 10 and the EEPROM device
50 can be deposited on an insulating layer of mate-
rial which has first been deposited on a metal
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I 162327
., .
substrate, which metal substrate can form a heat
sink and facilitate stacking and heat dissipation
of one ROM device on top of another ROM device or
an EEPROM device on top of another EEPROM device.
Also, if desired, the edges of the metal substrate
or substrates can have a heat radiating fin for-
mation thereon for further facilitating heat dis-
sipation.
Of course, metal substrates are not essential
and the ROM devi~e 10 or ~EPROM device 50 utilizing
same have a number of advantages, some of which
have been described above and others of which are
inherent in the invention. Such diodes and memory
regions that form memory circuits in a ROM or EEPROM
device can be easily deposited by thin film de-
position techniques on a substrate and the devices
can be stacked to make a three dimensional memory
system. Also, a diode made of two regions of this
material, one N doped and one P doped, has a low
forward bias resistance and a high reverse bias
resistance.
The diode takes u~ a minimum of space in that
it is made by thin film deposition techniques with
the amorphous alloy. Such a diode in combination
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1 162327
with a memory region in a ROM device or an EEPROM
device takes up a very small space such that the
memory circuit or memory cell density can be as low
as 0.1 mil2 with a center-to-center distance be-
5 tween adjacent memory cells or circuits of 8 mi-
crons utilizing two micron lithography. In conven-
tional bipolar ROM's, each cell is isolated between
a pair of junction diffusion channels. Material to
be diffused is deposited two microns wide, but the
high temperature process diffuses the material into
the substrate. As a result the channels are from
our to six microns wide, have a rectifier width of
about two microns with six to eight microns allowed
between the channels and the rectifier. This re-
sults in a bipolar ROM center-to-center distance of
about eigh~een microns and a cell density of about
.5 mil2.
Utilizing oxide isolation the rectifiers can
be formed, in a best case, adjacent or overlapping
the channel's; however, the channels are eight to
ten microns wide. This results in a center-to-center
distance of about twelve microns and a best cell
density of about .25 mil2.
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` 1 162327
The decrease in cell density from .25 mil2 to
.1 mil2 is a very significant cost reduction. Al-
though the conventional junction and oxide isola-
tion ROM's can be reduced in size as photolithog-
raphy techniques are improved, the corresponding
reduction will also take place in the ROM's and
EEPROM's utilizing the thin film diode of the in-
vention.
Certain embodiments disclosed in this application
are also disclosed and claimed in the parent application
filed under Serial Number 366,713 and a further divisional
application filed on even date.
.
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