Note: Descriptions are shown in the official language in which they were submitted.
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IMAGE PROCESSING INTEGRATED CIRCUIT
FIELD OF THE INVENTION
This invention relates to image processing devices and
more particularly to an integrated circuit device which
processes images and produces quantized black and white
output video signals representative of the image scanned
by the array.
BACKGROUND OF THE INVENTION
Present techniques for obtaining quantized video
signals require multiple processing functions, each
implemented by a combination of discrete and integrated
circuits. The ability to extract a quantized video signal
from degraded printing varies greatly between data lift
systems, but is generally a function of the sophistication
of the system.
SUMMARY OF THE INVENTION
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The invention provides an effective and economical way
to transform an optical image of a printed character or
other symbols to an electrical signal which is quantized
to represent black and white levels. This type of quantized
signal is required by almost all optical character recog-
nition systems utilized in optical character recognition
equipment. The device described may be utilized, for
example, in a hand-held OCR reader to supply signals
representing the character to the recognition logic. The
system consists of a pulsed infrared emitting diode illumin-
ation source and an integrated circuit which includes both
an image sensor and an analog signal processing section.
The optical image projected onto the sensor is transformed
into a stream of digital video data representing black or
white levels.
In accordance with an aspect of the invention there is
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provided an image processing system including an image
sensor for producing image data in the form of black and
white pixels, a video processor, and a decision circuit for
pr.oducing black or white decisions for each pixel, character-
ized in that the video processor has parallel processing
channels, one channel performing edge enhancement of the
iMage data and the other channel being a contrast ratio
detector which determines if a pixel is dark enough to
exceed a minimum acceptable level, and a circuit for
combining the outputs of said parallel channels prior to
making the black or white decision.
DESCRIPTION OF THE DRAWINGS
The features of the invention and the technical advance
represented thereby will be more fully understood when
considered in conjunction with the following specification,
claims and drawings in which:
Figure 1 is a block diagram of a prior art circuit;
Figure 2 is a block diagram of the present invention;
Figure 3 illustrates the sensor array;
Figure 4 is a schematic diagram of the sensor array;
Figure 5 is a schematic diagram of the 96 stage CCD
array spatial filter illustrated in Figures 2 and 3;
Figure 6 is a schematic diagram of the 115 stage CCD
array used for the white reference detector illustrated in
Figure 2;
Figure 7 illustrates the 7 x 7 background detector
matrix;
Figure 8 illustrates the sample point configuration
within the 7 x 7 matrix of Figure 7;
3~ Figure 9 is a schematic diagram of the black reference
circuit;
Figure 10 illustrates the spot filter image matrix shown
in Figure 2; and
Figure 11 is a timing diagram of the black/white video
si,gnal.
Figure 12 is a flow diagram of the major timing sequence.
Figure 13 is a block diagram of the relation ratio for
internal and external clocks.
DESCRIPTION OF THE PREFERRED EMBODIMENT
A fairly complex system which has good thresholding
characteristics with degraded printing is shown in block
form in Figure 1. The serial video signal from the single
output port of an array of photosensitive elements 50 is
first amplified by a preamp 52 in order to transmit it
through an integrator 54. The signal is sampled 56 at the
end of the integration, and then converted to a 4 bit
digital signal by the analog/digital converter 58. The AGC
function 60 serves to normalize the A/D output, always
producing 16 gray levels for a range of video input levels.
The purpose of the converter 58 is to drive the correlator
function 62. The correlator 62 is a digital filter that
quantizes a 4 bit input signal to a black or white level
based upon the sum of the cells surrounding a cell.
Approximately 20 MSI and SSI logic packages are required to
implement the control function 64 and timing signals 66, 68,
70 that tie all;the functions together.
The present invention has equal or greater thresholding
characteristics and can be implemented in a single
integrated circuit. This integrated circuit with several
external components, replaces all the functional blocks
shown in Figure 1.
Image processing systems similar to Figure 1 are
described in U.S. Patents 3,947,817, 3,964rO22 and 4,075,605.
The system is a data lift system that consists of a
pulsed infrared emitting diode illumination source (not
illustrated) and an integrated circuit comprising both an
image sensor and an analog signal processing section. A
block diagram of the system is illustrated in Figure 2. An
optical image projected onto the sensor array 80 is trans-
formed into a stream of digital video data representing
black or white levels. The sensor array 80 may be, for
example, area sensor 18 cells wide and 70 cells tall ~Figure
3)~ The sensor 80 may be, for example, a CCD device
consisting of 18 shift registers each 70 bits in length.
Fach stage serves both as a sensor and a storage/read out
device. In operation, an image is strobed on the sensor 80
using a pulsed infrared emitting diode as an illumination
source. As soon as the diode is off, the 18 registers are
shifted one bit, loading the serial read out register 82.
The read out register 82 is clocked 18 pulses to produce a
serial bit stream output. A second shift pulse to the 18
vertical shift registers is then produced and the cycle is
repeated a total of 70 times until all the data has been
read out. This type of read out can only be utilized
because the sensor is not illuminated during the read out
sequence. The illumination time will comprise about 10% of
the total frame time. This design has the advantage of
requiring a much simpler CCD structure whose total cell area
is light sensitive and thus twice as sensitive as a sensor
structure that utilizes alternate sensor and storage sites.
As shown in Figure 2, the sensor is interconnected with a
signal processing station. The video from the sensor array
is processed by two separate functions that produce outputs
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thlat are synchronized together to always relate to the same
cell of video data. These two functions are the 96 stage
CC,D spatial filter 84 and the 115 stage CCD background
reference circuit. The video signal is fed into the two
parallel CCD registers 84 and 86 which perform the two
processing functions simultaneously.
Looking at Figure 4, there is illustrated one possible
embodiment of the CCD sensor array 80. The photosites 90
are stages of vertical registers 92 which are read out by
vertically clocking all registers 92 to parallel load the
output register 94. The output register 94 ~as illustrated)
shifts to the left, shifting the video out at the cell rate
through a preamplifier 96 and then to the parallel registers
84 and 86 IFigure 2).
The spatial filter 84 is a linear filter designed to
amplify portions of the image that correspond to character
strokes characteristics or black parts of the image. The
filter 84 is designed to have an output that goes negative
for dark areas of video image and positive for white areas.
One possible embodiment of the 95 stage CCD shift register
and filter ~4 is illustrated in Figure S. The video is fed
into one end 84a of the shift register 84 in serial form.
The output from the differential amplifier 100 constitutes
the filter output. This output is sampled at the end of the
overscan time and stored on a capacitor 102 to be utilized
during the next frame as a black reference level. During
this sample time the filter register 84 contains only non-
exposed of black level cells.
Connected to the llS stage CCD register is a background
referen~e circuit 120 (Fig. 2) or reference detector which
is a nonlinear function which produces outputs that
represent the background or white level within a 7 x 7
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element area. This area is generally illustrated in Figure
7 an~ indicated as a 7 x 7 background detector matrix. A
description of this function is described later.
Each filter function output in conjunction with a black
reEerence level drives a comparator circuit to produce white
or black digital levels. The comparator number 1, 122 is
driven by a fraction of the background reference output and
the signal from the "center cell" (indicated in Figure 7 as
cell 58) which is the video information that is to be
quantized. The resistors Rl, 124 and R2, 126 determine the
percentage of background to be supplied to the comparator
122 which would be typically about 0.85. Comparator number
1, 122 output will be true, indicating white, if the center
cell value i8 greater than 0.85 of the reference. This
corresponds to a print contrast ratio of approximately 15%;
therefore, this function serves as a minimum print contrast
ratio detector to prevent paper noise and blind inks from
causing a black output.
Comparator 2, 128 is for the purpose of determining
whether the spatial filter 84 output is positive or negative
and providing a logic level signal. When the spatial filter
84 output is positive, the comparator 128 output is true
indicating a white level. The output of the comparator 128
will greatly emphasize image contrast differences making low
contrast white and black areas o~ a character white or black
logic level outputs.
~he two comparators 122 and 128 are combined by an OR
circuit 130 to produce a quantized black/white output. The
signals are OR'ED on a white basis so that either comparator
122 or 128 can force a white output. Comparator 1, 122 will
force a white output for an absolutely low contrast signal
and comparator 2, 128 will open up the white areas in an 8,
A" or other alphanumeric characters having an enclosed or
partially enclosed area. The output of the OR circuit 130
iS further processed by a spot filter 132 to remove isolated
white or black cells from the output. In addition to the
black/white data output, timing signals for external logic
synchronization are provided by the control logic 134 as
shown in Figure 2. These are Data Clock Out, Row/Frame
Sync, and Strobe Out. The Row/Frame Sync is used in
sampling the serial video stream and for vertical locationO
Strobe Out triggers the infrared emitting diodes which
illuminate the surface to be scanned or read. A Background
Signal Level Output, and the black reference are also
available to be used as an indication of the signal to noise
ratlo 80 that the video can be ignored at low light levels.
Description of major timing se~uence is illustrated in
the flow diagram of Figure 12. A vertical clock 150 is
generated for each 18 data or fixed rate pulses and is free
running. These clocks are counted by a vertical clock
counter 152. If the count is equal to or less than 73 a
test 154, 156 is made to determine if the count is 73. For
a count less than 73 a vertical clock 158 is gated to the
sensor array 160 causing the cell or fixed data to advance
by a row toward the read-out register 162. If the count is
73 a black reference sample pulse 164 is generated in
addition to vertically clocking the sensor. The output
register is then parallel loaded with the video data and
then read out, requiring 18 data clocks.
The above sequence is repeated until the vertical clock
count reaches 74. At this count, clocking of the sensor
stops and the IRED illuminator 168 is turned on. The
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illuminator 168 stays on until the count reaches 82, 170,
172. The vertical clock counter is then reset 174 which
allows the complete cycle to be repeated.
The relative rates for internal and external clocks are
illustrated in Figure 13.
The spatial filter 84 function provides character stroke
emphasis and serves as an aperture correction which corrects
for optical spreading in the array and for any uniform
component of lens roll-off.
~he spatial filter associated with the 96 cell CCD
register forms a two dimensional discrete circular
convolution of a two dimensional spatial impulse response
with the sensor's image data. In terms of a two dimensional
array, it can be considered as a 5 x S matrix superimposed
on the pattern of array cells. This is illustrated in
F~gure 7 wherein the 5 x 5 spatial filter matrix is shown in
conjunction with a 7 x 7 background detector matrix. It
should be noted that the cell 58 is the center of the
matrix. The reference detector 200 or background detector
shown in Figure 6 wherein the output is the white background
level output performs a limited area spatial peak detection
of the sensor image data. It covers the 7 x 7 matrix area
illustrated in Figure 7 but only uses a checkboard pattern
of samples for a total of 24 points as illustrated in Figure
8. Its implementation is on the second CCD register 8~ of
115 stases with the center of the 7 x 7 matrix at cell delay
58. Each sample point 202 is a unit weight diode-like
function which causes the detector output to represent the
highest (whitest) of the 24 cells being sampled. The match
between individual detector samples are usually within +5
for array signal levels above 20% of saturation.
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The black reference circuit 250 (Figure 9) produce an
o~tput level which is equivalent to a zero light level
condition on the sensor array. The error in the black
reference level as compared to the actual array black should
generally be equal to less than 1% of the illuminated array
output for illumination levels greater than 20% of
saturation.
The spot filter 132 further processes the data to
eliminate lone white or black data bits from the output. It
operates on the threshold matrix by the following function:
A(i,j) = T(i-l,j) + T(i+l,j) + T(i,j-l) + T(i,j+l)
~1 if A(i,j) = 4
S(i,j) = ~ T(i,j) if 0 ~ A(i,j) ~ 4
~0 if A(i,j) = 0
where S(i,j) is the two dimensional spot filtered image
matrix, the top left element of the matrix is S(o,o).
A(i,j) is the sum of the binary values (0-1) of the 4
onaxis, adjacent cells to the cell to be spot filtered in
the threshold matrix (see Figure 10).
If the four surrounding cells for a particular cell are
all the same, the spot filter forces the center cell to the
same value of the surrounding cells. Otherwise, the filter
does nothing to the center cell. Figure 9 represents the
function of four adjacent cells and a center cell. The spot
filter is a tapped CCD register feeding the appropriate logic
elements. In addition to the delay resulting from this
function, more delay is incorporated here to synchronize the
video with the Row/Frame Sync signal generated for the
system.
Having described a preferred embodiment of the image
Processing Integrated Circuit, other embodiments and
arrangements will become apparent to those skilled in the
art which will fall within the scope of the appended claim.
