Note: Descriptions are shown in the official language in which they were submitted.
~ 3 ~ll350
This invention relates to signal companders and
more particularly to an irnproved signal compander
adapted to be formed as an integrated circuit (IC).
- As well known c~mpander systems are designed to
compress the dynamic range of an audio signal prior to
transmission over or recordation on a dyanamic range
limited medium; and to expand the dynamic range of the
transmitted or recorded signal on subsequent playback
so that the signal has greater dynamic range than
otherwise provided by the transmitting or recording
medium.
One such compander system which has been widely
received as well as commercially successful is
described in U.S. Patent No. 3,789,143 issued Jan. 29,
197~ to David E. Blackmer and entitled Compander with
Control Signal Logarithmically Related to the
Instantaneous RMS Value of the Input Signal.
Generally, this sytem utilizes two basic components,
the gain control module or unit including a voltage
control ampliier (VCA) and the signal detector used to
generate the voltage control signal for the amplifier.
The voltage control amplifier is preferably of the type
described in U.S. Patent 3,714,462 issued Jan. 30, 1973
to David E. Blackmer and entitled Multiplier Circuits.
The detector preferably includes circuit means for
detecting the instantaneous RMS level of the input
signal, such as described in U~S. Patent 3,681,678
issued to David ~. Blackmer on Aug. 1, 1972 and
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5 ()
entitled RMS Circuits with sipolar Logarithmic Converter.
Generally, the voltage control amp1ifier impresses
a control]ed gain on the input signal so as to either
compress the dynamic range of the signal transmitted or
recorded, or expand the dynamic range of the signal upon
playbackO The amount of compression or expansion is
dependent upon the preselected compression or expansion
factor (how m~ch a signal is compressed or e~panded) D In
the compander system of U~S. Patent No~ 3~789,143 the
control signal is derived from a logarithmic function of
the instantaneous RMS level of the input signal so as to
provide expansion or compression as a function of the
instantaneous RMS level of the input signal. It should be
appreciated that other detection methods such as peak
detection and averaging detection have been used.
It is a general object of the present invention to
provide an improved compander syste~ which is easy and
ine~;~ersive to manufactureO
Another object of the present invention is to
provide a compander system having related improvemsnts so
as to be easily manufacturable in IC form.
And another object of the present invention is to
pxovide a compander system having improvements over the
one described in UOSO Patent NoO 3,789,143.
These and other objects are achieved by a signal
conditioning system comprising, in combination: (A) a
gain control module for varying a gain impressed upon an
input signal as a function of a control signal, the module
comprising: (l) a ~irst operational amplifier stage having
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an input terminal coupled to receive the input signal and
an output terminal; (2) ~irst log conversion means disposed
in each of two feedback paths coupling the input terminal
of the amplifier stage with the output terminal for providing
a log signal as a function of the logarithm of a corresponding
one of two representations of the input signal; antilog
conversion means coupled to each log conversion means for
providing an antilog signal as a function of the antilogarithm
of the sum of the corresponding log signal and the control
signal; and first bias generating means for generating a bias
current through the log conversion means of both the feedback
paths and thr~uyh the antilog conversion means; and
(B) control signal generating means for detecting the
input signal and for generating the control signal responsively
thereto, the control signal generating means comprising:
(1) operational rectifier means for providing a rectified
signal which is a substantial rectification of the input
signal, the rectifier means having an input terminal adapted
to receive the input signal and an output terminal for
providing the rectified signal, the rectifier means comprising:
Sa) a second operational amplifier stage ha~ing an input
terminal coupled to the input terminal of the rectifier means
and an output terminal; (b~ first current conduction means
responslve to the output of the second operational amplifier
stage and defining a transmission path bet~een the input and
output terminals of the reckifier means for substantially
conducting one representation of the input signal between the
input and output terminals of the rectifier means; (c) second
cu~rent conduction means responsive to the output of the
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second operational amplifier stage and defining a second
transmission path between the input and output terminals of
the second operational amplifier stage for substantially
conducting the other representation of the input signal
between the input and output terminals of the second
operational amplifier stage; (d) signal generating means
responsive to the input signal when substantially conducted
through the second transmission path for generating an
inverted signal of the other representation of the input
lD signal; ~2) second log conversion means coupled to the output
of the operational rectifier means for providing a second lo~
signal as a function of the logarithm of the rectified
signal; and ~3) means including a low pass filter coupled
to the output of the second log conversion means for providing
the control signal substantially as a function of the DC
value of the second log signalO
Other featuxes of the invention will in part be
obvious and will in part appear hereinafter. The invention
accoraingly comprises the appaxatus.possessing the construction,
combination of elements, and arxangement of parts which are
exemplified in the following detailed disclosure, and the
scope of the application of which will be indicated in the
claims..
For a fuller understanding of the nature and objects
of the present invention, reference should be had to the
following detailed description taken in connection with the
accompanying drawings wherein:
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I 1 ~3 ~ 3 ~5 0
Fig. 1 is a block diagram of the most basic components
of a compander system;
Fig. 2 is a block diagram of the essential components
of the preferred embodimen~ of the compander system of the
present invention;
Figs. 3A and 3B are circuit schematics of the
prefexred embodiment of the gain control module of the
p~esent invention; and
Yigs~ 4A and ~B are circuit schematics of the
preferred embodiment of the detector of the present invention.
In the dxawings the same numerals are used to refer
to like parts.
mg/~ 3b ~
3 5 0
In Fig. 1 the basic compander system such as the
one described in U.S. Patent 3,789,143 includes gain
control module 10 and detector 12. Generally the gain
control module adjusts the gain impressed on the input
signal ~in applied to voltage input terminal 14 as a
function ~f the control signal provided by detector 12.
Depending on the gain setting of module 10, the gain
impressed will provide either gain or attenuation of
the input signal to provide the output signal Eout at
output terminal 16. For compression the detector 12
can be connected in a feedback configuration(wherein
the detector detects the output signal Eout at output
terminal 16) or a feed forward configuration (wherein
detector 12 detects the input signal Ein at voltage
lS input terminal 14) both configurations being shown in
Fig. 1. For expansion, the feed forward configuration
is typically used. In both configurations, the detec-
tor provides the control signal in response to the
detected signal.
Referring to Fig. 2, the preferred gain control
module 10 includes input stage 18 having its input con-
nected to voltage input terminal 14 and its output con-
nected to VCA cell 20. The output of cell 20 is
connected to output terminal 16 of the system and is
suitably biased by bias generator 22.
Detector 12 shown connected with module 10 in the
feedforward configuration comprises rectifier 24 for
detecting the input signal at voltage input terminal 14
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and for rectifying the input signal. Rectifier 24 has
its output connec-ted ~o logging section 26 for providing
an output signal as a function of the logarithm of the
rectifier output of rectifier 24. Logging filter 28
converts the log signal output of section 26 to a
substantially DC signal which in turn is applied to the
input of buffer amplifier 30. Amplifier 30 has its
output connected to the control signal input of VCA
cell 20.
Referring to Figs. 3A and 3B, the gain control
module is shown as including the input stage 18 ~Fig. 3A),
VCA cell 20 (Fig. 3B), bias generator 22 (Fig. 3B) and
power supply 32 (Fig. 3A).
Referring specifically to Fig. 3A the current
input terminal 14A is identical to voltage input terminal
14 of Fig~. 1 and 2 except that it is modified to receive
the input current Iin as a function of the input
voltage Ein in a manner well known in the art. Input
texminal 14A is connected to the input of input stage 18
and the input of VCA cell 20. Input stage 18 is described
in greater detail in our copending application Serial No.
391,144 filed November 30, 1981. Specifically, input
terminal 14A is connected to the input terminal of stage 18
defined by junction 40. Junction 40 is connected to the base
of buffer transistor 42. The latter has its emitter connected
to the input 44 of a differential amplifier, generally indi-
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cated at 46, and its collector connected to current
generating means, generally indicated at 48, for
generating a current through transistor 42 so as to
reduce the amount of bias current drawn b~ stage 18
S ~rom the input terminal 14A~
In particular the current generating means 48
includes transistors 50, 52, 54, 56 and 58. The base
of transistor 50 is connected through junction 40 to
the base of transistor 42 while the bases of tran-
sistors 52 and 54 are connected together. The emitterof transistor 54 is connected to the collector of tran-
sistor 42 while îts collector is connected to the base
and collector of diode-connected transistor 53.
Transistor 52 has its collector coupled to the emitter
of transistor 50 and its emitter connected to the
collector and base of diode-connected transistor 56.
The emitter of transistor 58 and the collector of tran-
sistor 50 are tied together to s~stem ground while the
emitter of transistor 52 and the collector and base of
transistor 56 are connected to the collector of tran-
sistor 60. The latter has its base connected to the
base and collector of transistor 62 which in turn has
its emitter tied with the emitter of transistor 60 to
the upper rail voltage terminal 64 (shown in Fig. 3B~.
Differential amplifier 46 includes a pair of dif-
ferential elements comprising transistors 66 and 6~.
r~ransistor 66 has its base connected to input 44, its
collector connected through resistor 70 to the current
DBX-42
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~ irror generally indicated at 72, and its emitter connected
through capacitor 74 to system gro~lnd and through resistor 76
to junction 78. Translstor 68 has its base connected to
system ground at junction 80, its collector connected to the
current mirror 72, and its emitter connected to the collector
and base of diode-connected transistor 82. Transistor 82 has
its emitter connected through resistor 84 to junction 78.
Current mirror 72 is provided by transistors 86 and 8~ having
their bases connected together and their emitters connected
through the respective resistors 90 and 92 to the upper rail
voltage terminal 64. The colleetor of transistor 86 is con-
nected to resistor 86 and coupled to its base through
capacitor 94. Transistor 8~ has its collector connected
dlrectly to its base and to the collector of transistor 68.
The output of differential amplifier 46 is provided at
junetion 96 between the collector of transistor 66 and re-
sistor 70. Junction 96 is eonnected to the base of transistor
98 which in turn has its eollector connected to the collector
and base of transistor 62 and the base of transistor 60,
and its emitter connected to transistor 100 shown in Fig. 3Bo
The emitter of transistor 98, junction 78 as well as junction
44 are ~uitably eonnected to the power source 32.
As described in our copending application Serial No.
391,144 transistor 42 and current generating means 48 reduee
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~he lnput bias current drawn from -the input current at
terminal 14A without affectlncl the gain bandwidth pro-
duct of the stage. In parti.cular, the bipolar tran~
sistor 42 provides a buffer between terminal 14A and
the remaining portions of stage 18. Current generating
means 48 generates current through bipolar transistor
42 so as to reduce the amount of bias current drawn by
the remaining portion of the stage 18 without affecting
the gain bandwidth product of the stage. Further, as
described in our copending application Serial No. 391,144
the use of bipolar transistor 42 makes the circuit topology
easily adapted for IC implementation. The use of capacitor
94 and resistor 70 provide a zero (a zero being defined as
the value of complex frequency at which the transfer function
of the circuit becomes zero) in the transer characteristics
of the stage 18 so as to negate 90' phase shifts
generated by the feedback loop of the stage provided by
the VC~ cell.20, therefore effecting the stability of
the circuit. By connecting diode 82 to the emitter of
transistor 68 and by matching the impedance of resistor
76 with the combined impedances of diode 82 and
resistor 84, the noise contribution by the power supply
32 to the output at junction 96 i5 reduced. Finally,
the addition of capacitor 74 introduces a zero in the
transfer characteristics of the amplifier and the stage
which will negate the pole (a pole being defined as the
value of complex frequency at which the transfer func-
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tion of the eircuit becom~s infinite) introdueed kY the
base-to-emitter paras.itic capacitance of transistor 66.
Refer.ring to Fig. 3B transistor 100 has its
eollector conneeted to the upper rail voltage terminal
64 and its emitter conneeted through resistor 110 to
junetion 112. The la-tter forms one bias terminal oE
eell 20.
Cell 20 is deseribed in greater detail in applieant's
cop~nding applic~ti:on.Serial No. 359,031, filed ~ugust 26, 1980.
Junction 112 is conneeted through resistor 114 to the
collector of seeondary log transistor 116. The emitter
of secondary log transistor 116 is connected to the
emitter of primary log transistor 118. The collector of
transistor 118 is conneeted to junction 120, which in turn
is eonneeted to the input terminal 14A of the module.
Junetion 120 is also connected to the eollector oE primary
log transistor 122 which in turn has its emitter conneeted
to the emitter of seeondary log transistor 124. The
eolleetor of transistor 124 is coupled through resistor
126 to the junetion 128. Junction 128 forms the seeond
~ias terminal of eell 20 so that resistor 114, seeondary
log transistor 116, primary log transistors 118 and
122, secondary log transistor 124 and resistor 126 ~orm
a oircuit load for the bias generator 22. The
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junction 112 is also coupled through resistor 130 to
the collector of secondary antilog transistor 132,
which in turn has its emitter connected to the emitter
of antilog transistor 134. The collector of transistor
134 is connected to the junction 136 which in turn is
connected to the current output terminal 16A of the
module. Current output terminal 16A thus provides the
current output Iout of the module 10. Iout can easily
be converted to the voltage Eout in a manner well known
in the art. Junction 136 is also connected to the
collector of primary antilog transistor 138, which in
turn has its emitter connected to the emitter of secon-
dary antilog transistor 140. Secondary transistor 1~0
has its co]lector coupled through resistor 142 to the
15 junction 128. Resistor 130, secondary antilog tran-
sistor 132, primary antilog transistors 134 and 138,
secondary antilog transistor 140 and resîstor 142 form
another circuit load between junctions 112 and 128 for
bias generator 22~ The base of primary log transistor
20 122 is tied with the base of primary antilog transistor
134 to the control signal terminal 144, which in turn
receives the control signal from terminal of detector
12 described in reference to Figs. 4A and 4B. The
bases of transistors 118 and 13B can be respectively
2~ coupled to terminals 146 and 148 for receiving
adjusting currents between positive and negative input
signals to insure gain symmetry as will be more evident
hereinafter. The bases of each secondary transistor
DBX-42
L 3 5 ~3
116 and 132 are each respectively cross coupled to the
other's collecto~ and, similarly, the bases of each
secondary transistor 124 and 146 are each cross-coupled
to the other's collector
As described in detail in application Serial No.
359,031, each primary log transistor 118 and 12~ is
respectively coupled to a secondary log transistor 116
and 124 to f~rm two compound log devices, each dispo~ed
in a separate feedbac~ path ~etween the input and out-
put of stage 18. Primary transistor 118 is a PNP tran-
sistor while primary transistor 122 is an NPN
transistor. Each transistor 118 and 122 is connected
to a secondary transistor of an opposite conductivity
type. Accordingly, they functian as "compound log
transistors", each providing a log signal as a function
of the logarithm of the corresponding one of two
polarities of the input signal at terminal lAA.
As will be more evident hereinafter, the control
signal at terminal 144 is a function of the logarithm
of the instantaneous RMS value of ~he input signal at
terminal 14A. The control signal is added to the log
signals through the bases of primary transistors 122
and 134. Each primary antilog transistor 134 and 138
of opposite conductivity types is respecti~ely coupled
to a secondary antilog transistor 132 and 140 of an
opposite conductivity type to form two compound antilog
devices each for a diffexent polarity of input signal.
i 3 ~350
Transistors 132, 134, 138 and 140 function as "antilog
transistors" for providing an antilog signal as a function
o~ the antilogarithm of the sum of the corresponding log
signal and control signal. The log transistors 116 and 118
and antilog transistnrs 132 and 134 thus form one log-anti-
log transmission path for one polarity of the input signal and
log transistors 122 and 124 and antilog ~ransistor 138 and
140 provide a second log-antilog transmission path for the other
polarity of the input signal.
As described in copending application Serial No.
3S9,031, all of the NPN transistors are p~eferably matched
for their Vbe/Ic transfer characteristics. Similarly, all
of the PNP transistors are similarly matched to one another.
The secondary transistors provide signal modification ~eans
disposed in the log-antilog path f~r reducing distortion
due to the inherent base and emitter resistances of the
log and antilog transistors. Correction is derived from
a comparison between the input current and the output
(antilog) current from each log antilog path. Specifically~
a correction signal is derived from the voltage differential
generated between the collector voltages of the cross-
coupled secondary transistors of each log-antilog path. The
correction signal is provided to reduce the distortion at the
output terminal 16A due to the inherent parasitic base and
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emitter reslstances of -the transistors of cell 20. Any
mismatching of the parasitic and emitter resistances oE
each compound pair of transistors 116, 118; 122, 124;
132, 134; and 138, 140 can be easily compensated for by
individually adjusting the respective resistors 114,
126, 130 and 142.
Bias generator 22 is suitably connected at
junction 112 and junction 128 to provide a bias slgnal
through the circuit load including transistors 116, 118,
122 and 124 and through the circuit load including tran-
sistors 132, 134, 140 and 142. Generator 22 is shown
and described in greater detail in applicant 15 copending
application Serial No. 391,177, filed November 25, 1981.
Generator 22 is designed to provide a bias voltage between
j~nctions 112 and 128 of the cell 20, programmable by an
input current from the power source 32 to the generator
22 such that the resulting biasing current through the
log transistors and the resulting biasing cur~ent through
the antilog transistors will be e~ual or proportional to,
and thus track, the input current independent of temperature.
More specifically, generator 22 includes a first
resistor 150 having one end connected to the junction
112 and its other end connected to junction 154. Resistor
152 is coupled with resistor 150 between junction
154 a~d the junction 128~ Junction 112 is also
connected to the collector of NPN transistor 156 which
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in turn has its emitter connected to the emittex of PNP
transistor 158. NPN transistor 156 is matched ~or its
Vbe/Ic transfer characteristics to NPN transistors 116,
122, 132 and 138 and PNP transitor 158 is similarly
matched to PNP transistors 118, 124, 134 and 140 of
cell 20. The base of transistor 158 is connected to
junction 154, while its collector is connected to the
base of transistor 160. Transistor 160 has its emitter
connected to the base of transistor 162. The collectors
10of transistors 160 and 162 are connected together to the
base and collector of transistor 156 and to the junction
112. The emitter of transistor 162 is connected to the
junction 128. The base of transistor 158 is connected
to the anode of diode 164 which in turn has its cathode
connected to the base of transistor 160. The base of
transistor 160 is connected to a source of constant current
which is provided by power supply 32.
As described in our copending application Serial
No. 391,177, the current from source 32 to the junction of
~0the collector of transistor 158 and the base of transistor
160 is the programming input current to the generator.
The collector current of transistor 158 is equal
(neglecting the base current of the transistor 158) to
and is thus dependent on the current through the base-
to~emitter junctions of both transistors 156 and 158.
The transistors 160 and 162 form a plus one follower
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havinq voltage gain of one and very high current gain.
In operation, the current from power source 32 to
the base of transistor 60 remains constant and
establishes the level of the bias volta~e applied
across junctions 112 and 128. The amount of current
flowing through the emitters o~ transist~rs 156 and 158
establish the temperature dependent voltage across
resistor 150. The collector current of transistor 158
is approximately equal to the emitter current of tran-
sistor 158 and is equal to the input current to the
generator 22 so that the error current input to the
base of transistor 160 is approximately zero. If a
change wo~ld occur in the emitter current in tran-
sistors 156 and 158 compensation would be provided
through transistors 160 and 162 to adjust for the
error. Specifically, if the emitter currents through
transistors 156 and 158 increased, the voltage across
resistor 150 would increase. The collector current of
transistor 158 would in turn increase. Since the input
current from power source 32 remains constant, an error
current equal to the difference between the collector
current of transistor 158 and the input current would
result, and the voltage level on the base of transistor
160 would decrease with respect to the voltage level at
junction 112. This in turn would reduce the current
through resistors 152 and 150, reducing the voltage
across the base-emitter junctions o~ transistors 156
and 158, which in turn would result in a reduction in
DBX-42
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the emitter curr~nts in transistor 156 and 158 until
the collector current of transistor 158 equalized with
the input current from source 32 and the error current
in the base of transistor 160 e~ualed zero.
. Conversely, if the emitter currents of transistors
156 and 158 were to decrease and thus the voltage
across resistor 150 decreased and the collector current
of transistor 150 decreased, an error current equal to
the differenc~ between the collectors current of tran-
sistor 158 and the input current would be applied tothe base of transistor 160. This would cause an
increase in the voltage level of the base with respect
to the junction 112. This in turn would increase the
current through resistors 152 and 150 and the voltage
across the base~emitter junctions of transistors 156
and 158. This in t~rn would increase the emitter
currents in transistors 156 and 158 until the collector
current of transistor 158 e~ualized with the input
current from sources 32 and the error current in the
base of transistor 160 equaled zero.
A temperature-dependent voltage is thereEore
generated across resistor 150 which is the sum of the
voltage drops across the base to emitter junctions of
transistors 156 and 158. The temperature voltage drop
across each circuit load between junctions 112 and 128
of the cell 20 varies as a function of the sum of the
voltage across the base-to-emitter junctions of two NPN
and two PNP transistors matched respectively to the NPN
DBX-42
3 5 0
and PNP transistors 156 and 158.
Therefore~ in order to match the voltage current
temperature characteristics of the generator 22 with
the voltage current temperature characteristics of each
circuit load provided between the junctions 112 and
128, it is necessary to multiply the voltage generated
across resistor 150 by the scalar two. This is
accomplished by setting the resistance value of
resistor 152 equal to the resistance value of resistor
150 so that the current generated through resistor 150,
responsive to the voltage generated by transistors 156
and 158 there across, will be transmitted through
resistor 152 (neglecting the base current of transistor
158) to generate a like voltage. The voltages across
resistors 150 and 152 add toyether to provide the bias
signal across each circuit load between junctions 112
and 128 of cell 20. It will be appreciated that where
the gain control module is sub]ected to a change in
ambient temperature, a change in the base-emitter
voltage drops of transistors 156 and 158 will be
matched by a like change in ~he base-emitter voltage
drops of each pair of PNP and NPN transistor in each
circuit load.
Referring to Fig. 3A the current source 32 includes
transistor 170 having its collector connected to the
base of transistor 160 of bias generator 22.
Transistor 170 has its emitter connected through
resistor 172 to junction 174. Transistor 170 is
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cascaded w.ith transistors 176 and 178 by having their
bases connected togetherO Transistor 176 has its
collector connected to the emitter of transistor 177,
Transistor 177 has its base connected to system ground
and its collector connected to the emitter of tran-
sistor 98. Transistor 178 has its collector connected
to junction 78 of stage 18. The emitters of tran-
sistors 176 and 178 are directly connected to junction
174. The bases of transistors 170, 175 and 178 are
coupled through resistor 180 to the base of transistor
182 and the collector of transistor 184. The collector
of transistor 182 is directly connected to junction 44
of stage 18. The emitter oE transistor 182 .is con-
nected to the emitter of transistor 17OD The bases of
transistors 170, 176 and 178 are coupled through
resistor 186 to the base of transistor 184. The base
of transistor 184 is suitably connected two diode drops
below system ground by connecting the base through
diode-connected transistors 188 and 190 to system
ground~ Junction 174 is connected to the base of tran-
sistor 192 and through resistor 194 to terminal 196.
The emitter of transistor 192 is also connected to ter-
minal 196 while its collector is connected through
resistor 198 to junction 128 of cell 20. Terminal 196
can be suitably coupled through external resistor 200
to a voltage source 202. The nature of power supply 32
is such that a constant current is always provided on
the collector of transistor 170 so that bias generator
DBX-42
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22 functions in accordance with the teachings of our
copending application Serial No. 391,177.
Referring to Figs. 4A and 4B the detector 12
is shown in detail. In particular in addition to the
rectifier 24 (Figs. ~a and 4B), log sec-tion 26 (Figs. 4A
and 4B), log filter 28 ~Fig. 4B) and buffer amplifier
30 (Fig. 4BJ, the detector also includes current sources
300 and 302 (each shown partially in Figs. 4A and 4B)
and ~oltage source 403 (Fig. 4A).
Fig. 4A and voltage input terminal 14 is
connected through capacitor 310 to the resistor 312,
which in turn is connected to the current input terminal
14B (receiving the current input signal Iin). Current
input terminal 14B is connected to the input of recti-
fier 24.
Rectifier 24 comprises the operational amplifier
stage 320 and the bias generator 324. Rectifier 24 is
constructed in accordance with the teachings described
in applicant's copending application Serial No. 390,862
filed November 25, l9al.
Specifically current input terminal 14B is
connected to the input junction of terminal 330 of
the stage 320. Junction 330 is connected to the base
of transistor 332, the latter having its collector
connected to system ground and its emitter connected to the
collector of transistor 334. Junction 330 is also
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connected to the base of transistor 336, the latter
having its emitter connected to junction 33~ and its
collector connected to the emitter of transistor 340.
Transistor 340 has its base connected to the base of
transistor 334 and its collector connected to the
emitter of transistor 3q2. The base of transistor 342
is connected with the emitter of transistor 334 to the
voltage source 304, while the collector of transistor
342 is connected to the collector of transistor 344 and
the base of transistor 346. Transistor 344 has its
base connected to the base and collector of transistors
348 and its emitter tied with the emitter of transistor
34~ to the positive voltage rail indicated at 350. The
collector of transistor 348 is connected through capa-
citor 352 to the base of transistor 346. The collectorof transistor 348 is also connected to the colletor of
transistor 354 which in turn has its base connected at
355 to the system ground and its emitter connected to
junction 338. The transistor 346 has its collector
connected to the positive voltage rail 350 and its
emitter connected to the base of transistor 356 and
directly to the current sources 302. Transistor 356
has its collector connected to the positive voltage
rail 350 and its emitter connected to an anode of a
first diode 358 which in turn has its cathode connected
to the anode of a second diode 360. Diode 360 has its
cathode forming the output of stage 320 connected to
the recti~ier cell 322 such that the cell is connected
DBX-42
~ 3 ~35~
in a feedback path of the amplifier s-tage 320 as taught
in the copending application Serial No. 390,862.
Cell 322 comprises three transistors 380, 382 and
384. Transistor 380 is an NPN transistorl diode connected
by having its base connected through resistor 386 to its
collector to form input 388 of cell 322. Input 388 is con-
nected to the input of amplifier stage 320 at junction 330.
Transistor 382 i5 . also an NPN transistor having its collector
connected to the cathode of diode 398, which in turn has its
anode connected to the output 400 of the cell 388. Transis-
tor 382 has its emitter tied to the emitter`of transistor
380 and its base connected through resistor 390 to system
ground. The base of transistor 382 is also connected to the
terminal 392, which in turn is adapted to be connected
through a resistor 394 to a potentiometer 396. The latter
provides a variable current to the base of transistor 382
to insure gain symmetry between the current paths provided
by transistor 380 and 382 on the one hand and transistor 384
on the other hand as described in the copending application
Serial No. 390,852. Finally, transistor 384, an NPN transis-
torl has its emitter connected to the input 388 of the cell,
its base connected to the ca~hode of diode 360 of stage 320
and its collector connected to the output 400 of the cell.
As described in the copending application Serial No. 390,862,
the loop transmission of the stage 320 through each of the
- 21 -
jrc:~3~/
! 1 ~4350
path involving transistor 380 and the path involving trarlsistor
384 will limit at unity gain thereby eliminating stability
problems associated with unlimited loop transmission in the
rectification of positive input signals by the rectifier
disclosed in U.S. Patent 4,097,767.
The bias generator 324 provides a bias voltage
between the base of transistor 384 and the tied emitters
of transistors 380 and 382 as described in detail in the
copending application Serial No~ 390,B62. Generator 324
comprises signal generating means for generating the bias
voltage between the points 410 and ~12. The bias signal
is applied across a first impedance load comprising first
resistive means in the form of resistor 440. Resistor 440
is coupled to second resistive means, resistor 442, which
forms part of a second impedance load connected between
the base of transistor 384 and the tied emitters of transistors
380 and 382. As will be more apparent hereinafter by making
resistors 440 and 442 of equal resistance the bias voltage
is also applied between the base of transistor 384 and the
tied emitters of transistors 380 and 382.
More particularly, -the signal generating means
includes a first current source including transistors 414
and 416 for providing a reference current IB, a~second
current source including transistors 418 for providing
a reference current IA,.a pair of reerence ~ransistors
420 and 422 and a second pair of reference
- 22 -
jrc: ~
i ~ ~'13~)
-23-
transistors 424 and 426. Transistor 414 has its
emitter tied with the emitter of transistor 416 and the
emitter of transistor 418 to system ground. The
collector and base of transistor 414 are connected to
the current sources 302 and to the bases of transistors
416 and 418. The collector of transistor 416 is con-
nected to the base of transistor 434, which in turn has
its collector connected to the output of the.log sec-
tion 26 and its emitter connected to the base and
collector of diode-connected transistor 436. The
latter has its emitter connected to the point 412. The
collector of transistor 416 is also connected to the
collector of transistor 420, which in turn has its base
connected to the point 410 and its emitter connected to
the collector and base of diode connected -transistor
422. The emitter of transistor 422 is connected to the
negative voltage rail 450 and the resistor 428. The
collector of transistor 418 is connected to the base
and collector of diode-connected transitor 432 which in
turn has its collector connected to point 410. Point
410 is connected to the base and collector of diode-
connected transistor 424, the latter having its emitter
connected to the base and collector of diode-connected
transistor 426. The emitter of transistor 426 is con-
25 nected to the common junction of resistors 428 andresistor 430. Resistor 430 is in turn connected to
point 412.
The base of transistor 432 is connected to the base
DBX-42
3~ 0
of transistor 438, which in turn has its emitter con-
nected through resistor 440 to the point 412. The
collector of transistor 433 is connected to the base
and collector of diode-connected transistor 444, the
latter having its emitter connected to resistor 442
which in turn is connected to the ~ase of transistor
384 of the cell 322. The collector and base of transis-
tor 444 are connected to the base of transistor 446
which in turn has its emitter connected to the tied
emitters of transistors 380 and 382 and its collector
connected to the negative voltage rail 450 of the
current sources 302. As described in the copending
application Serial No. 390,862 transistors 420, 422,
424 and 426 are all NPN transistors matched for their
; Vbe/Ic characteristics with those of NPN transistors 380,
382 and 384 of the rectifier cell 322. Similarly, transis-
tors 432 and 438 are of like conductivity type and are
matched for their Vbe/Ic characteritics and transistors
444 and 446 are of the same conductivity type and matched
for their Vbe/Ic chacteristies.
The rectifier 24 operates in a manner consistent
with the teachings of copending applica~ion Serial No.
390,862. In general, when the input current at junction
14A is negative, the output signal at the cathode of diode
360 of stage 320 is positive. This provides negative feed-
back through the base-emitter
- 24
jrc ~/
il 1 6d350
junction of transistor 384 of the cell 322. This, in
turn results in current flowing from the output at terminal
400 of the rectifier, through the collector-base junction of
transistor 384 to the input terminal 330 of stage 320. Trans-
istors 3~0 and 382 are substantlally nonconductive since
their base~emitter junctions are reversed biased.
For positive input currents at terminal 14B the
output of stage 320 is negative, the base-emitter junction
of transistor 380 is forward biased and current flows
through the junction. A substantially equal mirrored
current flows through the collector of transistor 382 to
therefore provide an inverted signal at the output 400
for this polarity of the input signal.
The base of transistor 384 and the tied emitters
of transistors 380 and 382 are biased by the bias generator
324 so as to reduce the slewing requirements of amplifier
320 for a given level of performance.
As taught in the copending application Serial No~
390,862 the bias voltage generated between points 410
and 412 is equal to the voltage drop across the base-
emitter of transistor 424 plus the voltage drop across the
base-emitter of transistor 426 minus the voltage drop across
resistor 430. In general, if the reference current IB through
transistors 420 and 422 is equal to n times the reference
current IA through transistors 424 and 426, the voltage across
resistor 428 will be that which when subtracted from
- 25 -
jrc:i ~
5 ()
the voltage across a reference diode string (such as
provided by transistors 420 and 422) will cause the
current through a matched string to be reduced by a
factor of n. ~he voltage across resistor 430 then will
be that ~hich when subt.racted from the voltage across
the reference diode string of transistors 424 and 426
will cause the current through the matched string to be
reduced by a factor of n raised to the kth power
(wherein k is khe ratio of the resistance of resistor
430 to that of resistor ~28). Since the voltage across
point 410 and 412 is the voltage drop across the diode
string consisting of diode-connected transistors 424
and 426 minus the voltage drop across resistor 430, and
since transistors 424 and 426 are matched to transis-
tors 420 and 422, as taught in the copending application
in U.S. Serial No. 137,427 filed on April 4, 1980,
and the copending application Serial No. 390,862 the
circulating current provided to transistors 384 and 380
(the current circulating through base and emit-ter of transistor
384 and the collector and emitter of transistor 380) will be a
factor of n raised to the kth power less than the reference
current through transistors 424 and 426. The bias voltage
therefore can vary with temperature in such a manner
such that the circulating current will not change with
such temperature variations while the setting of current
IA, the ratio of IB to IA, as well as the ratio
of resistors 428 and 430 will set the maximum cir-
- 26 -
3 ~ 6 ~ 5 (~
27-
culating current generated in the collector and emitter
of transistor 380 and the base-emitter junction of
transistor 384 and the maximum error at output 400 due
to this circulating current.
The bias voltage across points 410 and 412 thus
equals the desired bias voltage. The voltage generated
across these points is applied across the first impe-
dance load comprising the base emitter junctions of
transitors 432 and 438 and the resistor 440. The base-
emitter junction of transistor 438 is forward biased so
as to be conductive. The bias voltage provided across
resistor 440 therefore generates a current through the
resistor 440 and the transistor 438 ~hich in turn for-
ces the current through resistor 442 and the diode-
connected transistor 444. The current through theemitter of transistor 44~ is set so as to be the same
as that through transistor 432 (IA) so that by matching
transistor 444 to transistor 446 and matching tran-
sistor 432 to transistor 438, any mismatching between
the voltage drops across each of transistors 432 and
438 due to a mismatching of currents flowing through
the collectors of these transistors will be offset by a
similar mismatch in voltage drops between transistors
444 ana 446 due to a duplication in the current
mismatching. The current through resistor 442 results
in the bias voltage being generated across a second
impedance load comprising the resistor 442 and the
base-emitter junctions of transistors 444 and 446.
DBX-42
... .
3 5 0
.. ;
-28- .
Thus, the voltage aeross resistor 442 and transistors
444 and 446 equals the required bias voltage whieh can
vary with temperature without effecting the eirculating
eurrent in transistors 380 and 384.
By providing the proper bias voltage to the base of
the transistor 384 and the common emitters of tran-
sistors 380 and 382, the eireulating error eurrent
transmitted at the output 400 due to the eirculating
eurrent flowing in the base emitter path of transistor
384 and the eolleetor emitter path of transistor 380 is
temperature independent and the maximum acceptable
level the circulating error current at output 400 is
determined by the ratio of the resistance values of
resistors 428 and 430, the bias current IA eonducted
through transistors 424 and 426 of the generator 324,
and the ratio of eurrents IB to IA.
Therefore, the eurrent output signal of rectifier
24 at output 400 is a full wave rectification of an
input current at terminal 14B. The output 400 i5 eon-
neeted to the logging section 26.
Logging section 26 (shown in Figs~ 4A and 4B)ineludes an operational amplifier stage 451 and logging
elements 452. Stage 451 includes an input 454 con-
nected to the output 400 of the cell 322 of rectifier
24. Input 454 forms the connection between the bases
of transistors 456 and 458. The collector of tran-
sistor 456 and the emitter of transistor 458 are con-
nected to system ground~ The emitter of transistor 456
DBX-42
~ ~435~)
-29- .
is eonneeted to the eollector of transistor 458 whieh
in turn has its emitter eonneeted to the voltage souree
304, the eurrent sourees 30Q. The emitter of tran-
sistor 458 is also eonneeted to the base and collector
of transistor 460 and the anode of di~de 461. The
colleetor of transistor 460 is eonneeted to eurrent
sourees 300 and the eathode of diode 4610 The emitter
of transistor 460 is eonnected to the eollector of
transistor 462- which in turn has its base eonneeted to
10 the base of transistor 458 and its emitter connected
through resistor 464 (shown in Fig. 4B) to the collec-
tor of transistor 458. The collector of transistor 460
is conneeted through eapacitor 468 to system ground and
to the base of tLansistor 466. The collector of tran-
15 sistor 466 is eonnected to the current sourees 300.The emitter of transistor 466 is conneeted to the base
of transistor 470 whieh in turn has its eolleetor con-
neeted to the sourees 300 and its emitter eonneeted to
the output of logging elements 452.
Logging elements 452 are formed by connecting two
diode-eonneeted transistors 478 and 480 in a feedback-
loop between the output and input of the stage 451, the
output and inputs being respeetively formed by the
emitter of transistor 470 and the input 454. In opera-
25 tion ~he reetified eurrent signal at input 454 willalways flow into the rectifier 24 so that the tran-
sistors 480 and 482 of the logging elements 452 are
always forward biased. The nature of stage 451 and
DBX-42
1 ~ 64350
logging elements 452 convert the rectified signal into
a signal which is a function of the square of its input
signal or more accurately a function oE two multiplied
by the logarithm of the input signal. Thusl the input
at terminal 476 of stage 451 is a representation of the
logarithm of the s~uare of the current input signal at
current input terminal 14B.
The output at the emitter of txansistor 470 of the
stage 451 is connected to the input of logging filter 28
(Fig. 4B). In particular filter 28 includes at least
one diode connected transistor 490. The oùtput oE the
log ~ection 26 is connected to the base and collector of
transistor 490 while the emitter of the transistor forms
the output of the filter. The output of the filter is
suitably biased by the current sources 302 and is con-
nected through external capacitor 492 to the external
resistor 494 which in turn is connected to system ground.
Since the output of the log section 26 is a log signal,
filter 28 functions as a low pass filter and the output
of the filter is primarily a DC signal. This D.C. signal
is provided to the input of buffer amplifier 30.
Amplifier 30comprises a transistor 500 having its
- 30 -
jrc: ~
~ ~6~350
base connected to the output of filter 28. The emitter
of transistor 500 is connected to the base and collec-
tor of diode-connected transistor 502 which in turn has
its emitter connected to the base and collector of
diode-connected transistor ~04. Transistor 504 has its
emitter connected to junction 506, which in turn is
connected to sources 3020 The collector of transistor
500 is connected to the collector and base of tran-
sistor 508, the latter having its emitter connected
through resistor 510 to the positive voltage rail 350.
The base and collector of transistor 508 is also con-
nected to the base of transistor 512, which in turn has
its emitter connected through resistor 514 to current
sources 300. The collector of transistor 512 is con-
nected to the base of transistor 516 and the collectorof transistor 518. Transistor 516 has its collector
connected to the positive rail 350 and its emitter con-
nected to the sources 302 and the base of transistor
520. Transistor 52~ has its collector connected to the
collector and base of transistor ~22, which in turn has
its collector and base connected to current sources
300 and its emitter connected to rail 350. Transistor
520 also has its emitter connected to the base of
transistor 518 which in turn has its emitter connected
~o the junction 506. The base of transistor 518 and
the emitter of transistor 520 collectively form the
output 524 of the detector 12. Output terminal 524 is
suitably biased by current sources 302 and is connected
DBX-42
J ~ 6~ .~5 ~
-32-
to terminal 144 of the cell 20 of the control module
shown in Fig. 3.
Current sources 300 and 302 and voltaye source 304
respectively provide the necessary bias currents and
voltage to the rectifier 24, logging section 26,
logging filter 2~ and buffer amplifier 30. In par-
ticular referring to Figs. 4A and 4s, sources 300
includes four PNP transistors 600, 602, 604 and 606 all
having their emitter connected to the positive voltage
rail 350. The collector of transistor 600 is connected
to the tied emitters of transistors 380 and 382 of rec-
tifier cell 322 of the rectifier 24. The base of tran-
sistor 600 is tied to the bases of transitors 602 and
604. Transistor 602 has its collector connected to the
collector of transistor 460 and base of transistor 466
: of the log section 26~ Transistor 604 has its collec-
tor and base connected to the current sources 302.
Finally, transistor 606 has its base connected to the
base and collector of transistor 522 of amplifier 30
: 20 and its collector connected to the base of transistor
460 of the log section 26.
Referring to Fig. 4A, current sources 302 includes
diode-connected transistor 620 hav;ng its collector and
base forming the output terminal 622. Terminal 622 is
connected khrough external resistor 624 to system
ground~ Diode connected transistor 620 has its emitter
connected to the base and collector of diode-connected
transistor 622, which in turn has its emitter connected
- DBX-42
... .
3~
-33-
to the collector of transistor 624. The latter has its
emitter connected to the negative voltage rail 45~.
The base and collector of transistor 622 (two diode
drops above the negative voltage rail 450) is connected
to the base of transistor 626 and the base of tran-
sist.or 628. The emitter of transistor 626 is connected
to the base and collector of transistor 624 (one diode
drop above the ne~ative voltage rail 450). Similarly,
the emitter of transistor 628 is connected to the
collector and base of transistor 624. The collector
and base of transistor 624 are in turn connected to the
emitters of transistors 630~ 632, 634, 636, 638 and 640
and to the base of transistor 642, the latter having
its emitter connected to the negative voltage rail 450.
The common base connection of transistors 626 and 628
is connected to the bases of transistors 630, 632l 634,
636, 638 and 640. The transistor 630 has its collector
connected to the emitter of transistor 644, which in
turn has its base connected to the base of transistor
646. Transistor 646.has its emitter connected to the
collector of transistor 632. The collector of tran-
sistor 626 is connected to the junction 338 of stage
320, while the collector of transistor 628 is connected
to the base collector of transistor 414 of bias genera-
tor 324. The collector of transistor 644 is connectedto the emitter of transistor 346 and the base of tran-
sistor 356 of amplifier stage 320. The collector of
transistor 646 is connected to the emitter of tran-
DBX-42
o
-34-
sistor 466 and the base of transistor 470 of the log
section 26. Transistor 634 has its collector connected
to the common collector and base of transistor 604 and
sources 300. Transistor 636 has its collect~r con-
nected to the output of filter 28 while the collectorof transistor 638 has its collector connected to junc-
tion 506 of buffer amplifier 30. Transistor 640 has
its collector connected to the base of transistor 520
and the emitter of transistor 516 of the buffer
amplifier 30, while the collector of transistor 642 has
its collector connected to the output terminal 524 of
the detector.
Voltage source 304 includes three diode-connected
transistors 700, 702 and 704. Transistor 700 has its
collector and base connected three diode drops above
system ground to the emitter of transistor 458 and the
base of transistor 460 of log section 26. The emitter
of transistor 700 is connected to the collector and
base of transistor 702 so as to form a source two diode
drops above system ground. The collector and base of
transistor 702 is connected to the emitter of tran-
sistor 334 and the base of transitor 342 of stage 320.
Finally, transistor 702 has its emitter connected
through the diode-connected transistor 704 to ground.
In operation the system is properly biased so that
tne necessary biasing currents are provided by source
32 of the gain control module and current sources 300
and 302 of the detector. When an input voltage signal
DBX-42
... .
3 ~ 0
-35-
.
is applied to input terminal 14 it is converted to a
current which is applied to terminals 14A and 14B.
Thus, current signal at terminals 14A and 14B is pre-
sented simultaneously to the gain control module 10 and
the deteetor 12.
The detector receives the signal at junction 330
whereupon the signal is rectified by rectifier 24.
Speeifically, a negative signal at input 330 results in
a positive output of amplifier stage 320. This results
in transistor 384 being forward biased and current
flowing from the output 400 of the cell 322 through the
collector-emitter path of transistor 384 of rectifying
cell 322. Thus, a current flows from input terminal
454 of logging section 26. The transistors 380 and 382
of cell 322 remain reversed biased and thus
nonconductive. Positive curent signals at input 330
result in a negative output of amplifier stage 320.
This results in transistor 380 being forward biased and
transistor 384 being reversed biased. Transistor 380
thus conducts a current which results in a mirrored
current through the collector emitter path of tran-
sistor 382. The emitter currents of transistors 380
and 382 are sunk through the bias generator to the
negative voltage rail 450. Thus, as in the case of
25 negative input signals, current flows from input ter-
minal 454 of logging section 26 to the cell 322. Full
wave rectification is therefore provided. The current
signal provided at input tèrminal 454 of logging sec-
DBX-42
1 D 6~350
-36-
tion 26 is converted to a log signal and multiplied by
the factor two through the feedback path of diode-
connected transistors 480 and 482. This results in an
output signal of the log section which is a represen-
tation of the logarithm of the square of instantaneousinput current at terminal 14B. The signal at the out-
put of log section 26 is transmitted through low pass
filter 28; thence through amplifier 30 to provide the
control signal at terminal 524. Terminal 524 is con-
10 nected to terminal 144 so that the control signal canbe added to the log signal in the VCA cell 20 of the
module.
The input signals at terminals 14A and 14B are
also transmitted through module 10 where a gain is
impressesd on the current signal as a function of the
control signal. For negative input signals at terminal
14A, feedback occurs through log transistors 116 and
118 of VCA cell 20. The voltage signal across primary
and secondary log transistors 116 and 118 are a func-
20 tion of the logarithm of the input signal since thetransistor lies in the feedback path of stage 18. The
control signal at terminal 144 is arithmetically added
to the log signal before the algebraic sum of the two
signals is converted by antilog transistors 132 and 134
25 to an antilog signal as a function of the antilogarithm
of the sum of the two signals. For positive input
signals at terminals 14A, feedback occurs through log
trans;stors 122 and 124 of VCA cell 20. The log signal
DBX-42
3 5 0
-37-
provided by log transistors 122 and 124 is again a
function of the logarithm of the input signal since the
transistor also lies in the feedback path of stage lB.
The control signal at terminal 144 is added to the log
signal before the algebraic sum of the two signals is
converted by antilog transistors 138 and 140 to an
antilog signal which is a function of the antilogarithm
of the sum of the two signals.
The use of stage 18 and in particular transistor
42 and current generating means 48 results in a smaller
bias current drawn by the stage from terminal 14A
without affecting the gain bandwidth product of the
stage.
Further, the use of capacitor 94 and resistor 70
15 provide a zero in the transfer characteristics of the
amplifier 18 to negate 90~ phase shifts produced in the
feedback paths through the VCA cell 20. By connecting
diode 82 to the emitter of transistor 68 and by
matching the impedance of resistor 76 with the combined
impedance of diode 82 and resistor 84, any noise
contribution by source 32 is reduced. Finally, the
addition of capacitor 84 introduces a zero in the
transfer characteristics of the stage which will negate
the pole introduced by the base-to~emitter parasitic
25 capacitance of transistor 66.
The use of bias generator 22 provides a bias
voltage between the junctions 112 and 128 of the VCA
cell 20. The bias voltage is determined by the input
DBX-42
3 5 0
-38
current from source 32 and generates a biasing current
through the cell which is independent of temperature.
The use of the secondary transistors 116, 124, 132
and 140 and resistors 114, 126, 130 and 142 reduce
distortion due to parasitic base and emitter resistan-
ces of the log and antilog transistors 118, 122, 134
and 138 of cell 20.
The use of the rectifying cell 322 of the detector
12 and in particular providing maximum limit of unity
10 loop gain in both feedback paths around the amplifier
stage 320, improves the performance of the detector.
Finally, the bias geneator 324 provides the bulk of
the yenerator away from the base of transistor 384 and
the common emitters of transistors 30 while at the same
15 time providing the desired bias voltage therebetween.
It will be appreciated that the foregoing provides
an improved compander system which can be used either
as a compressor or an expander of the signal applied to
the input terminals 14A and 14B. The system is easily
20 manufacturable as an IC circuit providing reduced costs
of manufacture. When manufacturing the module 10 and
detector 12 as separate integrated circuit chips both
will dissipate a substantially like amount of power.
More particularly, the output of detector 12 is a func-
25 tion of the RMS value of the input signal and operatingtemperature. The gain of the detector is a function of
the control signal and temperature. The present design
therefore is such that variations of the RMS output
DBX-42
... .
3 ~ Q
39- .
with temperature are matched to changes in VCA gain
with tempexature such that the compression or expansion
factor will be independent of temperature so long as
the module and detector are operated at the same
temperature.
Since certain changes may be made in the above
apparatus without departing from the scope of the
invention herein involved, it is intended that all
matter contained in the above description or shown in
the accompanying drawings shall be interpreted in an
illustrative and not in a limiting sense.
DsX--42
