Note: Descriptions are shown in the official language in which they were submitted.
~ 3 ~3~7
BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates to a signal conditioner and
commutator for a plurality of input signals.
II. Description of the Prior Art
~.
Conventional systems which interweave two or more input
signals into a single output for transmission employ individual
signal conditioners for each input signal and then pass the
signals to a commutator which sequentially looks at each
1~ pre-conditioned input signal. The conditioning typically
Il adjusts the range and offset of each input signal to standardize
; the input signals for transmission. The commutator, in
effect, serves only as an electronic switch with one pole
and a plurality of positions, one for each input signal.
In such conventional systems, each of the plurality of
input signals is being conditioned lt)0 percent of the time
by the respective signal conditioners while the commutator
is looking at only one conditioned signal at a time. Thus,
I if 128 input signals were employed, 127 conditioned signals
2~ ~l are unutilized at any given time.
` Since each signal conditioner typically requires three
resistors and se~eral operational amplifiers to achieve
suitable range and offset, it is apparent that such systems
are rather inefficient. ~his inefficiently results in a
system with excessive power requirements and reliability
problems and with excessive volume allocated to the signal
conditioning funstion. Furthermore, operational flexibility
in such conventional systems is severely limited by the
requirement of removing and replacing various resistors for
each input signal when the preconditioning function must be
varied. Flexibility is also reduced by the requirement of
modifying jumper circuits when the pattern of commutation must
be altered.
1 J &~3~7
It is, accordingly, an object of the present invention
to provide an apparatus for achieving re~uired signal
conditioning and commutating in an efficient yet flexible
manner.
It is another object of the present invention to provide
an apparatus of a reduced component count, volume, power
consumption, and weight which achieves conditioning and
commutating of a plurality of input signals.
It is still another object of the present invention to
' provide a signal conditioning apparatus which achieves
optimum flexibility in responding to changes in signal
conditioning and commutating re~uirements.
Additional objects and advantages of the invention will
be set forth in part in the descriptLon which follows, and
in part will be obvious from the description, or may be
learned by practice of the invention, The objects and the
advantages may be realized and obtained by means of the
I instrumentalities and combinations particularly pointed out
jl in the appended claims.
"
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Summary of the Invention
To achieve the foregoing objects, and ln accordance
with the purposes of the invention as embodied and broadly
described herein, a commutating signal conditioner for a
plurality of input signals of the present invention comprises:
(a) a variable amplifier means; tb) memory means for
storing operational information for the amplifier means; (c)
commutator means for selectively coupling the input signals
to the amplifier means; and (d) circuit means for adjusting
~0 the variable a~plifier means as indicated by the operational
information for each input signal coupled to the amplifier meansO
Preferabl~, the variable amplifier means selectively
varies the amplitude range of the input signals and/or
selectively offsets the input signals. Such a variable
amplifier means may, for example, comprise a plurality of
digital-to-analog converters and the memory means may, or
e~ample, comprise a read only memory.
The circuit means may also comprise means for stepping
the commutator means in synchronism with the adjusting of
~ said variable amplifier means to couple the input signals to
the amplifier means when the amplifier means is adjusted to
properly condition the specific input signal being coupled
to the amplifier means. The memory means may also include
means for storing order information for determining the
order of stepping the commutator means.
In a more limiting sense, the variable amplifier means
may comprise: (a) input and output terminals; (b) a
reference source; ~c) first, second, and third operational
amplifiers; (d) a first resistive network coupled between the input
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terminal and the input to the first opera-tional amplifier;
(e) an inverter coupled between the output of the first
operational amplifier and the output terminal; (f) a
second resistive network coupled between the output terminal
and the input terminal of the second operational amplifier,
the output of the second operational amplifier being coupled
to the input of the first operational amplifier; (g) a
third resistive network coupled between the reference source
and an input to the third operational amplifier, the output
1~ f the third operational amplifier being coupled to the
input of the first operational amplifier; and(h) means for
varying the resistive networ]cs as indicated by the operational
information stored in the memory means.
;l In another example of the preferred embodiment of the
present invention the signal commutator conditioner is
operable on a pluralit~v of input signals, and the conditioner
comprises: (a) first and second variable amplifiers; (~)
memory means for storing operational information for the
, amplifiers; (c) commutator means for selectively coupling
the input signals to the first and second variable amplifiers;
and (d) logic means for setting the first and second variable
amplifiers as indicated by the operational information for
each input signal coupled to the respective amplifiers, the
logic means setting one of the amplifiers while the other of
the amplifiers operates on an input signal.
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Brief Descript_on of the Drawin~s
The accompanying drawings, which are incorporated and
constitute a part of the specification, illustrate examples
of the preferred embodiment of the invention and, together
with the general description of the invention given above
and the detailed description of examples of the preferred
embodiment given below, serve to explain the principles of
the invention.
Fig. 1 is a block diagram of a conventional commutating
~~ signal conditioner;
Fig. 2 is a block diagram of a commutating signal
conditioner in accordance with the teachings of the present
invention;
~, Fig. 3(a) illustrates a standard non-variable amplifier;
Fig. 3tb) illustrates a modified form of the non-
variable amplifier of Fig. 3(a~;
Fig. 3(c) illustrates a programmable amplifier as may be
11
employed in accordance with the teachings of the present
' invention;
X~ Fig. 4 is a schematic diagram of one example of a
specific programmable amplifier constructed in accordance
with the teachings of the present invention;
Fig. 5 is a block diagram of another example of a
commutating si~nal conditioner in accordance with the
teachings of the present invention;
Fig. 6 is an electrical diagram of an example of a
commutating signal conditioner as illustrated generally in
Fig. 5;
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Fig. 7 is a block diagram of a logic circuit suitable
for use in the commutating signal conditioner illustrated in
Fig. 6; and
Fig. 8 is a block diagram of a memory unit suitable for
use with the logic circuit illustrated in Fig. 7.
The above general description and the following detailed
description are merely illustrative of the generic invention
and additional modes, advantages, and particulars of this
~invention will be readily suggested to those skilled in the
lart without departing from the scope and spirit of the
invention.
Description_of the Preferred Embodiment
Reference will now be make in detail to the present
preferred embodiment of the invention, examples of which are
illustrated in the accompanying drawings.
~, Broadly, the present invention relates to a commutating
signal conditioner for a plurality ot input signals~ Such
'systems are known generally as telemetry systems and as
~time-division multiplexing systems. A conventional commutating
2~ signal conditioner is indicated in Fig. 1 as comprising
signal conditioner unit 200, commutator 202, transmitter
204, and antenna 206. Signal conditioner unit 200 comprises
, a plurality of individual signal conditioners 208, for
example, one for each of a plurality of illustrated input
signals 1-128. Commutator 202 comprises a switching mechanism
~210 controlled by a logic network 212 which causes switching
mechanism 210 to sequentially connect conditioned input
signals from siynal conditioner unit 200 to a single input
channel of transmitter 204.
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Typically, transmitter 204 will require a pulse amplitude
modulation with non-return to zero (PAM - NRZ) signal which
has specific amplitude range and offset limitations. For
example, transmitter 204 might require a PA*5 - NRZ signal
of + 2 1/2 volts range centered or symmetrical with respect
to ground or zero volts. However, input signals 1-128 may
have different magnitudes of amplitude range variation and
not be zero centered. It is accordingly a function of
individual signal conditioners 208 to operate on the amplitude
range and offset of the individual input signals, thereb~
molding or scaling the input signals to the standards
required by transmitter 204.
Individual signal conditioners 208 may each comprise,
for example, the arrangement illustrated in Fig. 3a including
differential or operational amplifiers 214 and 216 and
resistors 218, 220 and 222. Amplifier 214 has an output
coupled back to a negative input terminal and serves the
function of a unity gain voltage follower, or buffer, of
high input impedance. The function of amplifier 214 is to
prevent the signal conditioner from presenting and excessive
load to the sources of the input signals. The output of
amplifier 214 is coupled through resistor 222 to the negative
input of amplifier 216 while the positive input of amplifier
~, .
216 is coupled to an appropriate bias source, such as ground.
Resistors 218 and 220 are series-coupled between bias v,
which may be positive or negative, and the output of amplifier
216 while the junction of resistors 218 and 220 is coupled
to the negative input of amplifier 216.
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As is well-known to those skilled in the art, the gain
of the signal conditioner illustrated in Fig. 3a is approximately
equal to minus the ratio of resistor 220 over resistor 222
while the offset is equal to minus the ratio of resistor ~20
over resistor 218 times the value of bias V. Accordingly,
adjustment of resistors 220 and 222 may operate to assure
that the gain or attenuation of the signal conditioner
establishes an output signal of desirable amplitude range
while adjustment of resistors 220 and 218 may assure that
the output signal is symmetrical with respect to a chosen
point such as ground.
Changes of amplitude range or offset are achieved in
such prior art arrangements by replacing one or more of
resistors ~18, 220 and 222. It is a prime purpose of the
present invention to increase the flexibility of such a
conventional signal conditionin~ system while reducing the
component count required by such conventional systems to
implement large telemetry systems. Addi-tional direct benefits
,l envisioned by the present inven~ion are reduced volume,
j lower costs for assembly, decreased turn around time to
implement changes, and increased system reliability.
In accordance with the present invention, a commutating
signal conditioner for a plurality of input signals comprises
a variable amplifier means, memory means for storing operational
information for the amplifier means, commutator means for
selectively coupling input signals to the amplifier means, and
circuit means for adjusting the variable amplifier means as
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indicated by the operational information Eor each input
signal coupled to the amplifier means. The circuit means
preferably includes means for stepping the commutator means
in synchronism with the adjusting of the variable amplifier
means to couple the input signals to the amplifier means when
the amplifier means is adjusted to properly condition the
specific lnput signal being coupled to the amplifier means.
Furthermore, the memory means may include means for storing
order information for determining the order of stepping the
commutator means.
~s shown by way of illustration and not limitation, an
example of a commutating signal conditioner in accordance
with the present invention is illustrated in Fig. 2 as
comprising commutator 300, programmable or variable amplifier
302, memory UIlit 304, transmitter 306, and antenna 308.
Commutator 300 comprises a random access switching mechanism
310 and a logic network 312. Switching mechanism 310 is in
efect an electronic switch with one pole and a plurality of
~ positions, for example, 128 positions for 128 input signals.
Logic network 312 may operate switching mechanism 310 to
, assure a sequential connection of each of input signals 1-
128 from commutator 300 to variable amplifier 302. However,
logic network 312 preferably operates switching mechanism
310 in any order governed by order information stored in
memory 304.
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Variable amplifier 302 is a programmable amplifier
which has the capacity of selectively offsetting input
signals and has the further capacity of varying the amplitude
range or gain of input signals. Variation of amplifier 302
is achieved through attenuation, offset and/or gain control
signals supplied from memory unit 304. An explanation of
the operation of variable or programmable amplifier 302 may
be had with respact to Fig. 3.
As ~xplained above, a conventional signal conditioner
~as illustrated in Fig. 3a has the capacity of setting the
gain or attenuation and offset of a single input signal. ' `
The subject invention envisions the utilization of a digital
system that in addition to controlling the order of commutation
also implements the functions of gain or attenuation and
offset compensation in which, in essence, the three resistors
218, 220 and 222 of the signal conditioner of Fig. 3a are
~replaced by three multiplying digital to analog converters
(MDACs) to create a variable or programmable amplifier.
Each of these MDACs can, for example, comprise eight bit or
12 bit devices in accordance with the ultimate accuracy
desired. The value of each MDAC for a particular setting is
programmed by digital operational information stored in
,memory unit 304 of Fig. 2.
As is known to those skilled in the art, MDACs are by
their nature essentially attenuation devices and accordingly
;the circuit of Fig. 3a needs to be modified so as to lend
itself to the application of MDACs. The gain function
normally controlled by resistor 222 is preferably supplemented
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by variation in resistor 220. Furthermore, the gain function
of resistor 220 is achieved either by raising the value of
resistor 220, which is difficult when utilizing MDACs, or by
attenuating the feedback signal supplied through resistor
220 which is a relatively easy operation for MDACs. An
analog network to achieve gain control by reduction in
feedback is illustrated in Fig. 3b.
In Fig. 3b resistors 218, 220 and 222 are supplemented
by the further employment of resistors 314 and 316. Resistor
,! .
10 1 314 is shown coupled between the output of amplifier 216 and
resistor 220 while resistor 316 is coupled between the
junction of resistors 220 and 314 and bias v'. By dividing
or attenuating the output of amplifier 216 through khe
employment of resistors 314 and 316, a reduced signal at the
.1 .
; ll junction of resistors 314 and 316 is provided to drive
!! resistor 220. Since the technique oE signal attenuation i5
¦~ employed in the arrangement shown in Fig. 3b, resistors 220,
314 and 316 can be simply replaced b~ a gain MDAC 318 as
l illustrated in Fig. 3c. Furthermore, resistor 218 can be
ao t¦ replaced by offset MDAC 320 illustrated in Fig. 3c and
- Ij resistor 222 can be replaced by attenuation MDAC 322 as
illustrated in Fi~. 3c. A more detailed illustration of the
programmable or variable amplifier illustrated in Fig. 3c is
shown in Fig. 4.
In Fig. 4 by way of example and not limitation a
variable amplifier means suitable for utilization in the
present invention is shown to comprise gain MDAC 318, offset
MDAC 320, and attenuation MDAC 322. The variable or programmable
amplifier further comprises input terminal 396 and output
~n terminal 398, and a reference bias source V.
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In accordance with the present invention, a preferredvariable amplifier means comprises first, second, and third
operational amplifiers illustratively shown in FigO 4 as
operational amplifiers 400, ~02 and 404. A variable amplifier
means in accordance with the present invention further
preferably comprises a first resistive network coupled
between the input terminal and an input to the first operational
amplifier. As illustratively shown in Fig. 4, a first
resistive network comprises resistors 406a through 406n and
resistors 408a through 408n. Resistors 406a through 406n
are series connected between input terminal 396 and an
appropriate source of bias B. Each first end of resistors
408a through 408n is coupled to a respective ends of resistors
406a through 406n closest to input terminal 396. The free
ends of resistors 408a through 408n are coupled respectively
through switches 410a throu~h 410n to a common negative
input of amplifier 400.
In accordance with the present invention, the variable
amplifier means further comprises an inverter coupled between
the output of the first operational amplifier and the output
terminal. As illustrativel~ shown in Fig. 4 amplifier 216
is coupled as an inverter between the output of amplifier
400 and output terminal 398.
Further in accordance with the present invention, the
variable amplifier means comprises a second resistive network
coupled between the output terminal and an input to the
second operational amplifier, the output of the second
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operational amplifier being coupled to the input of the
first operational amplifier. As illustratively shown in
Fig. 4, a resistive network comprising resistors 412a
through 412n and resistors 414a through 414n is shown coupled
between output terminal 398 and an input to differential
amplifier 402. Specifically, resistors 412a through 412n
are series~connected between bias V' and output terminal 398
while first ends of resistors 414a through 414n are coupled
to the respective ends of resistors 412a through 41~n closest
to output terminal 398. The second ends of resistors 414a
through 414n are coupled respectively through switches 416a
through 416n to the negative input of amplifier 402. An
addltional resistor 418 provides a feedback from the negative
input terminal of amplifier 402 to the output of amplifier
402. The output of amplifier 402 is coupled through resistor
420 to the negative input of amplifier 400.
In accordance with the present invention, the variable
amplifier means preferabl~v further comprises a third resistive
network coupled between the reference source and an input to
the third operational amplifier, the output of the third
operational amplifier being coupled to the input of the
first operational amplifier. As illustrated in Fig. 4,
again bv way of example and not limitation, resistors 422a
through 422n are respectively series-coupled to switches
424a through 424n and the resultant series combinations are
connected in parallel between bias V which serves as a
reference source and a positive input of amplifier 404.
Bias V is connected to the negative input of amplifier 404
by resistor 426. A feedback resistor 428 is coupled between
the negative input of amplifier 404 and the output of amplifier
404. The output of amplifier 404 is coupled by resistor 430
to the input of amplifier 400.
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In accordance with the present invention -the variable
amplifier means preferably further comprises means for
varying the resistive networks as indicated by operational
information stored in a memory means. As illustratively
shown in ~ig. 4, switches 410a through 410n, 416a through
416n and 424a through 424n comprise mechanisms whereby the
resistive networks of MDACs 318, 320 and 322 of Fig. 3c are
selectively varied by digital information which may, for
example, be stored in memory unit 304 of Fig. 2, with particular
digital signals representing operational information governing
the selective closing and opening of these switches. As
will be apparent to those skilled in the art, the more
ii .
resistors and switches employed in each particular MDAC, the
more precise the scale factoring and offset compensation
which can be achieved by the variable amplifer of Fig. 4.
In summar~ if the input signal :is to be amplified, MDAC
322 should have all or as many as possible switches 410a
through 410n closed and gain is achieved by closing an
appropriate number of switches 416a through 416n associated
with gain or feedback attenuation MDAC 318. If the input
signal is to be attenuated, switches 416a through 416n
associated with gain MDAC 318 are set to produce unity gain
from MDAC 318 and the attenuation function is controlled by
the setting of switches 410a through 410n of attenuation
MDAC 322. Offset MDAC is controlled by the setting of
switches 424a through 424n to generate either a positive or
negative output voltage of re~uired amplitude such that,
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when converted to a current by resistor 430, the injected
eurrent through resistor 430 is sufficient to cancel the
effects of any offset currents induced ky an asymmetrical
input signal to amplifier 400 of attenuation MDAC 322. In
the case of a symmetrical input signal, eentered around
zero, the output of offset MDAC 320 is programmed to produce
a zero eurrent through resistor 430.
Memory unit 304 of Fig. 2 provides means for storing
operation information for variable amplifier 302. Memory
lunit 304 is preferably a programmable read only memory
either erasable or non-erasable, although unit 304 may
comprise other forms of memory storage such as a random
aeeess memory.
Logie network 312 of Fig. 2 may simply eomprise a
~eounter which selectively energizes address loeations in
~'memory unit 304 interlaeed with sequential energization of
i'~switching meehanism 310 so that proper a-ttenuation offset
and gain operational information is supplied to amplifier
302 from memory unit 304 when eaeh input signal is connected
~0 Ito amplifier 302 by switehing meehanism 310. Logie network 312
may, however, inelude programmable memory means whieh seleetively
I
alters and varies the order by whieh switchanism 310 eouples
input signals to amplifier 302 as will be explained in more
detail in eonneetion with Fig. 8. Again, for eaeh input signal
;coupled to amplifier 302, logic network 312 assures that the
proper address of memory 304 is energized.
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Returning to Fig. 2, with amplifier 302 comprising, for
example, the variable amplifier illustrated in Fig. 4,
attenuation, offset, and gain information for memory unit
304 to amplifier 302 comprises digital information directed
to control the operation of switches 410a through 410n, 424a
through 424n, and 416a through 416n, respectively. The
output of amplifier 302 is coupled to transmitter 306 for
pulse amplitude modulation transmission from antenna 308 as
is well~known to those skilled in the art.
In operation of the commutating signal conditioner
illustrated in Fig. 2, an array of operational information
and order information is stored in address locations of memory
unit 304. Thus, logic unit 312 pro~:ides means for adjusting
the settings of variable or programmable amplifier 302 as
indicated by the stored operational :information in memory
unit 304 for each input signal 1-128 coupled to amplifier
302 through operation of switching mechanism 310 which is
also controlled by logic network 312~ More specifically,
; when, for example, logic network 312 closes the first position
2~ of switching mechanism 310 such that input signal 1 is
passed to amplifier 302, logic network 312 also accesses
addresses of memory unit 304 which provide digital operational
information to control the attenuation of amplifier 302, the
offset of amplifier 302, and the gain of amplifier 302 by,
~for example, setting switches 414a through 414n, 424a through
~424n and 416a through 416n, of Fig. 4, respectively, to
selected positions. In the same manner, for whatever input
signal logic network 312 determines is to be connected to
amplifier 302, logic network 312 also assures that amplifier 302
is first adjusted to the proper setting of that input signal.
1 ~ 6~3~
Thus gain MDAC 318 and attenuation MDAC 322 are controlled
by operational information stored in memory unit 304 to
achieve an output set to the required limits of transmitter
30~. For example, gain MDAC 318 and at-tenuation MDAC 322
may be selectively controlled by information stored in
memory unit 304 to assure that the output swing for each
input signal 1-128 is no greater than 5 volts peak-to-leak
whether centered about zero or not.
~ Furthermore, if the input signals 1-128 are not symmetrical
~,with respect to zero, offset MDAC 320 is controlled by
information stored in memory unit 304 to generate either a
~positive or negative output voltage of required amplitude
such that an output current from offset MDAC 320 injected
into the negative input of amplifier 216 is of suficient
amplitude to cancel the effects of an offset current induced
by an asymmetrical input signal through attenuation MDAC
322. Of course, in the case of a symmetrical input signal,
centered about zero, the output of oEfset MDAC 320 may be
programmed to produce a zero current.
2~ ~, In a series of sequential operations, loglc unit 312
~configures programmable amplifier 302 for proper attenuation,
offset and gain for each of the 128 input signals provided
to commutator 300. In this manner, reliable signal conditioning
is established with reduced component count, reduced volume,
reduced weight and expense but with increased reliability
and extreme flexibility over conventional systems with separate
signal conditioning and commutating functions. It should be
~further understood that while three MDACs are shown employed
in the illustrative example of a variable amplifier illustrated
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;in Fig. 4, the requirements of a particular set of input
signals might only necessitate the employment of one or two
of the MDACs illustrated in Fig. 4. It should also be
clearly understood that the present invention is not to be
~;limited to the employment of MDACs per se since MDACs are
merely illustratively shown as components which may be
; employed to provide one suitable example of a variable
amplifier ~or use in connection with the subject invention.
As will be apparent to those skilled in the art, amplifier
302 must be given time to establish proper operating conditions
before input signals are allowed by switching mechanism 310
to be communicated to amplifier 302. A potentially more
lefficient example of the present invention which expressly
,Ideals with the problem of setting a variable amplifier prior
to receipt of an input signal is illustrated in Fig. 5
wherein the input signals are divisible into first and
second groups, namely even channel group 500 and odd channel group
502 which groups are associated with first and second programmable`
' or variable amplifiers 504 and 506, respectively.
20 ~'l In accordance with the present invention, a commutating
signal conditioner including first and second variable
amplifiers further comprises commutator means for selectively
coupling the input signals to the first and second variable
, .
amplifiers. As illustratively shown in Fig. 5, commutator
1 508 operates to communicate even channel input signals 500
to amplifier 504 and commutator 510 operates to communicate
odd channel input signals 502 to amplifier 506.
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The embodiment of the commutating signal conditioner
~illustrated in Fig. 5 also includes a memory unit 512 which
provides means for storing operational information for
amplifiers 504 and 506.
; In accordance with the present invention, logic means
~are provided for setting the first and second variable
amplifiers as indicated by the operational information for
each input signal coupled to the respective amplifiers r the
logic means setting one of the amplifiers while the other of
the amplifiers operates on an input signal. As illustratively
shown in Fig. 5, logic network 514 addresses memory unit 512
~to ~et amplifiers 504 and 506 as indicated by operational
information stored in memory unit 512 for each input signal
from even group 500 and odd group 502 coupled to the respective
amplifiers 504 and 506. Logic network 514 operates, as will 'I
be explained below, to set one of amplifiers 504 to the
appropriate amplitude and offset compensation while the
other of the amplifiers operates on an input signal. The
,
~'outputs from amplifiers 504 and 506 are combined in combiner
1 516 to provide a unified pulse amplitude modulation signal
Isuitable for transmission.
A specific example of the embodiment of the subject
invention incorporating two variable amplifiers is illustrated
in Fig. 6. In Fig. 6, a first variable amplifier is illustrated
as comprising MDACS 600, 602, 604, and inverter 606. A
second variable amplifier is illustrated as comprising MDACs
` ~608, 610, 612, and inverter or operational amplifier 614.
: ~ MDAC 600 receives odd signals and is coupled at its output
to the input of inverter or operational amplifier 606. MDAC
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~602 provides an output current to the input of inverter 606
while MDAC 604 provides feedback attenuation control for
inverter 606. In a similar manner MDAC 608 receives even
signals and couples them to the input of inverter 614. MDAC
610 provides an offsetting current to the input of inverter
~614 and MDAC 612 provides feedback or attenuation control to
inverter 614.
The settings of MDACs 600 and 608 are governed by
;memory unit 616, the settings of MDACS 602 and 610 are
~0 ,governed by memory unit 618, and the settings of MDACs 604
and 612 are governed by operational information stored in
memory unit 620. Odd channel signals are coupled from the
output of inverter 606 to output terminal 622 by FET 624
¦with the conduction of FET 624 governed by odd logic control
f f signal Q0. The even channel signals are supplied from
inverter 614 to output terminal 622 through ~'ET 626 and the
i i
conduction of FET 626 is governed by even logic control
~signal Qe-
The commutating signal conditioner includes commutator
~ I
''means for selectively coupling the input signals in the ~ven
iand odd groups to the first and second variable amplifiersO
~s shown in Fig. 6, a commutator may, for example, comprise
,digital multiplexers 628, 630, 632, 634, 636, 638, 640, and
.642 which are coupled to receive input signals as illustra~ed
; in Fig. 6. Multiplexers 628, 634, 636 and 642 are shown
as receiving single ended input signals while multiplexer
632, 634, 638 and 640 are shown as receiving differential
signal which are coupled into single signals by differential
amplifier 660.
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Each of the digital multiplexers is illustratively
shown to receive eight different input signals and select
one of the eight input signals through a combination of Q
control signals whi~h comprise Q control signals Q100, Q10,
Qll, and Q12 for digital multiplexer 628, Q101, Q10, Qll,
and Q12 for digital multiplexer 630; Q101, Q10, Qll, and Q12
for digital multiplexer 632; Q107, Q10, Qll, and Q12 for
multiplexer 634; Q100, Q10, Qll, and Q12, for digital multiplexer
~ 636; Q106, Q10, Qll, and Q12 for digital multiplexer 638;
~ Q106, Q10, Qll, and Q12 for digital multiplexer 640; and
,
Q107, Q10, Qll, and Q12 for digital multiplexer 642. As
will be explained below, control signals Q10, Qll, Q12, and
Q100-Q107 are provided by a log.ic circuit to allow digital
"multiplexers 528 through 542 to pass particular ones of the
input signals in an orderly fashion t:o the first and second
variable amplifiers.
The commutator further comprises buffers 650 for the
output of each digital multiplexer. Digital multiplexers
628, 634, 636, and 642 are illustratively shown as receiving
. single ended input signals which are merely passed through
the multiplexers and buffers 650. However, for illustrative
ipurposes multiplexers 630, 632, 638 and 640 are shown capable
.of receiving differential ended input signals with the first
half of the odd differential input signals 17 through 31
being received by multiplexer 630 and the second half of odd
differential input signals 17' through 31' being received by
; multiplexer 632. The first half of even input signals 50
through 64 is shown received by multiplexer 638 while the
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I ~ ~;6~67
second half of differential input signals 50' through 64' is
received by multiplexer 640. The outputs of multiplexer 630
and 632 and the outputs of multiplexers 638 and 640 are
coupled through buffers 650 to differential circuits comprising
~resistors 652, 654, 656, and 658, and operational amplifiers
;6600 The junction of resistors 6S2 and 654, in each case,
is coupled to one input of an operational amplifier 660
while the junction of resistors 656 and 658 provides an
input for the second input to each operational amplifier
1~ i 660. The output of operational amplifiers 660 and the
output of buffers 650 for multiplexers other than 630, 632,
,638 and 640 are coupled to respective inputs of multiplexers
; ,~662 and 664 as illustrated in Fig. 6. Multiplexer 662 is
governed by control signals Ql~ Q3 and Q5 whereas multiplexer
664 is governed by control signals Q2, Q4 and Q6. ~he
output of multiplexer 662 is coupled to a buffer 666 to
pro~ide odd signals to the first variable amplifier while
`~the output of multiplexer 664 is coupled through buffer 668
Ito provide even signals to the input of the second variable
lamplifier.
A suitable logic network for the operation of the
commutating signal conditioner illustrated in Fig. 6 is
shown in Fig. 7 to comprise a 64 khz clock 670, a seven
stage counter 672, a first divide by eight unit 674, a
second divide by eight unit 676, a one-of-eight decoder 678
and an inverter 680. As will be apparent to one skilled in
the art, each count of clock 670 provides an odd control
signal QO while inverter 680 provides at its output an even
control signal Qe for each positive to negative swing of
clock 670.
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QO is inputted to divide-by-eight unit 674 to provide
outputs Ql, Q3, and Q5 whereas even control signal Qe is
provided as an input to divide-by-eight unit 676 to provide
control signals Q2, Q4, Q6. QO is also provided as an i.nput
to seven stage counter 672 which, in effect, divides by 128
to provide a binary count of 128 at outputs Q10 through Q16
Outputs Q10 through Q16 are also coupled to the inputs of
one-of-eight decoder 678 to provide a sequence of eight
unique outputs Q100 through Q107 during each 128 counts of
1~ cloclc 670-
The outputs of the logic network illustrated in Fig. 7
are coupled as indicated in Fig. 6. Namely, QO is coupled
to the gate of FET 624; Qe is coupled to the gate of FET
626; Ql, Q3 and Q5 are coupled to the digital control inputs
of multiplexer 662; Q2, Q4 and Q6 are coupled to the digital
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Ijcontrol inputs of multiplexer 664; Q10 through Q16 are
'Icoupled to the digital control inputs of memory units 616,
618 and 620; while Q10, Qll, Q12 and Q100 through Q107 are
coupled to the digital control inputs of multiplexers 628
through 642.
In operation of the commutating signal conditioner
illustrated in Fig. 6, operational information is stored in
~memory units 616, 618 and 620 indicative of the settings of
MDACs 600 ihrough 614 which are required to properly compensate
each input signal 1 through 128 at output 622. The memories
of memory units 616, 618 and 620 are sequentially energized
by control signals Q10 through Q16 to energize a particular
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set of addresses in the memory units for each input signal.
Multiplexers 628 through 642, 662 and 664 operate as is
well-known to those skilled in the art to provlde first an
odd signal at the output of buffer 666 and then an even
signal at the output of ~68 until each odd input signal of
the 128 input signals is coupled to the input of MDAC 600
and each of the even input signals is coupled to the input
of MDAC 608.
With the logic unit of Fig. 7 coupled as illustrated in
Fig. 6I MDACs 600, 602 and 604 pass an odd input signal
while MDACs 608, 610 and 512 are being set as indicated by
loperational information stored in memory units 616, 618 and
,620 to proper values for passage of the next even signal.
~Upon passage of the next even signal, MDACs 600, 602, and
~604 are being set as indicated by operational inormation
stored in memory units 616, 618 and 620 to pass the next odd
signal received at MDAC 600. The sequential operation of
MDACs 600, 602 and 604 and MDACs 608, 610 and 612 continues
until all 128 signals are coupled to ou~put terminal 622 at
,Iwhich point the operation is repeated as often as required.
ig. 8 illustrates a memory unit 680 which provides means
! ' ,i, for storing order information for determining the order of
connecting input signals 1-128 -to ampliiers 666 and 668 in
ig. 6. Memory unit 680 is positioned be-tween the outputs
Ql-Q6, Q10-Q12, and Q100-Q107 in Fig. 7 and the respective
inputs for these signals in Fig. 6. Accordingly, the use of
memory 680 in connection with Figs. 6 and 7 illustrates
one example of means for stepping the multiplexers of Fig. 6
in synchronism with adjusting the variable amplifiers of
80 Fig. 6 to couple input signals to the amplifiers when the
amplifiers are adjusted to properly condition the speciic
input signals being connected to the amplifiers.
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Additional advantages and modifications will readily
occur to those skilled in the art. The invention in its
broader aspects is therefore not limited to the specific
details, representative operations, and illustrative examples
shown and described. Accordingly, departures may be made
from such details without departing from the spirit or scope
of applicants' generally inventive concept, as claimed
herein.
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