Note: Descriptions are shown in the official language in which they were submitted.
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"PHASE DETECTOR CIRCUIT"
This invention relates to phase detector circuits.
This sort of the circuits are used for, fo~ example,
color signal processing circuits in video tape recorders
and the like.
In the recording of NTSC video signals on magnetic
tape with a video tape recorder, the luminance signal
and chrominance signal are separated from the video
signal to be recorded. The luminance signal is
frequency modulated ~ a frequency modulator, while
the chrominance signal is converted into a signal with
a low frequency subcarrier in a color signal processing
circuit. The frequency modulated luminance signal and
the converted chrominance signal are combined in a~
mixing circuit, and the resultant signal is recorded
on a magnetic tape by a magnetic head. In the color
signal processlng clrcuit, the subcarrier frequency of
the chrominance signal is converted from fsc = 3.58 MHz
to (44 - 4)fH (fH denotes the frequency of the
horizontal~sync signal). The color signal processing
circult lncludes a converting~ signal generator for
converting the original chrominance into the converted
chrominance slgnal. The converting signal has a
frequenc~y of the sum of the original subcarrier
frequency (3.58 MHz) and the;converted subcarrier
frequency (688 kHz), and is synchronized to the
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` ~ horizontal ~i~ signal. The converting signal is
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also controlled such that it can be used as a hurst siynal.
An automatic frequency control circuit (abbreviated
as AFC circuit) synchronizes the converting signal
frequency (3.58 MHz -~ 688 kHz = fsc + 4 fH)
horizontal s~nc signal frequency. The automatic
frequency control ~ircuit includes a voltage-controlled
oscillator (abbreviated as VCO), a frequency divider for
dividing the frequen~y oscillated from the VCO output,
an integrating circuit for integrating the frequency
divider output and generating a sawtooth wave signal,
and an AFC detector to which the sawtooth wave signal
(which is a compared pulse signal) and the horizontal
sync signal (which is a reference pulse signal) are
coupled. The ~FC detector provides an output which
corresponds in voltage to the phase difference between
the sawtooth wave signal and the horizontal sync signal.
This output is applied to a frequency control terminal
of the VCO. The output of the VCO is thus synchronized
in frequency to the horizontal sync signal. The circuit
described above is termed an AFC loop.
In the AFC loop described above, it is important
that the sawtooth wave signal generated from the
integrating circuit has steady slant portions, that is,
the slant portions of the sawtooth wave signal have good
linearity. However, the characteristics of resistors
; and capacitors that are employed in the i~tegrating
circuit are susceptible to tempexature changes, which
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causes the slan-t portions of the sawtooth wave signal to
fluctuate.
The sawtooth wave signal output from the
integrating circuit is given as a function Ao which is
t
Ao = Eo~l - eR~),
S Eo: the amplitude of the pulse input to the
integrating circuit,
t : time in second,
RC: the time constant of the integrating circuit.
The slope n of the sawtooth wave signal is thus
n = ~C eRC (V/sec)
where 0 ~ t < T ( T being the pulse width of pulse input
to the integrating circuit). It will be seen from the
above equation that the slope of the output sawtooth
wave signal is inEluenced by changes of the time
constant with temperature change. This means that the
sensitivity of the AFC detector circuit is also changed
with temperature change. Under the constant sensitivity
of the AFC detector~circuit, an output voltage from the
AFC detector circuit~ is in proportion to a phase
difference between the sawtooth wave signal and.the
horizontal sync signal always changes linearly in
accordance with the change of the phase difference.
Where the sensitivity of the AFC detector circuit
varies with temperature change in the above described
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conventi.onal AFC detector cir~uit which employs an
integrating circuit~ an accurate output siynal can no
longer be obtained. Besides, the slant portions of the
output of the conventional integrating ~ircuit employing
the time constant ~ircuit is non-linear, so that the draw-
in frequency and the hold frequency of the AFC loop with
respect to the ~enter frequency cannot be equalized.
Further, in case of fabricating the AFC loop employing
the conventional integrating circuit on an IC chip, the
capacitor for the time constant circuit cannot but be
constructed in an external circuit to the IC chip, so
that the large number of connection pins cannot be
reduced.
An object of the invention is to provide a phase
detector circuit, which alleviates the adverse effects
of temperature changes and has steady and stable sensi-
tivity of phase difference detection when detecting -
phase difference among a plurality of signals and also
reduces the number of required terminal pins in case of
implementing on an IC circuit.
For achieving the above object, the phase detector
circuit according to the present invention comprises:
a phase detector including a first differential
amplifier and a second differential amplifier, a
reference pulse signal and a comparison pulse signal
being applied to f irst in.put terminals of said
respective first and second differenti.al amplifiers,
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preset bias voltages of first and second DC blas voltage
sources being applied to second input terminals of said
respective first and second differential amplifiers,
said second differential amplifier providing from an
output terminal thereof a phase detection pulse of a
pulse width proportional to the phase difference between
the reference pulse and comparison pulse,
a buffer circuit connec-ted to the output terminal
of said second differential amplifier, for extracting
said phase detection pulse output,
a gate circuit connected to an output terminal of
said buffer circuit, a current path of said buffer
circuit between a phase detection pulse input terminal
and an output terminal being on-off controlled by said
reference pulse signal, said buffer circuit providing an
output pulse while said current path is in the "on"
state, the pulse duty of said output pulse varying
according to the pulse width of said phase detection
pulse, and
a filter for receiving the output of said gate
circuit.
This invention can be more fully understood from
~the following detailed description when ta~en in
conjunction with the accompanying drawings, in which:
Fig. l is a block diagram showing a color signal
processing circuit to which the present invention is
applied;
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Fi~ . 2 is a circuit diagram showing ~n embodiment
of the present invention; and
Fig. 3 is a waveform diayram showiny siynal wave-
forms at various parts of -the circuit of Fig. 2 with the
letters designating the waveforms indicating the part in
Fig. 2.
Fig. 1 shows a color signal processing circuit for
a video tape recoxder (VTR), particularly a circuit for
recording operation. The color signal (with subcarrier
having frequency of 3.58 MHz) separated from the video
sigrlal is applied through an input terminal 11 to a first
input terminal of a first balanced modulator 12 and then
converted to a low frequency converted color signal des-
cribed later in detail. The converted color signal is then
filter~d out through a filter 13 to an output terminal 14.
The original color signal is also applied to an
automatic phase control detector (abbreviated as APC
detector) 15 which constitutes part of an automatic
phase control loop (APC loop). In the APC detector 15
the burst signal included in the original color signal
is compared in phase with the output (at ~.58 MHz)
from a first VCO 18 among the gating period according
to the burst pulse. The resultant voltage which corres-
ponds to the phase difference between the burst signal
and the output of the first VCO 18 is sampled and held
by a follo~ing sample-and-hold circuit 16 under the
control of the burst gating pulse. The output
voltage of` the sample-and-hold circuit 16 is
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coupled throuyh a low~pass filter 17 to an oscillation
frequency control terminal of the first VCO 1~. Thus,
the output of the first VCo 18 is locked in phase to the
burst signal.
The output of the VCO is also fed to a first input
terminal of a second balanced modulator 19. To a second
input terminal of the second balanced modulator 19 is
fed an output (688 kHz) of a frequency divider 29, which
divides the frequency (2.7 MHz) of the output of second
VCO 27 to 1/4.
The output of the second balanced modulator lg
thus has a frequency of 3.58 MHz ~ 688 kHz or roughly
4.2 MHz. This output (4.2 MHz) is applied through a
filter 20 to a second input terminal of the first
balanced modulator 12 as a converting signal. The
original color signal is modulated at the first balanced
modulator 12 with the output or the converting signal
from the filter 20. As a result, the low frequency
converted color signal is obtained at the output
terminal of the first balanced modulator 12.
The second VCO 27 is automa~ically frequency
controlled such that its output frequency
~(175 x fH =~27 MHz) is synchronized to the horizontal
sync signal frequency (fH).
~ In the color signal processing system for a video
tape recorder, the frequency (688 kHz) of the low
frequency converted color siynal has to be synchronized
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to the frequency (fH) of the horizontal sync sign.al
included in the video sign.al. Accordinyly, this is
because of the :Eact thak the horizontal sync signal
variations have effects upon the color signal hase
variations. The circuit that is involved is designed
to maintain a constant relation of the low frequency
converted color signal frequency and horizontal sync
signal frequency to each other.
The video signal is ~ed through an input terminal
10 21 to a sync separator 22. The sync separator 22
separates the horizontal sync signal from the video
signal. The horizontal sync signal is applied to a
first input terminal of a phase detector multiplier 23
and also to a gating pulse input terminal of a gate
circuit 25 both being included in an AFC loop. To a
second input terminal of the phase detector multiplier
23 is applied the output (5fH) of a frequency divider
28, which divides the output frequency (175 x fH = 2.7
MHz) of the second VCO 27 to 1/35.
Phase detector multiplier 23 detects the phase
difference between the horizontal sync signal and the
frequency divider output, and provides a phase detection
pulse output which corresponds to the deviation from
synchronization between the horizontal sync signal (at
fH = 15.73 kHz) and the frequency divider output (at
5fH). The phase detector output pulse is applied
through a bu~fer 24 to the gate circuit 25~ In the gate
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circuit 25, the path between i-ts phase detection pulse
input terminal and output terminal is enabled, i.e. ren-
dered conductive, during the horizontal sync signal period,
thus producing an output pulse of a pulse dut~ proportional
to the pulse width of the phase detection pulse.
The invention can be effectively applied to the
circuit composed of the phase detector 23, buffer 24 and
gate circuit 25 shown in Fig. 1. 6
Fig. 2 shows a specific circuit construction of an
embodiment of the invention. Referring to the Figure,
labeled el is a reference pulse signal (for instance the
horizontal sync signal) from a first signal source such as
in the Fig. 1 embodiment the signal from sync separation
circuit 22, and labeled e2 is a compared pulse signal (for
instance a frequency divider output such as in the Fig. 1
embodiment the signal from frequency divider 28) from a
second signal source (for instance a VCO). Labeled El is a
first DC bias voltage source, and labeled E2 is a second DC
bias voltage source. The second DC bias voltaqe E2 is
applied to the base of a transistor Ql The transistor
Ql has its collector connected to the first DC bias
voltage source El and its emitter connected in series
with resistors Rl and R2 to a reference potential
terminal. The emitter of the transistor Ql is also
connected in series with resistors R3 and R4 to the
collector of a transistor Q2. The transistor Q2 has
its emitter connected to the reference pote~tial
terminal and upon its base the aforemention~d
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reference pulse siynal el P
The compared pulse signal e2 is applied to the
base of a transistor Q3. The first DC bias voltage
source El is connected throuyh resistors R5 and R6 to
the collector of the transistor Q3, and this collector
is connected through a resistor R7 to the base of the
transistor Q4. The transistor Q4 has its emitter
connected to the reference potential terminal and its
collector to h~ the DC bias El -i{.~ d through
resistors R8 and Rg. The collector of the transistor
Q4 is also connected through a resistor Rlo and a diode
Dl to the reference potential terminal. The diode D
is a temperature compensation diode.
The juncture between the resistors R1 and R2 is
connected to the bases of transistors Q6 and Q13' and
the juncture between the resistors R8 and Rg is
connected to the base of a transistor Q8. In other
words, the potential at the junc-ture between the
resistors Rl and R2 is set as the base bias for the
transistors Q6 and Q13~ and the potential at the
juncture between the resistors R8 and Rg is set as the
base bias for the transistor Q~. Transistors Q5 and
Q6 form a first differential amplifier A, transistors
Q7 and Q8 form a second differential amplifier B, and
transistors Q12 and Q13 form a third differential
: amplifier _.
~he reerence pulse el is applied through the
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transistor Q2 and resistor R4 to the base of the b
transistor Q5 of the first differential amplifier A
and also to the base of the transistor Q12 of the second
differential amplifier C. The compared pulse signal
e2 is applied through the transistor Q3 and resistor
R6 to the base of the transistor Q7 of the second
differential amplifier B. The transistors Qs and
. Q6 have their emitters commonly connected to the
collector of a transistor Qg which forms a current
source. The emitter of the transistor Qg is connected
through a resistor R12 to the reference potential
terminal. The first DC bias voltage source El is
connected to the collector of the transistor Qs, and
the transistors Q7 and Q8 have their emitters common~y
connected to the collector of the transistor Q6. The
first DC bias voltage source is directly connected to
the collector of the transistor Q7, and it is also
connected through a resistor Rll to the collector of
the transistor Q8. The collector of the transistor Q8
is also connected to the base of a transistor Qlo which
is a component el.ement of the buffer 24.
The first differential amplifier A is constituted
by the transistors Q5 and Q6 and the second differential
amplifier B is constituted by the transistors Q7 and
Q~ form the phase detector 23.
The transistor Qlo of the buffer 24 has its
collector to which the first DG bias voltage source
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El is connected and its emitter connected to the
collector of a transistor Qll The transistor Q11 forms
a constant current source, and its emitter i5 connected
to the reference potential terminal. The emitter of the
5~ transistor Qlo is connected to the output terminal of
the buffer 24, and it is connected through a resistor
Rl4 to the base of a transistor Ql4-
The transistors Q14' Ql2 and Ql3 form the g
circuit 25. The collector of the transistor Q12 is
connected to the base of the transistor Ql4~ which has
its emitter connected to the collector of the transistor
Q13 The first DC bias voltage source El is connected
to the collector of the transistor Ql4 The transistors
Ql2 and Q13 have their emitters commonly connected to
lS the collector of a transistor Ql5 which forms a constant
current source. The emitter of the transistor Ql5 is
connected through a resistor Rl5 to the reference
potential source. The emitter of the transistor Ql4 is
connected to the filter 26.
A series circuit including a resistor Rl6, a diode
D2 and a resistor R17 sets the base bias for the
constant current source transistors Qg~ Q11 and Q15-
The diode D2 serves the roles of bias setting and
temperature compensation~ The current through the
collector-emitter path of the transistor Qg is set
equal to the çurrent through the diode D2. In other
words, the current path formed by the transistor Qg
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and resistor Rl2 and that by -the resistor Rl6, c1iode
D2 and resistor Rl7 form a current mirror circuit.
The operation of the phase detector 23, buffer
24 and gate circuit 25, having the above construction,
will now be described. It is now assumed that the
reference pulse signal el and compared pulse signal e2
are related to each other as shown in (a) and (b) in
Fig. 3. When the reference pulse signal el goes to a
high level, the potential of the collector on the -tran-
sistor Q2 is reduced. In consequence, the signal -to the
base of the transistors Q5 and Ql2 goes to a low level
as shown in (c) in Fig. 3. When the compared pulse
signal e2 goes to a high level, the collector potential
on the transistor Q3 is reduced. In consequence, the
signal to the base of the transistor Q7 goes to a low
level as shown in (d) in Fig. 3. The transistors Q6 and
Q8 are both on state during a period t shown in (e) in
Fig. 3. During this period t, a pulse as shown in (e)
in Fig. 3 prevails at the base of the transistor Qlo. The
current through the transistor Qlo is controlled by the
pulse shown in (e) in Fig. 3.
When the reference pulse el goes to a high level,
the transistor Ql2 is cut off, while the transistor Ql3
is tr1ggered. (While the reference pulse el is at the
low level, the transistor Ql2 is "on" and the transistor
Ql3 if "off".). Thus, the base potential o~ the
transistar Ql4 is increased when the transistor
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Q12 is cut off and is reduced when the current through
the transistor Qlo is subsequently controlled. The
signal to the base of the Q14 thus has a waveform as
shown in (f) in Fig. 3, and a signal as shown in (g) in
Fig. 3 appears from the emitter of the transistor Q14
In other words, in the gate circuit 25, the current path
between the phase detection pulse input terminal and
output terminal is conductive while the reference pulse
el is at the high level, and during this period the
pulse duty of the output pulse is set. When the
reference pulse and compared pulse go to high level at
the same time a phase detection pulse can be obtained,
a pulse width of said phase detection pulse proportion
between the reference pulse and compared pulse, to the
collector of transistor Q8 Thus, the output (as shown
in (h) in Fig. 3) of the filter 26 can be utilized as a
voltage which corresponds to the phase difference
between the reference pulse and compared pulse.
The current I through the emitter of the transistor
Q9 in the automatic frequency control phase detector 26
is given as
I = R +R R ---; (1)
VF : the forward voltage across the diode D2,
R12: the resistance of the resistor R~2,
~16: the resistance of the resistor R16,
R17: the resistance of the resistor R17.
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This means that the current path constituted by the
resistor Rl6, diode D2 and resistor R17 and that
constituted by the transistor Qg and resistor R12 form
a current mirror circuit.
The sensitivity ~ of the phase detector 26 is
given as
Rl6+Rl7 Rl2' ~ /sec) ---- (2)
under the assumption that T 1 _ T2 where T l is the pulse
width of the reference pulse el and T 2 is the pulse
width of the compared pulse e2.
As is seen from the above equation, the sensitlvity
of the phase detector is determined by the resistance
R17 Rll Since the resistOrS Rll~ 12 16
R17, etc. can be realized as distrlbuted resistance
within a semiconductor integrated circuit, the error of
the aforementioned resistance ratio R +R R - can be
held within 3%.
Thus, sufficiently high precision of the
sensitivity can be obtained. Also, satisfactory
linearity of the sensitivity can be obtained as is seen
from equation (2).
In equation (2), only VF is dependent upon~the
temperature. If the circuit constants are selected such
that El ~ VF and Rl6 >> Rl7, ~ can be appro~imated as
R17 Rll El
- R16 R12 Tl
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In this case, the temperature changes have practically
no influence upon the sensitivity.
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