Note: Descriptions are shown in the official language in which they were submitted.
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Descri~on
USE OE` NODES TO ~NIQ~ELY IDENTIFY PROCESSES
Back~round of the Invention
1. Field of the Invention
This invention relates to a method for identifying a
process of an electronic digital signal processor. In
particular, it pertains to the use of nodes to construct a
nodal address to uniquely identify a process when more than
one copy of the process exists in the system.
2. Description of Prior Art
Electronic digital signal processing systems have been
developed for the processing of work requests in a real
time environment. These systems have utilized an operating
system in which a process was created and deleted for each
work request. Such electronic digital signal processing
systems require additional time and added memory size
requirements.
An electronic digital signal processing system for
processing work requests has been developed with an im-
proved work request scheduling system resulting in an
improved response time and smaller memory size require-
ments. The improved scheduling mechanism has been designed
which separates the process from the routines that execute
the individual work requests. The process in such a system
becomes a dispatchable entity and operates to execute work
requests assigned to a queue associated with each process.
A need has arisen for a method to uniquely identify a
process within such a system, particularly when at least
one of said processes may be replicated within the system.
A further need has arisen to more efficiently allocate the
execution of work requests by processes in multiprocessor
systems linked together by a data buss.
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SummarY of the Invention
The present invention provides a method for identifying
a process in a unique manner when more than one copy of the
process exists in an electronic digital signal processing
system such that the identified process may be moved within
the system or to another system without code modification.
A process is defined to be a functional unit consiting
o~ a predefined stack, a process control block, and a pre-
defined sequence of instructions t:o be operated in response
to a work re~uest queued to that process in an electronic
digital signal processing system. The process is assigned
a unique identification code, cal].ed a Process ID (PID).
The process functions as a dispatchable entity in an
electronic digital signal processing system for the exe-
cution of a predefined sequence of instructions for a work
request assigned to the process.
One or more processes are logically grouped together to
define a node. The nodes provide a means for identifving
the processes within a uni~ue node address. Each node
address consists of a primary node identifying an electronic
digital signal processor and a subnode or subnodes iden.i-
fying a process or logical grouping of processes within
that processor's system. A nodal address comprises the
combination of the node ID for a processor and a process
within a processor with the Process ID (PID) to uniquely
identify any process in that environment. This combination
o the node ID and PID allows development programmers to
design and implement software routines to communicate with
the various processes in other systems central processors,
using the same software interfaces as they would to communi-
cate with processes in the same central processor.
Brief Description of The Drawings
For a more complete understanding of the present in-
vention and further advantases thereof, reference is now
made to the following description taken in conjunction with
the following drawings:
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FIGURE 1 is a block diagram of a word processing system
for implementing the present invention;
FIGURE 2 is a block diagram of a system with a single
processor and a plurality of processes defined within a
single subnode;
FIGURE 3 is a block diagram of a single processor with
a plurality subnodes;
FIGURE 4 is a block diagram of a single processor with
a plurality o~ processes defined within a plurality of
subnodes;
FIGURE 5 is a block diagram of a multiprocessor environ-
ment;
FIG~RE 6 is an example of a node address table format
for a central processor; and
FIGURE 7 is an example of a process address table format
for a plurality of processes within a processor.
Description of the Preferred Embodiment
Referring now to FIGURE 1, a block diagram of a word
processing system implementing the present invention as
illustrated. A keyboard 10 is provided for inputting
graphic characters, data, and instructions to the word
processing system. The keyboard 10 applies its input to
the system through a data buss 12 to a central processor 14
of the system. A processor 14 may be implemented by a
commercially available microprocessor, such as the Intel*
8086 processor.
The keyboard 10 also applies a hardware interrupt
signal via interrupt line 16 to an interrupt arbitrator 18.
The 825~-A Intèrrupt Controller was selected to implement
the interrupt arbitrator 18 to resolve interrupt requests
from the incoming interrupt lines of the system. The 8259-A
Interrupt Controller may resolve interrupt requests from up
to eight interrupt lines into eight priority levels for the
processor 14.
*Trade Mark
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The processor 14 forms the various control functions
necessary for the word processing system to process, edit
and display data. The processor 14 is connected by a memory
buss 20 to a random access memory 22 for storing system
data and programs. A visual display 24 is also connected
by the memory buss to the processor 14 for displaying data
and information for enabling communication between the word
processing system and its operator. A diskette drive 26
driven by the system clock 28 is also connected through the
memory buss to the processor 14. The diskette drives 26
comprise means for accessing the system programs loaded
from a program library onto the diskettes. Modules from a
program library may either be loaded or deleted fro~ the
diskettes. The word processing system may also include
other "DMA" devices 29 connected by the memory buss 20 to
the processor 14. The diskette drives 26 and other DMA
devices 29 provide hardware interrupts signals on interru?t
lines 30 and 32, respectively, to the input arbitrator 18.
A printer 34 communicates via a data buss 36 with
processor 14 for providing a printed record of data or
other information under the control of the processor 14.
The printer 34 also provides a hardware interrupt signal
via interrupt signal line 38 to the arbitrator 18. Other
processor input/output devices 40 may, of course, be ~ro-
vided as part of a word processing system. The processor
input/output devices 40 may communicate via a data buss 42
to the processor 14, and they provide a hardware interrupt
signal by interrupt signal line 44 to the arbitrator 18.
Referring to FIGURE 2, a plurality of processes 50 are
logically grouped together to define a subnode, SUBNODE-l.
SU~NODE-l may be part of a basic system as illustrated in
FIGURE 1, where only one primary node, PRI~ARY NODE-l, may
be defined for a processor 14. In the basic system of
FIGURE 1, all the processes 50 execute in one processor 14
(~RIMARY NODE-l), and tnus can be uniquely identified simply
by its PID.
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Referring to FIGURE 3, the system has only the single
processor 14 identified as PRIMARY NODE-l, and it includes
a plurality of processes 52 logically grouped together to
define SUBNODE-l. Process A of SUBNODE-l is further copied
in the system as process 54 and process 56, and these repli~
cated processes are grouped to define SUBNODE-2 and SUBNODE-3,
respectively. In this single processor system, the repli-
cation of Process A in SUBNODE-l, SUBNODE-2 and SUBNODE-3
may be representative of a print process which is available
for each printer in the system though the Process A for
performing the work request for printing is identical. In
this system environment, each printer would be considered
as a separate subnode within the PRIMARY NODE-l. In this
way the processor can address each uni~ue process associated
with its printer by use of the subnode address and PID.
Referring to a FIGURE 4, an electronic digital system
environment is presented where a plurality of work stations
are supported in the system by a single processor 14, identi
fied as PRIMARY NODE-l. Each of the three work stations in
the system include the same set of the plurality of processes
58, 60 and 62. The processes 58, 60 and 62 replicated in
this system are logically grouped together and identified
as SUBNODE-l, SUBNODE-2, SUBNODE-3, respectively. The
system presented in FIGURE 4 represents a modification of
the basic system illustrated in FIGURE 1, wherein the single
processor 14 is responsible for controlling not one but
three separate work stations.
Referring to FIGURE 5, a multiple processor environ~ent
is presented in which system processors 14, 64 and 66 may
communicate with one another through a common buss 68. The
processors 14, 64 and 66 may be uniquely identified by
their primary node IDs: PRIMARY NODE-l, PRIMARY NODE-2 and
PRIMARY NODE-N. Of course, each of the primary nodes illus-
trated in FIGURE 5 may include any number of processes
logically grouped together as subnodes, as illustrated in
FIGURES 2, 3 and 4.
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Referring to FIGURE 6, a Node Address Table (NAT) 70 is
illustrated for a processor, such as processor 14 of FIGURE
1. The NAT 70 defines the primary node ID 72 for the processor
and contains an entry 74 indicating the number of subnodes
within the primary node. Each of the subnodes is identified
by an entry 76 containing the address of a Process Address
Table (PAT) and a Lock Control Block ~LC8) for each of the
subnodes.
FIG~RE 7 illustrates a Process Address Table ~PAT) 80
and includes an entry 82 indicating the number of entries
representing the number of processes. Each entry in ~4 in
the PAT &0 contains the address of a Process Control Block
~PCB) for a process that is executing under that subnode,
or a zero if a process is not loaded under that subnode.
The node-process relationship will permit two or more
instances of a process to be executed simultaneously, each
in a different subnode.
In operation, this node-process identification combi-
nation uniquely identifies a process in any system environ-
ment. A systems development programmer may utilize this
nodal address to design and implement a software routine to
communicate with any of the various processes in processors
of other systems. Development programmers may use the same
software interfaces between compatible systems with the
combined node ID-process ID address in the same manner they
would use these interfaces to communicate with processes
within the same processor.
In order to schedule a work request, such as printing,
the word processing system would specify the process, e.~.,
Process A, to effect the printing of a document. The work
request instruction could identify the node ID selection
which would identify which processor in a multiprocessor
environment is to be assigned the task, and the subnode ID
could further identify the subnode. The process ID could
also be provided to identify the print process, Process A,
in a selected subnode to cause the printing of the document.
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