Note: Descriptions are shown in the official language in which they were submitted.
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DYNAMIC RANDOM ACCESS MEMORY
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TECHNICAL FIELD
: ~ The present invention pertains to semiconductor
: integrated circuits and in particular to a random access
memory which utilizes dynam:ic memory cells.
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BACRGROUND ART
The operation of previous dynamic random access
memory circuits is described in U.S. Pat~nt No. 3,588,844
and 3,514,765 to Christeneon, U.S. Patent No. 3,699,537
S to Wahlstrom and V.S. Patent No. 3,902,082 and 3,969,706
to Proebsting et al. As shown in the Wahlstrom and
Proebsting Patents, it has been the practice to use sense
amplifiers to detect voItage differentials on bit lines
which have had memory cells connected thereto. The
}0 ` connection of the memory cell to the bit line changes
the previously established voltage on the bit line to
estabish the desired data state as a voltage differential
on the bit lines. However, the voltage change on a bit
line caused by the connection of a memory cell thereto
lS is very smali and ~he detection of such a small voltage
- change has presente~ a serious problem in the design
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of dynamic random access memories. A further problem
is that electrical noise can be picked up by the bit
lines and his noise can mask the desired voltage offset
20 ~ produced by a memory cell. Further, integrated circuit
fabrication tolerances can result in unbalanced bit lines
which also interere with the reading of a memory cell.
In respo~se~to these problems, it has heretofore
been the practice to incorporate a dummy cell with each
blt 1ine of the memory. The dummy cells are precharge~
o a given voltage state and are connec~ed during each
memory cycle~to the nonselected bit line within each
pa~ir of bit lines. However, the inclusion of a large
number of: dummy cells :together with their associated
30~ circuitry in~reases~the si e of the integrated circuit
and adds to the ~ircu~t complexity.
In view of the above problems, there exists a need
for a dynami~ ran~om access memory which operates in
~such a method so as not to require-a dummy cell for
35 ~ each bit line while at ~he same time p~viAing reliable
identification~of the voltage states stored in the
-~ memory cells.
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~)ISCLOSURE OF THE INVENTION
The present invention provides a method for operating
a dynamic random access memory in the following steps. A
high or low voltage state is stored in a dynamic
S memory cell where the high vvltage state corresponds to
a first data state and the low voltage state corresponds
to a second data state. The memory cell is then connected
to one of a pair of bit lines after the bit lines have
been set to an intermediate voltage state. When a
memory cell storing a low voltage is connected to the
bit line, the voltage on the bit line is decreased. When
a memory cell storing a high voltage is connected to
the bit line, the voltage on the bit line is increased.
When the voltage state on one bit line is being changed
15 by the connection of a memory cell thereto, the ~
complementary bit line of the pair of bit lines is
maintained essentially at the intermediate voltage ~
state which had been set thereon. After the ~emory cell
; has been connected to one of the bit lines, the bit
20~ 1ine h~aving the~lowest voltage thereon is driven to
à low voltage~state~, and the other of the bit lines is
driven to a~ hlgh voltage state. The memory cell lS
disconnected ~rom the correspondi~g ~bit line after the
corresponding~bit line~has been~driven to either the low
25~ ~voltage ~tate or the high ~oltage state. After the
mèmory~cell has been disconnected from the corresponding
bit l~ine,~the b~its lines are connected together to
equilibrate the voltages~on the bit lines to establlsh
the intermediàte~voltage state in preparation for a new
`30~ ~cycle.
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BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present
invention and the advantages thereof, reference is now
~ade to the following description taken in conjunction
5 with the accompanying drawings in which:
FIGURE 1 is a schematic îllustration of the dynamic
random access memory in accordance with the present
invention; and
FIGURE 2 is a set of timing diagrams illustrating
the various signals which occur in the dynamic random
access memory illustrated in FIGURE 1.
FIGURE 3 is a schematic illustration of the sense
amplifier shown in FIGURE 1; and
FXGURE 4 is a schematic illustration of the pull-up
15: circuit shown in FIGURE 1.
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DETAILED DESCRIPTION OF THE INVENTION
The dynamic random access memory of the present
invention is illustrated in FIGURE 1. A memory address
is provided to the memory 10 through a group of address
lines 12. The address lines 12 are provided to each of a
plurality of row decoders such as row decoder 14. The
address lines 12 are also connected to each of a plurality
of column decoders such as decoders 16 and 17. The
address bits for the selected row line are provided in
parallel fashion through lines 12 at one time in the
memory cycle and the address bits for the selected column
are provided through lines 12 at a later time in the
: memory cycle. This is illustrated by the address waveform
: indicated as Ao~An shown in FIGURE 2.
15 ~ The row address bits select a row decoder such as
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~ 14 which in turn activates a row line 18.- The row line
: ~ 18 is connected to a dynamic memory cell 22 which
comprises an access transistor 24 and a storage capacitor
~ 6. The gate terminal of transistor 24 is connected to
:: : 20 the row line 18 and the source terminal of the a~c:ess
::transistor is connected to a first terminal of capacitor
26. The remaining: terminal of capacitor 26 is connected
` to~a ground node 28. The drain terminal of access
:transistor 24 is connected:to a bit line 30.
25~ ~ A~row line 20 is charged by a row decoder 21 and
is connected to a dynamic me~ory cell 32 which comprises
an access transistor 34 and~a~storage capacitor 36. The
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: : gate terminal of transistor 34 is:~connected to ~he row
;line 20 and the sour~e~terminal thereof is connected
;30 to a first terminal of the:~capacitor 36. The remaining
te~rminal of:capacitor 36 is:connected to the ground node
: 28.~ The~drain ter~inal of:transistor 34 is connected ~ :
to a bit ~Iine 38 .: ~ ~ ~
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When row line 18 is driven to a high v~ltaye state
the corresponding access transistor 24 is a~tivated
to provide a conductive path between the bit line 30 and
the storage capacitor 26. The voltage on a row line
S selected by a row decoder is illustrated by the timing
signal 40 shown in FIGURE 2. The sense amplifier 44
is activated in response to a latch signal which is
transmitted through a latch node 46. The latch signal
L is illustrated in FIGURE 2 as waveform 48.
The memory 10 includes an equilibration circuit which
~ comprises transistors 50 and 52 wherein transistor 50
: ~ has the source and drain terminals thereof connected
: ~ between bit line 30 ~nd latch nod 46 and transistor 52
has:the source and drain terminals thereof connected
: 15: between bit line 38 and the latch node 46. The gate
terminals of:transistors 50 and 52 are:connected to a
~: ~ : node~-54 wh:ich receive an equilibration signal E. ; The
equilibration~signal E is illustrated in FIGURE 2 as
wave~orm~56. When the equilibratio~n signal E is at ~ :
2~0;~bigh~voltage state~the transistors 50 and 52 are turned
on~thereby connecting~the bit lines 30 and 38 to node -
A:~pull-up~circuit 60 is connected to the bit line
3~hrough a line~62:.~ The pull-up~circuit 60 operates
25~ in~response:~to~prech~a~rge:signals P, P0 and P1 which are
Ilu~trated::~respect~ive:ly~as:wave~orms 63, 64 and 66 in
FIGURE~2. :A~similar:pull-up circuit 68 is connected to
bit line:38~thrQugh~line 70~ Pull:-up circuits ~0 and 68
d~etect~when~the voltag~e:on the~corresponding bit line
: 3~ is~above:a~:pre:set vol:tage level and, upon receipt of
the:precharge~signals~j:pulls the~it lin~ up to the supply
voltage:,~as:described~below.
Each~of~the blt~ ne~s~ia provided with a column
transistor fQr:routing da~a states~:into and out of the
35~: memory cells.~ Column transistor 74 has the source and
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drain terminals thereof connected between bit line 30
and an input/output line 76. The gate terminal of
column transistor 74 is connected to the column decoder
16. Likewise, a column transistor 80 has the drain and
source terminals thereof connected between bit line 38
and an input/output line 82. The gate terminal of column
transistor 80 is connected to the column decoder 17 which
responds to the same column address as does column decoder
16. The column decoders I6 and 17 activate selected
column transistors in response to the column address bits
received through address lines 12 to transfer data
states to and from an addressed memory cell.
The input/output lines 76 and 82 are connected to
an input/output circuit 84 which serves to transfer the
data states which are written into and read from he
memory cells. The data states are received fro~ external~
circuitry through a data input terminal 86 and transmitted
to external circuitry through a data output terminal 87
The operation of the dynamic random access memory
10 of the p~esent invention is now described in reference
to~FIGURES 1-4. It is assumed that this circuit operates
wi~th~a 5.0 volt power supply. ~A memory cycle is initiated
by~a row address strobe~(RAS) signal 90 wh ich goes to
an active~state~in a transition from~a high level to a
25~ low level.~ The~row address~bits~ are supplied to the row
decoder~14 as~ind~icated by the reference numeral g2a.
The row addr~ess bits~are received shortly after the RAS
s~ignal goes to~the aotive state. ~he row decoder 14
routes the row~enable signal 40 to the selected row line.
30~ When the row enable signaI 40 goes to the five
volt level~the access transistor 24 in memory cell 22
is rendered conduc~tive to connect the'storage capacitor
26 ~o the bit line 30~ The bit lines 3D and 38 have
`prevlously~been equillbrated to the voltage level of
35~ approximately 2.0~volts as shown~by waveform 96. If
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capacitor 26 has previously had a 5.0 volt level s~ored
therein, bit line 30 would be driven to approximately
2.3 volts as indicated by waveform 96a in FI~URE 2,
due to charge sharing between the capacitor 26 and bit
line 30. But if the capacitor 26 has previously been
discharged to ground the bit line 30 will be pulled to
approximately 1.8 volts as indicated by waveform 96b.
After the memory cell 22 has been connected to the
bit line 30 the latch signal L shown as waveform 48 is
pulled to ground potential. The sense amplifier 44
responds to the latch signal by pulling to ground
potential the one of the bit lines connected thereto
which is at the lower voltage. If capacitor 26 has
previously been discharged the voltage on bit line 30
lS will be that shown in waveform 96b where the voltage
is pulled to ground potential. But if the storage
capacitor 26 has~had a high voltage level stored
therein, as shown in waveform 96a, bit line 30 will
not be affected by the operation of sense amplifier 44.
20 ~ ut~if bit~line 30 has~been elevated in voltage shown
by waveform 96a, it exceeds the bit line 38 voltage, shown
as waveform 98,~so that bit line~38 will~be pulled to
ground as~shown~by~waveform 98a. But lf the;voltage on
b~it~lin~e 3~0~had~been~pulled down by the storage capacitor
2~5~ 26 the equilibration voltage on bit line 38 would not ~-
b~e~afected by~the~sense amplifier~44. This condition
is indicated~in~waveform 98b.~
A~ter the~ sense ~ampliier 44 has pulled one of the
bit~ nes to~ground and;after;~he precharge signal P
3Q ~ has~precharged the pullup circuits~60 and 68, the
pr~echa~rge~signals,~PO and~Pl are received to actlvate
he pull up circuits &0 and 68. ~The pull up circuits
d~etect~whlch one~of~the bit lines~has a voltage thereon
;above~a~prese~ voltage. One~ of the bit lines will be
àt ground potenti`al and the other o the bit lines will
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be at either the equilibration voltage or at the elevated
voltage caused by connecting a storage capacitor having
a high voltage stored therein. The bit line with the high
- voltage thereon will be pulled up to the supply voltage.
For the-bit lines which received a high charge from the
storage cell this is indicated by waveform 96a and for
the bit line which was at the e~uilibration voltage this
is indicated by waveform 98b. At this time the storage
capacitor which had been connected to the bit line has
been restored to its original voltage.
When one of the bit lines has been driven to the
supply voltage and the other ~it line has been pulled
to ground the column transistors 74 and 80 are turned
on to connect the bit lines 30 and 38 ~o the input/output
lines 75 and 82 respectively. The voltage states on the
bit lines are transferred through the input/output lines
to the inputjoutput circuit 84 which has a sense amplifier
therein to detect the voltage differential between the
input/output lines 76 and 820 ~The sense amplifier in the
~20 input/output circuit determines the voltage state which
is stored in the memory cell and transfers this voltage
state through the~data output line 87.
After one o the bit lines has been pulled to
ground~and the other bit line has been pulled to the
25~ supply voltage,~the data state in the memory cell has
been restored, and the row line 18 is returned ~o ground
to isolate the char~e on the storage capacitor. The
; bit lines are then~permitted to~float. The equilibration
~signal 56 is then applied to the gate `terminals of
30 ~ ~transistors 50 and 52 to render these transistors
con~uctive and connect bit line 30 to bit line 38 through
latch node 46. This connection permits the charge on
the bit~lines~to be shared such th~at the bit lines
eguilibrate to a voltage approxima~ely midway between
35; ~he supply voltage and ground. This is indicated in both
of the waveforms 96 and 98 where the waveforms are
returned to the equilibration voltage of two vo~ts.
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A representative circuit for the sense amplifier
44 shown in FIGURE 1 is illustrated in FIGURE 3. A
pass transistor 104 has the source and drain terminals
- thereof connected between bit line 30 and a node 106.
A second pass transistor 108 has a source and drain
terminals thereof connected between bit line 38 and a
node 110. The gate terminals of both transistors
104 and 108 are connected to a high voltage, such
as the supply voltage V~c. Transistors 104 and 108
are always conductive and functi~n as resistors. A
transistor 112 has the drain terminal thereof connected
to node 106 and the source terminal thereof connected
to the latch node 46. The gate terminal of tr~nsistor
112 is connected to node 110. A transistor 114 has the
drain terminal thereof connected to node 110, the source
terminal thereof connected to node 46 and the gate
terminal thereof connected to node ln6
~ The sense`amplifier operation occurs after a memory
cell has been connected to one of the bit lines, either
~20 30 or 38. One of the bit lines is then at a higher
voltage than the other bit line. Assume, for example~
that bit llne 30 is at the higher voltage. When the
. ~ latch signal~slowly~pulls node 4~ to ground, transistor
~; 114 will be turned on before transistor 112 because
the gate to source bias on transistor 114 is greater
han the gate to source bias on transistor 112. As
transistor 114 is rendered conductive node 110 will be
discha~rged through transistor 114 into the latch node
46. As node~ll0 is discharged the gate bias on transistor
30~ ;112~is 1owered~thus~preventing transistor 112 from being
rendered conductive~ When the latch signal is pulled
all the ~way to ground transistor 114 will continue ~to
be conduc~ive since bit line 30 and node 106 remain at
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the previous high charge state. As node 110 is
discharged, conduction through transistor 108 discharges
bit line 38. Thus, after the latch signal has gone
completely to ground bit line 38 will also be pulled
S to ground.
If bit line 38 is at a higher voltage after a
memory cell is connected to one of the bit lines,
transistor 112 will be rendered conductive to discharge
node 106 and pull bit line 30 to ground.
: 10 A schematic illustration for the pull-up circuits
60 and 68 is given in FIGURE 4. A transistor 120
has the drain terminal thereof connected to Vcc, the
source terminal thereof connected to a node 122 and the :
gate terminal thereof connected to receive the precharge
~15 signal Pr A transistor 124 has the drain terminal thereof
; :connected to node I22, the source terminaI thereof
connected to bit line 30 and:the gate terminal thereof
connected to receive the precharge signal P0.
: : A transistor 126 has the drain terminal thereof
20 ~ connected~to receive the precharge signal Pl, the gate
terminal thereof connected to node 122 and the source
terminal thereof connected to the gate terminal of
a~transistor:128. The drain terminal o transistor
: 128~is c:onnecte~ to the trcc~and the source terminal
25~ thereof~:is connected to bit~line~30.
:When~the precharge~signal P is received trans:istor
20:îs:rendered conductive to precharge node 122 to
a~high~oltag~state. Once~the:~precharge signal returns
to a~:low:voltag~ level the~node 122 is left floating
30~ :at the~;high~voltage ~talte.~ When the precharge signal
P~ goes to approximately 2 ~olts, transistor 124 is
rendered~onductive if the~bit line 30 is at a
ufficiently:low voltage state:such that there is at
least one~;`transistor threshold voltage between the gate
; 3~5 ~and source terminals of transistor 124. If transistor
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124 is rendered conductive node 12~ is discharged into
the bit line 30.
But if the charge on bit line 30 is sufficiently
high so that there is less than one transistor threshold
voltage between the gate and source terminals of
transistor 124, transistor 124 will not be rendered
conductive by the precharge signal P0, leaving node 122
floating at a high voltage level. The Pl signal is then
applied to the drain terminal of transistor 126. If node
122 is at a high voltage, transistor 126 is conductive
so that the source of transistor 126 follows signal P1
- above Vcc. This is possible since the channel capacitance
~ of transistor 126 bootstraps node 122 to a hiyh voltage
; level. With the full voltage level of bootstr~pped
precharge signal Pl applied to the gate ter~inal of
transistor 128, the full supply voltage Vcc is applied
to the bit line 3n, thereby pulling the bit line to the
voltage state of Vcc. Thus when the voltage on the
bit line 30 îs abov~ a preset level, the bit line will
be elevated to the supply voltage by opera~ion of the
precharge circuit 60, but if the vol~age on the bit
line 30 is less than a preset level, the precharge circuit
60 will have~no effect upon the bit line 30.
In ~summary,~the present invention comprises a
~dynamic random~access memory in which bit lines are
equilibrated to approximately one half of the supply
vol~tage before a memory cell is connec~ed thereto. A
sense amplif~ier detects the voltage dif~erence on the
bit lines caused by the connection of the storage
~capacitor to one of the bit lines and pulls the bit
line having~a~lower voltage thereon to ground~ A
pull up circult elevates the bit line having the greater
voltage thereon~ Af~er the voltage state is transferred
~hrough input~output lines and after the memory cell i5
isolated, the bit lines are permit~ed to float and are
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connected together through a latch node so that the bit
lines are returned to the equilîbration voltage as a
result of charge transfer between the bit lines.
Although one embodiment of the invention has
been illustrated in the accompanying drawings and
described in the foregoing Detailed Description, it
will be understood that the invention is not limited
to the embodiment disclosed, but is capable of numerous
rearrangements, modifications and substitutions without
departiny from the scope of the invention.
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