Note: Descriptions are shown in the official language in which they were submitted.
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~ 171~36
c~LlIsR~rrlQN SYSTEM FO _ S
B~CKGROUND OF T~E INVENTION
This invention relates to a system for calibrating
analog to-digit~l (A/D) conversions and, more particularly,
to a system for determining the transfer function of an
analog-to-digital converter based upon two reference points.
Modern building automation systems have combined
the advantages of digital processing equipment with the
monitoring of analog points. Sensors for measuring tempera-
ture, pressure, security lines and the like are typically
used for supplying the analog values or these analog
points. Because digital processing equipment is used in
such systems, it becomes apparent that~these analog signals
must be converted to digltal signals~for use b~ such equip-
ment. Thus, analog-~to-dlgital~converters have been desi~ned~
to fill this need.
One of~the problems ~ith analog-to-digital
converters, however, is that their transfer functions will ~
dri~t as a function of aging, changes in ambient temperature
in which the analog-to-digital converter oper~tes, and
manufacturing tolerances~ Thusj the outputs of the analog-
to-digital converter may vary over tlme; and from sample~to
sample even;for the~same~ input quantities.
SUMM~RY~OF THE IWVENTION
The present invent~ion simpli~fies the
an~log-to-digital conver~sion~cal~ibrdtion technique by~
supplying two;refe-ence points~oE the current trdnsfer~
function for use by the calibration apparatus. With~these
two reference points, the~ calibr;dtion appdratus can deter~
mine the trdnsFer~functio~n since th~e trdnsfer f~ n of
thc analog-to-digital converte~rs oE the present invention
~re substanti~lly linear.
: ~: : :
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~ 37113~
Thus, the present invention for determinin~ the tran~ ~ ~
sfer function of an analog-to-digital converter for calibrating ~ .
analog-to-digital conversions involves an analog-to~digital con-
verter, a reference apparatus for supplying first and second ref-
erence points, a connection device for connecting the reference -
apparatus to the input of the analog-to-digital converter, a ~ ~
calibration apparatus connected to the autput of the analog-to- ;
digital converter for determining the transfer functlon of the
analog-to-digital converter based upon the two referenoe points,
and a connector connect~ing the calibration apparatus to the con-
nection device for controlling the connection of the reference
apparatus to the analog-to-digital converter.
In accordance with the present lnvention, there is
provided a system for determining~the transfer function of an
analog-to-digital converter for callbrating analog-to-digital . ~:
conversions comprising: an analog-to-digital converter having an
input and an output; at least first and second reference means
for supplying correspondlng first and second reerence points,
at least one of said first and second reference means being a
resistor; connecting means connecting said reference means to the
input of said analog-to-digital converter; calibratlon means con- ;
nected to~the output of~said analog-to-digital converter for
calculating the transfer~ function of:said analog-to-digital con- ~ :
verter based upon said two reference points/ wherein said cali- :~
bration means applies said transfer~functlon to predetermined
; ~digital inputs for determining analog values; and said calibra-
tion means being connected to said::connection means for control- :
ling the connection of at least one of said: reference means to
`
said analog-to-digitaL converter,
BRIEF DESCRIPTION:OF THE DRAWINGS
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These and other features and advantages of the inven
.
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371136
\
tion will become more apparent from the detailed consideration
of the invention when taken in conjunction with the drawings in
which:
Figure 1 is a block diagram of the invention;
Figures 2A-2D show the multiplexer and the resistance-
to-period (R/P) converter of the analog-to-digital converter of
Figure l;
Figure 3 shows how the temperature dependent resistors
are connected to the multiplexer and resistance-to-period con-
verter of Figures 2A-2D; and,
Figure 4 shows the theoretical and actual transfer
function for the analog-to-digital converter shown in Figure 1.
DETAILED DESCRIP_ION
In Figure 1, muLtiplexer 50 is connected to two ref-
erence resistors REFl and REF 2 and four temperature sensing
resistors TRl-TR4. Under control of processor 300,
~`!, J - 2a
~ 3 r\~ ~3~
multiplexer 50 supplies analog signals, one ~t ~ time, to
resistance-to-period circuit 100 which is designed to
provide a pulse train output signal having a period
linearily proportional to the resistance of the resistors
connected to multiplexer ~0. This output is a digital sig-
nal since the time between pulses (the period) represents
the measured analog value. Digitizer 200 of the analog-to-
digital converter converts this period into a digitally
numerical value which is then supplied:to processor 300.
Di~itizer 200 has a control input from~pr~cessor 300 so that
it can be synchronized ~o muItiplexer 50. Connected to the
output of processor 300 is display circult 400 which may
take the form of a CR~, a printer or the like. Digitizer
200 may be man~fac~ured under part number 14502568-001 and
is used in the 1200 DGP (Da.a;Gathering Panel) of the Delta
1000 Building~Automation Con~rol manufactured:b~ ~oneywell~
Processor 300 is used in the same DGP and is made u~der part
number 1~502566-001.
Multiplexer 50 and resistance-to-period circuit
100 are shown in more detail in Figures 2A-2D. These
Figures are labeled with the pin numbers used in the serîes
1200 DGP of~t~he Delta I000 to show how multiplexer 50 and
resistance-to-period circuit I00 ma~ be interconnected~with
digitizer 200;and processor ~300.
In Fi~ure 2A, coun:ter ~sect~ion 1 is comprised of
c4unter 2 connected ~o two:flip-flops~3 and 4. ~The clear~ ~ :
terminal of counter~ 2 is connected to power c:lear :input ter- ;
minal TP58 as i~s the set terminal of f~lip-flop 3. When pow-
er clear terminal TP58 goes low, counter 2 is cleared and
the Q output of flip-flop 3 goes low. :After the:power sup-
: . ~
ply has stabilized, power clear t~rminal TP58~ill resume
its hi~h st~te. When processffr 300 issues ~n ~dvance pulse
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~ 37113~
on terminal TP~, coun~er 2 w~ll be lo~ded t~ a count o~ 4and the Q terminal of flip-~lop 3 will go hi~h. Terminal
~P4~ is ~ clock signal and will be repetitively pulsed.
However, until a Datachain signal is received on terminal
TP62, further Advance pulses ~fter the initial Advance pulse
on terminal TP4~ will have no effect on the system~ ~qhen
Datachain terminal TP62 goes high, the next Advance pulse
will switch flip-flop 4 to provide an enable signal to
counter 2 and will also enable ~ND gates 5 and 6 to begin
decoding the output of counter 2. Counter 2 will continue
to lncrement~ un~il it reaches a count of 15 when pin lS of
the counter goes high to provide the Datachain~out signal on
terminal TP31. Thus, i more than one multiplexer 50 and
resistance-to-period circuit 100 are~used in the system
associated with processor 300, the circuits SO and 100 may
be connected in daisy chain fashlon;so that the Datach~in
out terminal~TP31 is connected to the next succeeding
Data~chain terminal TP62. ~ccordingly, when circui~t 50 sho~n
in Figures 2A-2D is finished multiplexing its input
resistors throuyh resistance-to-period converter 100, the
next circuits 50 and 100 are energized to multiplex the
associated r~esistors. ~ ;
The~next ~dvance pulse after pin 15 of counter 2
goes high wi~ll reset flip-flop 3,~will ;cause the~value~of
counter 2 to~be n and will drlve the Datachain out signal on
TP31 low. Therea~ter, the next Advance pulse on terminal
TP44 will cause counter 2 to ~e loaded to a count of 4 and
drlves t~he Q termlnal of flip-flop 3 high. Counter sectlon
~: , : ,~
1 is now in a state to receive the next ~atachain signal on
TP62 to begln its multiplexing function once agdin. Counter
2 may be supplled under the stdndard~ pdrt number 1.S161 rnd ~
:
3 ~;
flip-flops 3 and 4 may be supplied under the standard part
numbers I.S74.
Each of the resistors REF ~, REF 2 and TRl-TR4
sho~7n in Figure 1 is connected between constant current
source circuit 7 shown in Fiyure 2A and the signal
multiplexing and amplification circuit shown in Figure 2C.
For example, one of the temperature responsive resistors TRl
is shown in Fiqure 3. This resis~or has its first end
connected to output terminal TP3 and its second end
connected to ground terminal TP212~ shown in Fîgure 2A.
Similarly, the first end of resistor TRl is connected to
input terminal TP42 and the second end is connected to input
terminal TP8 of the signal multiplexer and amplification
circuit 8 shown in Figure 2C.
Constant current source circuit 7 of Figure 2~
comprises constant current source 9 ha~ing series connected
resistors 10 and 11 connected bet~een a positive source and
ground. The junction of resistors 10 and 11 is connec~ed to
the non-inverting input of amplifier 12 the output of which
is connected to the base of P~P transistor 13 the emitter of
which is connected through resistor 1~ to the positive
source and the collector of which is connected to input pin
~ of multiplexer 15. The inve~ting input of amplirier i2 is
connected to the junction of the emitter of transistor 13
and the resistor 14. Under the:control of decoder 5 which
decodes the output from counter 2, the constant current
supplied by constant current source 9 is multiplexed between
output terminals TPS9,~TP37, TPl~and TP3-a~s well:as to the
re~erence resistors REF ] and REF 2 shown in Pigure 2A. All
six outputs from multiplexer 15 have:series connected
resistors therein an~l the four outputs from multiplexer 1:5
to temperature responsive resistors TRl-TR4 are connected to
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3 ~
ground through cap~citor b~nk 17. ~esistors 15 and
cap~citors ].7 provide static protection or constant current
source circuit 7~
As shown by Figure 3, each of the reSlStoES
TRl-TR4 receives constant current from multiplexer 15 and is
also connected to the signal multi~lexing and amplification
circuit 8, as ~re reference resistors REF 1 and RE~ 2 as
s'no~n by terminals G, H, I and J.
In Figure 2C, signal multiplexing and ampli'ica-
tion circuit 8 is comprised of mul~iplexers 20 and 21 each
having their control input terminals connected to terminals
D, E and F from decoder 6 shown in Figure 2~. ~ecoder 6 is
essenti~lly the s~me as decoder 5 so th~t the resistor to
which constant current is supplied by constant current
multiplexer 15 will also be the resistor connected through
signàl multiplexers 20 and 21. E~ch multiplexer 20 and 21
has corresponding resistor and capacitor static protec~ion
circuits 26 and 27 in the same form as that for multiplexer
li. Fur~her, pins 3 of multiplexers 20 and 21 are the out-
put terminals for these multiplexers and are connected to a
corresponding input terminal of amplifier 22. Resistors 23,
24 and 25 of amplifier 22 are selected for controllin~ gain.
~s sho~7n, when multiplexer~l5 is controlled by decoder 5 to
supply constant current to reference resistor REF 1 r decoder
6 also selects multiplexer 21 to connect terminal H to its
output pin 3 and thus to the positive input Oe amplifier 22.
Likewise, decoder 6 selects multiplexer 2a to connect the
other side of the reference resistor REF 1 at termin~l J to
its output. pin 3 and thus to the negative input of amplifier
22. In effect, therefore, the resistanc~ of the resistor
connected ~cross amplifier 22 by multipl~exers 20 and 21 i5
then supplied to output termina]. L of Figure 2C. Multi-
71:~36
plexers 15, 20 and 21 may each be supplied under the standardpart number 4051.
The output terminal L shown in Figure 2C is connected
to the input terminal L shown in Figure 2D. Figure 2D shows
voltage to period section 30 and is comprised of an integrator
portion 31 and pulse generator portion 32. In Figure 2D, series
connected resistors 33 and 34 are connected from a negative
source to ground. The junction of these resistors is connected
through resistor 35 to the inverting input of amplifier 36 the
non-inverting input of which is connected through resistor 37
to ground. Feedback capacitor 38 is connected from the output
of amplifier 36 back to its inverting input. The output of
amplifier 36 is also connected to the input I of analog switch
39 which has its output O connected back to the inverting input
of amplifier 36. The output from amplifier 36 is also connected
through resistor 40 to the non-inverting input of amplifier 41
which has its inverting input connected to terminal L through
resistor 42. The output from amplifier 41 is connected back
to its non-inverting input through resistor 43, to a positive
source through resistor 44, and to the control terminals C of
analog switches 45, 46 and 47. The input terminal I of analog
switch 45 is connected to ground and the output terminal O is
connected through inverter 48 to one input of NAND gate 49 the
:
other input of which is connected over terminal C to an output
of coun er 2. The output of NAND gate 49 is connected to out-
put terminal TP57. The input terminal I of analog swltch 46 is
connected to a positive source and the;output terminal O is
connected to ground through resistor 51 and is also connected
to control terminal C of anaIog switch 39. Output terminal O
3Q of analog switch 47 is connected to the inverting input of amp-
lifier 41 and the
,1
3 ~
input terminal is conn~cted to yround throucJh resis~or 52~
The norninal invers~ slope of in~egr~tor section 31 is deter-
mined by the voltag~ source connected thereto, resistors 33,
34 and 35, an~ capacitor 38.
With circuit 30 of Figure 2D at rest, the output
from amplifier 22 ~t terminal ~ is low so that the inverting
input of comparator 41 is low. Because of the resistance
43, the output of the comparator ~1 is high which closes
switch 46 and, thus, switch 39, to màintain capacitor 38
discharged. When multipleY.er 50 is selected by the
Datachain input terminal TP62, an output will appear at the
output of amplifier 22 and thus to the inverting input to
comparator ~1 driving its output lo~l opening switches 46 and
39 to allow capacitor 38 to begin charging. The input to
the inverting input of amplifier 41 is at a le~el dependent
upon the value of the resistance connécted through multi-
ple~ers 20 and 21 to the inputs of amplifier 22~ Integrator
31 ~7ill begin ramping up and will continue until its output
voltage which is supplied to the non-inverting input of
comparator 41 reaches the voltage at the inverting input at
which time the output from comparator ~1 pulses high. When
this occurs, analog switches 39, 45, 46 and ~7 are closed.
When s~Jitches 39 and 46 are closed on, capacitor 38 is
discharged. Switch 47 is turned on to reduce th~e input
voltage to the inverting input of comparator 41 ~o approxi-
mately 10% of ;ts initial value to make the discharge cycle
for capacitor 38 more reliable and thus reduce the poss;bil-
ity of false triggering of the comparator. Switch 45 is
also turned on to supply an output pulse at terminal TP57.
When capacitor 38 is sufficiently dischar~ed to drive the
output ~rom comparator 41 low, the analog switches are
turned off an~l capacitor 38 is allowFd to charge- The
3 6
timing of counter 2 is such as ~o ~llow c~ sufEicien. nu~ber
of pulses to be supplied at ter~in~l TP57 for use b~-
digitizer 200. Digitizer 200 measuees the period bet~een
the pulses supplied at terminal TP57 and provides a binary
count tO processor 300.
In addition to the above functions, the
multiplexer S0 and resistance-to-period circuit 100 ha~e
strapping optlons for indicatiny the type of point OL
circuits 50 and lnO, the temperature range of the sensors
TRl-TR4 and sensor correction factors. Thus, the circuit in
Figure 2B includes diode set ~n, comprised of 6 dio~_s,
which may be used to inform processor 300 over ter~in~ls
TP48, TP50-TP53, and TP55 the type of point repres~nted by
the circuits 50 and 100 plus whether or not circuits 50 and
I oa are busy. Specifically, when flip-flop 4 in Fi~ure 2A
switches to enable counter 2, it also provides an inpuL to
N.~ND gate 61 shown in Figure 2B ~7hich ~lso receives an input
from the C output terminal of counter 2. When gated, ~.~ND
gate ol allows processor 300 to read terminals TP~,
TP50-TP53 and TP55. B~ disconnecting the middle t~o diodes
of diode set 60, the information available at these
terminals will indicate that circaits 50 and 100 are
multiplexee and resistance-to-period circuits~ In aidition,
terminals K, L and M are connected from the output o count- :
er 2 to the input of decoder 62 which~provide~s its outputs
to dip switches 63, 64 and 65 and in addition to a pair of
diodes 66. The dip switches 63, 64 and 65 connec, one of
their inputs to a corresponding output, as shown for example
with respect to dip switch 63. Connected between the odd
numbered outputs of switch 63 and output terminal ~P~6 are
four reversely connected diodes and connected het~e~ the
even numbered outputs o~ switch 63 and terminal TP~ ~re
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~ 1 J l ~ 3 6
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reversely connected diodes. The s~itches of s~litch 63 may
be operated to inclicate the ternper~ture r~n~e o:~ each of the
four sensors connec~ed to circuit 50. Four ran~es may be
selected by usin~ switch 63. Thus, when one sensor is
connected at its inpu~ to constant current multiplexer 15
and at its output to signal multiplexers 20 and 21, decoder
62 at the same time connects th~ corresponding switches to
terminals TP46 and TP45 which are read by the processor 30Q
to determine the temperature range of the selec-t~d tempera-
ture responsive resistor.
In addition, switches 64 and 65 may be operated to
provide correction codes to the processor 300. For example,
the resistors TRl-TR4 mav not pro~ide the same outp~t ~or
the same sensed tempera~ure. S~Jitches 64 and 65 are
operated to correct this anamoly and to inform the computer
300 of the correction factor to be applied to each of the
sensors for which it receives an input. Thus, pins 12 and
16 of switches 6~ and 65 are connected throu~h reversely
connected diodes to terminal TP53. Pins 11 and 15 o
-switches 64 and 65 are connected through reve~sely connected
diodes to terminal TP52. Pins 10 and 14 of switches 6~ and
65 are connected through reversely connected diodes to ter-
minal TP51. And, Pins 9 and 13 o switches 64 and ~S are
connected to terminal TP50 throu~h reversely connected
diodes. At the same time that processor 300 reads the tem-
perature range over terminals TP~,5 and TP~6, it reads the
correction factor over terminals TP50-TP53 for the particu-
lar sensor for which it is now making a readlng.
Finally, terminal TP49 can be read to indicate the type of
resistor which is bein~ read. There are as indicated in
~igure 1 two types of resistors. The first type is the ref-
erence resistor which i~ used to calibrate the analog-to-
.
--1 0--
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digital c~nverter and the second type is the tempera~uresensing resistor used to provicle in~orm~tion to prooessor
30û. Decoder 62 may be supplied under the standard part
number LS138.
The way in which processor 300 calibrates the
analog-to-digital conversion of analog-to-digital converter,
and particularly the resistance-to~period conv~rter 100
therein, is best explained in connection with Figure 4. ~s
counter 2 begins counting, it first connects constant cur-
rent source 7 to reference resistor RE~ 1 and connects ref-
erence resistor RE~ 1 to the input of signal multiplexers 20
and 21 and processor 3Q0 reads the digital value at the out-
put of digitizer 200. Thus, proce5sor 300 knows the res.is-
tance Rl of REF 1 and can determine the digital signal Pl
from reading the output of digitiæer 200. As counter 2
continues to.~ount, reference resistor REF 2 is next
connected to the outpui of multiplexer 15 and the inputs of.
multiplexers 20 and 21. ~gain, processor 300 knows the
resistance value for this reference resistor and can deter-
mine the digital signal P2 at this resistance value by read-
in~ the output of digitizer 200. The curve l~beled Theoret-
ical with its digital points Pl' and P2' represent the nomi-
nal tr~nsfer function for the analog-to-digital converter.
However, a5 pointed out above, aging, changes in ambient
temperature, and~manufacturing tolerances will distort the
The~retical transfer function to the Actual transfer
function. Only résistance-to-period converter 100 is sub- ~
ject to distortion since di~itlzer 200 is strictly a digital ~ `
circuit and its performance~should not be subject to distor- -
tion. Once the points Rl, Pl,~ R2 and P2 are known, ~he com-
puter can next determine the slope of the actua1 transfer
function by the following:
-~ K = (R2 - Rl)/(P2 - Pl) 1 171136
~here Pl is the cli~it~l signc~ for the resistance value Rl
and P2 is the digital signal for the resistance value R2.
Next, the offset C can be calculated by the equa-
tion
C = R2 - KP2 2.
Now, processor 300 is ready to calculate the
resistance values R that it reads from temperature respon-
sive resistors TRl-TR4 by the equation
R = KP -~ C 3.
here C and K are determined from e~uations 1 and 2, and P
is the digital signal read for the corresponding temperature
responsive resis~or by the analog-~o-digital converter.
Knowing the val~e of the resistance, the temperature can be
determined by the equation
T = 256~bR) ~ a.
where Gb represents a constant pl~s a calibration factor as
determined by switches 64 and ÇS of~Figure 2B and R ;s
determined by equation 3. The program for accomplishing
these c~lcul~ations is provided in the Appendix attached
hereto.
It may be possible to modify these calculations so
that no offset has to be determined. For example~ if the
transfer Eunction can al~ays be made to pass through the
origin of the axes of Figure 4, one point of the transfer
function will alw~ys be known by processor 300. This~can he
accomplished b~ applying as a first refe~rence point a ground
input to the analog-to-digital converter and~forcing its
output to 0 by suitably adjusting one of the elements of the
circuit. Thus, the digital value Pl for this first point
need not actually by read by the processor since it is
presumed to be 0. Specifically, when R is 0, P is 0. Then
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a reference source is applied to ~he analog-to-digit~l con-
verter and i~s digital output read. T'nis reerence source
with its digital output represents the second point o~ the
transfer function. The processor 3GO can then determine the
transfer function for the analog-to-digital converter. It
is important to note, ho~7ever, that the determin~tion of the
transfer function in either case requires ~wo points.
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