Note: Descriptions are shown in the official language in which they were submitted.
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BACK~ROUND OF THE INV~NTIOI`~
Field of the Invention:
This invention generally relates in general to a pulse
detecting circuit, and more particularly to a diyitallv designed
vertical synchronizing separator circuit, and associated framing
detection circuit.
Description o _ e Prior Art:
Hitherto, four servo systems, including a drum phase
servo system, a drum speed servo system, a capstan phase servo
system and a capstan speed servo system have been provided in
helical scan type VT~ (Video Tape Recorders) using rotary magnetic
heads. Generally, an analogue control method is employed for
these servo systems. Accordingly, it is difficult to form them
as IC (Integrated Circuits). There are some problems due to
aging and the temperature characteristics. Therefore, the
development of digital control servo circuits is desirable. Some
digital servo circuits have already been designed.
In the drum phase servo system and the capstan phase
servo system, the vertical synchronizing signal separated
from the video signals is used as the reference signal in the
recording operation. In the drum phase servo control, the
vertical synchronizing signal and the pulse obtained from the
pulse generator mounted on the rotary drum are phase com~ared with
each other to produce an error voltage. In the capstan phase
servo control, the vertical synchronizinq signal and the pulse
obtained from the frequency generator mounted on the capstan are
phase-compared with each other to produce an error voltage.
In the assemble edit operation, the phase servo control of the
rotary drum is performed with reference to the vertical synchronizing
signal of the external video signals until the magnetic tape
has run to the editing point.
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In the digital servo circuit, various clock pulses
and reference signals are generated by the reference oscillator,
which are supplied to the respective circuits constituting the
servo systems. The reference oscillator is driven with the
subcarrier frequency, and in the recording operation, it is
reset with the vertical synchronizing signal.
Usually, the integrating type sync separator is used
in the conventional vertical synchronizing separating circuit for
separating the vertical synchronizing signal from the video
signals. Capacitors are included in the integrating type sync
separator which make it difficult to form the vertical synchronizing
circuit in ICs. Excessive time is required to adjust the time
constant circuit including the capacitor. Some vertical
synchronizing separating circuits have been digitally designed.
However, the noise in such circuits is excessive in these digital
vertical synchronizing separating circuit. Misoperation can occur
due to noise. The influence of noise can be somewhat eliminated
by the use of a Schmidt circuit which is arranged at the input
side of the vertical synchronizing separating circuit. ~lowever,
it is difficult to eliminate.the influence of wide band nosie.
In the framing servo system, it should be discriminated
whether the separated vertical synchronizing signal belongs to
the odd or the even field. For example, in the assemble edit
mode, it should be discriminated whether the video fields at the
editing point are odd or even. In such a case, a framing signal
with a level which is inverted at every field, is used for
the discrimination. The framing signal functions to reset the
above-described reference oscillator in the digital servo circuit,
for example, during the assemble edit operation.
In the conventional framing circuit for obtaining
framing signal, for example, the framing pulse genera~ed every
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frames and the pulse inverted by the vertical synchronizing
signal are phase c~mpared with each other. t~hen the number
of times which successively do not coincide with each other
reaches the predetermined number N, the above-described pulse
is inverted. ~onostable multivibrators including capacitor
and resistor are used in the framing circuit. Accordingly,
it is difficult to form the framing circuit in IC. It takes too
much time to adjust the CR elements. Misoperation often occurs
due to noise.
SU~RY OF TH~, I~ENTIO~
An object of this invention is to ~rovide a digital
signal detecting circuit.
Another object of this invention is to provide a novel
signal detecting circuit by which synchronizing timing can be
obtained from a composite synchronizing signal.
A further object of this invention is to provide a
novel sianal detecting circuit by which vertical synchronizing
timing and framing pulse can be obtained from the composite
synchronizing signal reproduced by VTR (Video ~ape Recorder).
A noise-free synchronizing-detecting circuit and a
framing pulse generator are formed by the signal detecting
circuit of this invention.
In accordance with the foregoing objects, there is
provided:
A signal detecting circuit for extracting
a vertical sync timing out of an incoming composite
synchronizing signal comprising:
A) first counter means for counting a reference clock
pulse having a fixed frequency higher than
horizontal sync frequency,
B) logic gate means coupled to a reset means of
said counter for cyclically resetting said
counter means except a vertical sync duration of
said incoming composite ~ynchronizing signal,
said logic gate means being supplied with
said composite synchronizing signal and contents
of said first counter`means, and
C) means for generating a vertical sync timing
during said vertical sync duration of the
composite synchronizing signal out of said first
counter means.
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Various other objects, advantages and features of the
present invention will become readily apparent from the ensuing
detailed descri?tion, and the novel features will be particularly
pointed out in the appended claims.
BRIEF DESCRIPTION OF THE DRAl~INGS
Fig. 1 is a circuit diagram of a digital servo circuit
for VTR according to one embodiment of this invention;
Fig. 2 is a circuit diagram of a motor dri~e circuit
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according to the embodiment of this invention;
Fig. 3 is a bottom view of a rotary drum in the
embodiment of Fig. 2;
Fig. 4 is a circuit diagram of details of important
parts in the embodiment of Fig, 1;
Fig. 5 to Fig. 7 are timing charts of signals at the
respective parts of the circuit diagram of Fig. g.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
An outline of a digital servo circuit according to
one embodiment of this invention will be described with reference
to Fig. 1 to Fig. 3. This servo circuit is applicable to all
kinds of helical scan type video tape recorders. However,
there will be described the case where the servo circuit is
applied to a helical scan type video tape recorder of the rotary
two-head 180Q wrapping type.
Fig. 1 shows a circuit to obtain various error signals
for controlling the rotary phases of the rotary drum and capstan,
and their rotational speeds. Fig. 2 shows motor drive circuits
which are supplied with the error signals from the circuit of
Fig. 1. In the servo circuit of this embodiment, a PG (pulse
generator) and an FG (frequency generator) are provided in a
rotary drum and a capstan so as to detect the rotary phases of
the rotary drum and capstan and the rotational speeds thereof.
In the two-head helical type VTR, the A-head and B-head
are mounted on a rotary drum 1, as shown in Fig. 2. Six
permanent magnets 2 are mounted on the lol~er surface of the
rotary drum 1 at angularly regular intervals (60). One permanent
magnet 3 is arranged on drum 3 within the rotary path of the six
permanent magnets 2, Two pick-up heads 4 and 5 are arranged
angularly distant by 30 to 40~ from each other adjacent to the
rotary path of the permanent magnets 2. Another pick-up head 6
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is arranged adjacent to the rotary path of the one permanent
magnet 3. The above-described PG is constituted by the permanent
magnets 2 and 3, and pick-up heads 4 and 5. When the rotary
drum 1 rotates, pulse signals SPGA and SPGB are generated from
the pick-up heads 4 and 5, respectively. Normally, the frequency
of the pulse signals SPGA and SPGB is 180 Hz. The spacing of the
pulses SPGA and SPGB represents the rotational speed of the
rotary drum 1. A pulse signal PPG is generated from the pick-head
6. Normally, the frequency of the pulse signal PPG is 30 Hz.
The pulse signal PPG represents the rotary phase of the rotary drum
1.
A magnetic wheel g is fixed to the shfat of a capstan
8 which drives the magnetic tape 7. The circumferential surface
of the magnetic wheel 9 is magnetized with numerous N-poles and
S-poles. Pick-up heads 10 and 11 æe arranged adjacent to the
circumferential surface of the magnetic wheel 9. The above-
described FG is constituted by the magnetic wheel 9 and pick-up
heads 10 and 11. Pulse signals FGA and FGB are generated from
the pick-up heads 10 and 11, respectively. Normally, the frequency
of the pulse signals FGA and-FGB is, for example, 450 Hz. The
spacing of the pulse signals FGA and FGB represents the rotational
speed of the capstan 8. A CTL signal recorded on a control
track of the magnetic tape 7 is detected by a CTL head 12. The
CTL signal is used for the phase servo of the capstan 8 in the
reproducing mode.
The circuit of Fig. 1 is divided into a digital part
indicated by dotted lines and an analogue part, and it is formed
on one LSI chip.
The above-described pulse signals SPGA, SPGB, FGA,
FGB and CTL signal from the pick-up heads 4, 5, 10, 11 and 12
are supplied to the circuit o~ Fig. 1. Clock pulses are counted
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by counters for measuring the spacings of these signals. Output
duty ratios of PWM (Pulse Width Modulation) circuits are controlled
with the counted value of the counters. The outputs of the PWM
circuits are led out as the error voltage from the LSI chip. A
reference oscillator 15 is arranged for generating the above-
described pulses. Clock pulses of various frequencies are
generated by the reference oscillator 15, and they are supplied to
the above-described counters. In addition to the above-described
clock pulses, a reference pulse is generated by the reference
oscillator 15. In the recording mode or external synchronization
reproduction mode, the reference oscillator 15 is driven in
synchronization with a sub-carrier signal SC obtained from a
color burst signal of video signals. In the reproducing mode
without external synchronization, the reference oscillator 15
self-excited and it oscillates.
In a drum speed servo system of the circuit of
Fig. 1, the pulse signal SPGA is supplied through a variable
delay circuit 17 to a flip-flop 16 to set the flip-flop. The
pulse signal SPGB is supplied to the flip-flop 16 to reset it.
The width of the output pulse of the flip-flop 16 corresponds
to the speed of the rotary drum 1. A DS (Drum Speed) counter 18
is actuated by the output pulse of the flip-flop 16. The clock
pulses are counted by the DS counter 18. The counted value of the
DS counter 18 is supplied to a PWM circuit 19 to control the output
duty ratio of the latter. An error voltage DS Pl~ for the drum
phase servo is obtained through a buffer amplifier 20 from the
PWM circuit 19. A speed adjusting voltage Ecl is supplied to
the variable delay circuit 17 to adjust the delay time for the
pulse signal SPGA.
In a drum phase servo system of the circuit of ~ig. 1,
the pulse signal PPG is supplied through a variable delay
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circuit 22 to a fl-ip-flop 21 to setthe latter. A reference
signal SPl of 30 Hz from the reference oscillator 15 is supplled
to the flip-flop 21 to reset it. Accordingly, the width of
the output pulse of the flip-flop 21 represents the rotary phase
of the rotary drum 1. A DP (Drum Phase) counter 23 is
actuated by the output pulse of the flip-flop 21. The clock pulses
are counted by the DP counter 23. The counted value of the DP
counter 23 is supplied to a P~l circuit 24 to control the output
duty ratio of circuit 2a. An error voltage DP- pT~ for controlling
the drum phase is obtained through a contact a of a switch circuit
25 and a buffer a~plifier 20 from the P~ circuit 2a. A phase
adjusting voltage Ec2 is supplied to the variable delay
circuit 22 to adjust the phase of the pulse signal PPG. In
special reproducing modes such as slow motion mode, still mode
and quick search mode, the switching circuit 25 is changed over
to engage a contact _. A change-over signal SS is supplied
through a Schmidt circuit 26 to the switching circuit 25 to
change over circuit 25 to the contact _. In the special
reproducing mode, a horizontal synchronizing signal PB-HD of
reproduced vidèo signals is supplied through a Sch~idt circuit
26 to an H. AFC PWM circuit 27, and a part of the output of
the PWM circuit 24 is supplied thereto, so that the drum speed
is controlled and the horizontal synchronizing signal PB-HD is
reproduced at regular intervals. Thus, the error voltage DP P1~1
is obtained from the H AFC PWM circuit 27. In Fig. 1, all of
the Schmidt circuits 26 are provided so as to eliminate noise.
The pulse signal PPG is used also for forming a switching
signal SW for the heads A and B. For that purpose, the pulse
signals SPGA and PPG are supplied to a PG sampling circuit 28.
A nearly central position of the spacing of the pulse signal
PPG is detected by the PG sampling circuit 28. The detecting
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output of the PG sampling circuit 28 is supplied through a
variable delay circuit 29 which is adjusted by an adjusting voltage
EC3, to a switching pulse generator 30, The pulse signal PPG
is further supplied to the switching pulse generator 30. The
predetermined switching signal SW is formed by SW generator 30
on the basis of the pulse signal PPG and the detected central
position, and it is supplied also to a vertical synchronizing
signal generator 49. A vertical blanking pulse signal V~LK for
controlling a signal system in the normal mode and a pseudo
vertical synchronizing signal VD' for the special mode are
obtained from the vertical synchronizing signal generator 49.
In a capstan speed servo system of the circuit of
Fig. 1, the pulse signal FGA is supplied through the Schmidt circuit
26 to a flip-flop 31 to set it. The pulse signal FGB is supplied
through the Schmidt circuit 26 to the flip-flop 31 to reset it.
Accordingly, the width of the output pulse of the flip-flop 31
corresponds to the speed of the capstan 8. A CS (Capstan Speed)
counter 32 is actuated by the output pulse of the flip-flop 31.
The clock pulse is counted by the CS counter 32. The counted
output of the CS counter 32 is supplied to a PWM circuit 33 to
control the output duty ratio. An error signal CS-PWM for
controlling the capstan speed is obtained through the buffer
amplifier 20 from the PWM circuit 33. The frequency of the clock
pulses supplied to the CS counter 32 is changed over into one
of two frequencies by a switching circuit 34 in accordance with
the set speed of the capstan ~ which changes the recording/
reproducing time (for example, one-hour recording/reproducing or
two-hour recording/reproducing). A speed setting signal SH is
supplied through the Schmidt circuit 26 and a speed setting
circuit 35 to the switching circuit 34 to change-over the
frequency of the clock pulse supplied to the CS counter 32. The
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speed setting circuit 35 includes flip-flops.
In a capstan phase servo system of the circuit of
Fig. 1, the pulse signal PGB is supplied through the Schmidt
circuit 26 to a fre~uency-dividing counter 36, and the frequency
of the pulse signal FGB is divided to about 30 Hz, The divided
pulse signal from the counter 36 is supplied through a contact
REC.ASS of a switching circuit 37 to a flip-flop 38 to reset it
in the recording mode. Further, a signal SP2 of 30 Hz obtained
from the reference generator 15 is supplied through a contact
REC of the switching circuit 37 to the flip-flop 38 to set it.
The signal SP2 is further supplied as a signal REC-CTL through a
buffer amplifier to the control track of the tape where it is
recorded thereon. The width of the output pulse of the flip-flop
38 represents the phase of the capstan 3. A CP (Capstan phase)
counter 39 is actuated by the output pulse of the flip-flop 38.
The clock pulses are counted by the CP counter 39. The counted
value of the counter 39 is supplied to a P~ circuit 40 to
control the output duty ratio. An error voltage CP-PWM for
controlling the capstan phase is obtained through the buffer
amplifier 20 from the P~l circuit 40. In the reproducing mode,
the signal SP2 is supplied through a variable delay circuit 41
and a contact PB-ASS of the switching circuit 37 to the flip-flop
38 to set it. A signal PB-CTL reproduced from the tape is
supplied through a contact PB of the switching circuit 37 to the
flip-flop 38 to reset it. The output pulse of the flip-flop 38
is supplied to the CP counter 39 to actuate it. The counted
value of the CP counter 39 is supplied to the PWM circuit 40 to
control the output duty ratio. The error voltage CP-P~M for the
capstan phase control in the reproducing mode is obtained
through the buffer amplifier 20 from the PWM circuit 40.
An adjusting voltage Ec4 is supplied to the variable
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delay circuit 41 to adjust the servo reference position of the
signal SP2 from the reference oscillator 15. I~hen a recording
mode setting signal REC or an assemble edit mode settina
signal ASS to be described hereinafter is supplied through a
gate 42 to the switching circuit 37, it is changed over.
Further, the pulse signals F~,A and FGB are supplied
through the Schmidt circuits ~6 to a frequency multiplier 43.
The frequency o~ the pulse signals FGA and FGB is multiplied
there by four. The output of the frequency multiplier 43 is
supplied to a Pl~ circuit 44 and a capstan speed detecting
circuit 45. A s~gnal CS P~ for the special mode is obtained
as a capstan speed detecting signal from the P~ circuit 44.
A signal CS is obtained from the capstan speed detecting
circuit 45 which represents an amplification of the capstan speed.
In the assemble edit mode, the lower movable contact
to a contact PB from a contact REC-ASS from a contact REC-ASS in
the switching circuit 37, when an editing point has been located.
The frequency-dividing counter 36 is reset with the signal PB.CTL.
Thus, the CTL signals and video tracks are orderly combined
before and after the editing point of the tape, respectively.
When it is required that the output of the reference
oscillator 15 be synchronized with even and odd fields of
input video signals, the reference oscillator 15 is reset by
a frame pulse generated from a frame detecting circuit 47. A
composite synchronizing signal REC.SYNC of the input video
signals is supplied through the Schmidt circuit 26 to a vertical
synchronizing separating circuit 48. The frame detecting
circuit 47 which is actuated by an O~.OFF signal, generates
the frame pulse on the basis of a vertical synchronizing signal
VD from the vertical synchronizing separator 48.
The above described error voltages are supplied to
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respective circuits of Fig. 2. The signals DS.PWM and DP.PI~I
are supplied to integrating circuits 50 and 51, and converted into
DC voltages, respectively. They are added to each other in an
adder 52, The output of the adder 52 is supplied through a
motor drive amplifier 53 to a drum motor 54 to control its phase
and speed. The error signals CS PI~ and CP.PWM are supplied
to integrating circuits 55 and 56, and converted into DC voltages,
respectively. They are added to each other by an adder 57.
The output of the adder 57 is supplied through a contact a
of a switching circuit 58 and through a motor drive amplifier 59
to a capstan motor 60 to control its phase and speed.
In the special mode, the switching circuit 58 is
changed over to a contact b with a sianal SS. The error
voltage CS.P~ for the special mode is co~pared with a speed
~'esignation signal SCM in a control circuit 61. The compare~
output of the control circuit 61 is supplied throu~h an
integrating circuit 62, the switching circuit 58 and the motor
drive amplifier 59 to the capstan motor 60 to drive it
at the designated speed.
Next, examples of the vertical synchronizing signal
separating circuit 48 and frame detecting circuit 47 of the
present invention will be described with reference to Fig. 4.
In Fig. 4, the vertical synchronizing separating circuit
48 includes a Schmidt circuit 71, a flip-flop 72, a mod-32
counter 73, a mod-4 counter 74, AND circuits 75, 76, 77, inverters
78, 79, 80 and an OR circuit 81 connected as shown. An input
terminal 70 and a clock input terminal 82 are connected to the
~ertical synchronizing separating circuit 48. Signals a to i at
the respective points of the vertical synchr~nizing separating
circuit 48 are shown in Fig. 5A to Fig. 5J.
A composite synchronizing signal SYNC as shown in
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Fig. 5A is supplied to a line a from the input terminal 70.
A vertical synchronizing signal VD as shown in Fig. 5J is
obtained as the output of the mod-4 counter 74 from a line 1.
The composite synchronizing signal SYNC includes a horizontal
synchronizing signal HD, equalizinq pulses E~ and a vertical
synchronizing signal VDo. The vertical synchronizing signal VD
represents a predetermined position within the period of the
vertical synchronizing signal VDo. In this example, a window
signal for detecting the vertical synchronizing signal VDo and
noise is formed on the basis of the time when the composite
synchronizing signal SYNC becomes low level "0". It is detected
whether or not the composite synchronizing signal SYNC has
become higher "1", within the period of the window signal.
Next, operation of the vertical synchronizing
separating circuit 48 will be described with reference to Fig.
5A to Fig. 5J.
The composite synchronizing signal SYNC applied to
the line a is supplied through the Schmidt circuit 71 to the
AND circuit 76 and flip-flop 72. At time t1, the flip-flop 72
is set with the falling edge of the horizontal synchronizing
signal HD of the composite synchronizing signal SYNC. The Q
output of the flip-flop 72 becomes "1" (line b), and so the
AND circuit 77 is opened for the clock pulses applied to the
input terminal 82. The clock pulses are counted by the counter
73. They are supplied from, for example, the reference oscillator
15 of Fig. 1. For example, the frequency of the clock pulses is
lMHz.
The output c of the third bit of the counter 73 and
the output d of the fourth bit of the counter 73 are applied
to the inverters 79 and 80, respectively, and they are inverted
thereby. The inverted outputs are supplied to the AND circuit
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75. The output f of the AN~ circuit 75 is supplied through the
OR circuit 81 to the inverter 80, and it is inverted thereby.
The inverted output g is the window signal, and it is supp~ied
to the AND circuit 76.
However, when there is no noise in the composite
synchronizing signal SYNC until the following horizontal
synchronizing signal H~ or the equalizing pulse ~Q, or when the
composite synchronizing signal SYNC is maintained at the high
level "1" until the following horizontal synchronizing signal
HD or the equalizing pulse EQ, the window signal g is not
opened, and is maintained at the low level "0".
When the horizontal synchronizing signal HD of the
composite synchronizing signal SYI~C is supplied to the
Schmidt circuit 71 at time tl, the counter 73 counts the clock
pulses, and generates the output c at the third bit. The outpu
of the inverter 79 falls down, and the output f of the AND
circuit 75 falls down, and the output g of the inverter 80 rises up.
The output g of the inverter 80 and the level "1" of the composite
synchronizing signal SYNC following the horizontal synchronizing
signal HD are supplied to the AN3 circuit 76. The output h of
the A~D circuit 76 rises up. The flip-flop 72 is reset with
the output _ of the AND circuit 76. The Q output b of the flip-flop
72 becomes "0". Accordingly, the AND circuit 77 is closed for
the clock pulses supplied to the input terminal 82. As a result,
the sindow signal g is not opened, and it is maintained at the
low level "0" till the following horizontal synchronizing
signal HD or the equalizing pulse EQ. The flip-flop 72 is set
and reset whenever the horizontal synchronizing signal HD or
the equalizing pulse EQ is supplied to the input terminal 70.
At time t2~ the ~ertical synchronizing signal VDo arrives,
and the composite synchronizing signal SYNC becomes "0", the
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flip-flop 72 is set. The counter 73 starts to count the clock
pulses. Since the composite synchronizing signal SY~C is
maintained at the low level "O", the AND circuit 76 is not opened,
and the counter 73 continues to count the clock pulses.
The outputs of the counter 73 becomes "1" in order at the third
bit, fourth bit and fifth bit. As a result, the window signal g
is opened as shown in Fig. 5H, with a window period of the level "1".
The equalizing pulse PQ' of the vertical synchronizing signal VDo
is not included in the window period of the window signal g.
~he flip-flop 72 is not reset with the equalizing ~ulse EQ'
which is a positive pulse. The trailing edges of the window signals
g ~re counted by the mod-4 counter 74. When four of them
have been counted by the counter 74, the vertical synchronizing
signal W is obtained on the line i from the counter 74. Due
to the fact tha- the composite synchronizing sisnal SYNC is
at the low level "O" during the four window periods of the
window signals g, a period including the four window periods
is considered to be the period of the vertical synchronizing
signal VDo fro~ which the vertical synchronizing signal VD
is taken. After the end of the period of the vertical synchronizing
signal VDo, the same operation is repeated as during the time
tl to t2-
When the negative noise N as shown by the dotted linein Fig. 5A occurs in the composite synchronizing signal SYNC
during time tl or t2, the same operation is effected as
for the horizontal synchronizing signal HD or the equalizing pulse
EQ. The flip-flop 72 is set and reset in a very short time.
The window signal g is not opened. When negative noise N occurs
for a considerable time, the window signal g is opened
correspondingly. However, if the considerable time is shorter
than the four win~ow periods of the window signals g, it is not
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considered to be the period of the vertical synchroni~ing signal
VDo.
I~hen positive noise occurs during the period of the
vertical synchronizing signal VDo, there is concern that the
vertical synchronizing signal VD will not be taken out. To
overcol~e this concern, a self-excited type vertical synchronizing
signal oscillator may be connected to the mod-4 counter 74.
In the vertical synchronizing separating circuit
of this invention, the window signal is formed on the basis
of the rising edge or falling edge of the composite synchronizing
signal (for example, during the times tl and t2), and it has
the predetermined window period during which it is maintained
at a predetermined level (for example, level "1"). The level
change of the composite synchronizing signal is detected in
at least one of the window periods of the window signals. When
the level change is not detected, an output (for examDle,
vertical synchronizing signal VD) is obtained.
Accordingly, the vertical synchronizing separating
circuit of this invention may be constituted by an entirely
digital circuit without capacitors, as shown in Fig. 4, and so
it can be formed in Integration Circuit technique. Particularly,
it is effective against wide noise, and is secure and accurate in
operation.
Next, there will be described the example of the
frame detecting circuit 47 with reference to Fig. 4.
The framing circuit 47 consists of a framing pulse
for~ing circuit 90 and a noise inhibition circuit 91. The
framing pulse forming circuit 90 includes a differential
circuit 94 constituted by inverters 91, 92 and an exclusive
logic sum circuit 93, a flip-flop 95, an AND circuit 96, a
counter 97, a decoder 98, a counter 99, an AND circuit 100,
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and another differential circuit 104 constituted by inverters
101, 102 and an exclusive logic sum circuit 103 connected as
shown. Clock pulses of, for example, lMHz are supplied to the
counters 97 and 99 through an input terminal 105, for example,
from the reference oscillator 15 of Fig. 1~ The noise inhibition
circuit 91 includes a flip-flop 106, AND circuits 107, 108,
a counter 109, a decoder 110, an OR circuit lll and an output
terminal 112.
Next, there will be described operation of the framing
pulse forming circuit 90 with reference to Fig. 6.
It is assumed that the composite synchronizing signal
SYNC of the odd field is supplied to the input terminal 70.
As shown in Fig. 6, the composite synchronizing signal SYNC
includes a horizontal synchronizing signal HD, a vertical
synchronizing signal VDo and equalizing pulses EQ, EQ'. As above
described, the composite synchronizing signal SYNC is supplied
to the vertical synchronizing separating circuit 48 to remove
the vertical synchronizing signalVD which represents the
predetermined position within the period of the vertical synchronizing
signal VDo.
Further, the composite synchronizing signal SYNC is
supplied to the differential circuit 9~ which differentiates it.
The differential pulse as shown in Fig. 6 is supplied to the
AND circuit 96 and the flip-flop 95. The latter is reset with
the trailing edge of the differential pulse. I~hen the differential
pulse rises, the Ql output of the flip-flop 95 is at high level "l".
The differential pulse passes through the AND circuit 96 to
the counter 97 to reset it. Then, the Ql output of the flip-flop
95 becomes low with the trailing edge of the differential pulse.
The counter 97 starts to count the clock pulses with the reset.
The counted value of the counter 97 is decoded by the decoder 98.
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The decoder 98 ~enerates an out~ut to set the fli~-flop 95 at the
time when the counter 97 has counted the number of the clock
pulses corresponding to the period of ~H ~H: Horizontal scanning
period). The ~1 output of the flip-flop 95 becomes high "1".
As the result, the counter 97 is reset on every rising edge of
the horizontal synchronizing signal of the composite synchronizing
signal SYNC. Such operation is repeated until time tl. The
decoder 98 is designed so as to generate another output at the
time when the counter 97 has counted the number of the clock
pulses corresponding to the period of 6H . However, the other
output corresponding to ~II is not generated until time tl.
The period of the vertical synchronizing signal VDo occurs
in the time of lH after the counter 97 is reset with the rising
edge of the composite synchronizing signal SYNC at the time
tl. Accordingly, the counter 97 is not reset for the time of
about 1.5H e~tending from the time tl to the rising edge of
the first equalizing signal EQ' in the vertical synchronizing
signal VDo. As a result, the decoder 98 generates the other
output after the time of 6H from the time tl. Thus output
is not obtained in the composite synchronizing signal of the odd
field. In the odd field, the horizontal synchronizing signal
HD of the composite synchronizing signal SYNC is shifted by the
time of 1 H, as sho~n by the dotted line in Fig. 6, from the
horizontal synchronizing signal HD of the composite synchronizing
signal SYNC of the even field. Accordingly, the reset time of
the counter 97 and the time corresponding to the time tl as
shown in Fig. 6 are shifted by the time of 1 H, relative to the
reset ti~e and time tl of the even field. ~s the result, the
counter 97 is reset at the intervals of lH also in the period of the
vertical synchronizing signal VDo. However, the output for
6 H is obtained from the dec~der 98 with the last equalizing pulse
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EQ' both in the odd field and in the even field.
The counter 99 is reset with the first output of
5H from the decoder 99, which is a frequency-dividing counter
for delay, and its output is maintained at high level "1" until
it counts a predetermined number of the cloc]~ pulses from the
reset, as shown in Fig, 6. The output of the counter g9 and
the vertical synchronizing signal VD from the vertical
synchronizing separating circuit 4~ are supplied to the AND
circuit 100. The output of the AND circuit 100 is differentiated
by the differential circuit 104 to obtain a framing pulse FP.
~ The framing pulse FP is normally obtained in the
even field every frame. ~owever, when noise occurs in the
composite synchronizing signal SYMC, or when one or more pulses
of the horizontal synchronizing signal HD and equalizing pulses
EQ are lost in the composite synchronizing signal SYNC, there
is concern that the framing pulse FP will be generated
at an erroneous position or in the odd field, or that it will not
be generated. In order to avoid these problems, the framing
pulse FP from the framing pulse forming circuit 90 is supplied
to the noise inhibition circuit 91 to eliminate the influence
of the noise. Next, there will be described operation of the
noise inhibition circuit 91 with reference to Fig. 7.
The flip-flop 106 is triggered with the trailing
edge of the vertical synchronizing signal VD to generate Q2
output as a framing signal. The frequency of the framing
signal is half of that of the vertical synchronizing signal VD,
and the framing signal has a predetermined phase in the
predetermined field. In Fig. 7, right framing pulses FP
obtained in the even field are indicated by o, and erroneous
framing pulses FP generated at erroneous positions are indicated
by x. Framing pulses FP indicated by ~ represent ones obtained
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~ ~7~3~
in the case when video signals of even fields are successively
supplied to the VTR, f~r example, at the connection point in the
assemble edit operation.
The Q2 output of the flip-flop 106 triggered with the
trailing edge of the vertical synchronizing signal VD, and
the framing pulse FD are supplied to the AND circuit 107,
and the Q2 output of the flip-flop 106, and the frami~g pulse FP
are supplied to the AND circuit 108. The output of the AN~
circuit 108 is supplied through the OR circuit 111 to the
flip-flop 106 and the counter 109 to reset them. When the right
framing pulses FP are su~plied to the AND circuits 107 and 108,
the Q2 output of the flip-flop 106 is at low level "~", as
shown in Fig. 7. ~ccordingly, so long as the right framing
puises FP indicated by o are supplied to the AND circuits
107 and 108, the flip-flop 106 generates the framing signal of
half the frequency of the vertical synchronizing signal VD
regardless of the reset signals. The framing signal is taken out
through a switching circuit 83 from an output terminal. When
the framing pulse FP indicated by x is su2plied to the AND circuits
107 and 108, the output of the AND circult 107 is supplied to the
clock terminal of the counter 109 and counted thereby. However,
the following framing pulse FP indicated by o and the Q2 output
of the flip-flop 106 are supplied to the AN~ circuit 108, and
the counter 109 is reset with the output of the AN~ circuit 108.
The frequency of the Q2 output of the flip-flop 106 is maintained
to be half of the frequenc~ of the vertical synchronizing
signal VD. When two of the erroneous framing pulses indicated by x
are successively supplied to the AND circuits 107 and 108, the
counter 109 counts "2", and then it is reset. The Q2 output
of the flip-flop 106 is n~t disturbed by the erroneous framing pulses
FP. When the framing pulses FP indicated by ~ are successively
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supplied to the AND circuit 107 and 108, the counter 109 counts
"3", and then it is reset with the output of the decoder 110.
Concurrently, the flip-flop 106 is reset to invert the Q2
output and Q2 output. It is considered that the framing pulses
FP indicated by ~ are not erroneous, and that the phase of
the frame is inverted. Correspondingly, the framing signal of
half the frequency of the vertical synchronizing signal VD
is obtained from the output terminal 112.
In the above-described framing detecting circuit,
the level of the composite synchronizing signal SYNC is detected
at the time of about 1 H to about 1~ (for example, ~H~ from the
leading edge or trailing edge of the composite synchronizing
signal, and the framing pulse is obtained at the time when
the above-described level is inverted.
Further, the output of the flip-flop triggered with
the vertical synchronizing signal and the framing pulse are
compared in phase with each other. The flip-flop is reset at
the time when, the number of times which the output of the flip-
flop and the framing pulse are not coincident in phase with each other,
has reached the predetermined number N.
Accordingly, the framing detecting circuit of this
invention can be constituted by a pure digital circuit without
capacitors. ~he above-described predetermined number N can be
determined such as "3" by the counter and the accuracy can be
improved.
I~hen the framing detection is not required, the output
of the vertical synchronizing separating circuit 48 is taken
from the switching circuit 83 which is changed over by a control signal
supplied to an input terminal 113, from the output terminal 112.
While this invention is illustrated with specific
embodiment, it will be recognized by those skilled in the art
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~ 17~13~
that modifications may be made therein without departing from
the true scope of the invention as defined bv the following
claims.
