Note: Descriptions are shown in the official language in which they were submitted.
--1--
FORCED LOAD S~ARING CIRC~IT FOR
INVERTER POWER SUPPLY
BACKGROUND OF THE INVENTION
This invention relakes generally tc the
field of power supply circuits, and more particularly
to a system for causing equal sharing of the load by
a plurali-ty o power supplies electrically connected
there-to.
I-t is known in the prior art that i~ is often
10 advantageous to provide a plurality OjC power supplies to-
drive a particular load rather than to design and
construct a single power supply Eor -that purpose. These
advantages come from several sources, such as beins
able to utilize readily available components rather
15 than requiring power components that may be unduly
expensive or unavailable in the present art, There is an
advantage in being able to design and construc-t s-tand-
ardized individual power supply units that can then
be selected and utilizèd in a number or driving a
load under consideration. Also, a margin of safety
can ~e designed into such a system ~y providing more
power supply units then would normally be required
in order to accommodate failures in individual supplies.
There are o course more and varied detailed advantages
25 in such multiple power supply systemsr but prior art
systems are not without problems.
It has been common in the prior art systems
--2--
that invol~e the use of ~ultiple po~er supplies to
drive a ~lven load, to operate the power supplies
in a current limit mode. This mode of operation
results in the indivldual power supplies bein~ operated
at their maximu~ power ou-tput capaci-ty, wit~ only one
power suppl~ making up the balance oE -the power required
~or the particular load. For example, if a particular
load had six power supplies coupled to it and the ou~put
capacity of four of -the power supplies operating at
maximum outpu-t is not quite sufficient to drive the
load, four of the power supplies would be operated at~
maximum capacity with the balance of the load supplied
by the fifth power supply. In such a con-figuration the'
sixth power supply would not be operative and would be
idle. In such a system, if the load were variable and
would increase be~ond the capaci-ty of the fifth power
supply when added to the four power supplies opera-ting
at maximum capacity, the sixth power supply would then
be brought into operation to supply the balance of the
load. Of course it is apparent that the system must
be designed such tha-t the maximum load that can be
encountered can be supplied ~y the number of power
supplies available.
It has been found that this type of multiple
power supply configuration results in unequal stress
on the power supplies since some of the power supplies
will be operating a-t maximum capacity at all times,
some of the power supplies will be operative at varying
capacities depending upon load requirements, and some
of the power supplies may be inoperative for lon~ periods
o~ time. This uneven stress operation tends -to result
in a hi~her supply failure rate for those power supplies
that are operated at maximum capacity for the greatest
length oE time. Further, sys-tems of tha-t type exhibit a
poor response that can ~e very disruptive to the load
when a power supply that is supplying curren-t to the
load fails.
~ e~
SUMMA~Y OF THE INVE~ION
With the foregoing background in mind, this invention
provides a syste~ to force a number of power supplies whose outputs
are connected to drive a common load, to share the load current
equally.
A plurality of power supplies have individual output
terminals coupled in common respectively to drive the associated
load. Each power supply has associated with it, circuitry that
senses the current level of the power supply and circuitry for
comparison to the average of current levels being supplied by all
powe~ supplies in the system~ When it is determined that a
particular power supply is supplying more than the average current
level, an error signal will be generated. m e error signal will be
utilized by control circuitry to alter the output level o the power
supply and thereby cause it to approach an operational level ~here
it will be providing a current level comparable to that of the
average of all Fower supplies in the system.
The power supply utilizes switchin~ transistors that
provide signals through a coupling transformer to a rectifier
network. The output of the rectifier network is filtered and
provided as a regulated DC output to the load. The output voltage
is sampled and provided as a voltage feedback for comparison
purposes. At the same time, a current signal from the inverter
power supply is sampled by a transformer-coupled current detector
and produces a signal proportional to the output current of the
power supply. me sensed current level is converted to a voltage
which is compared to the average feedback voltage of all power
supplies in the system. When it is determined that the sensed
current level, as indicated by the converted voltage level, exceeds
the average, control circuitry provides a control voltage level that
functions throu~h pulse-
.~
. I
wid-th-modulator circuitry to alter the operation of
the switching transistors to reduce the duty cycle,
and there~y reduce the current supplied by the power
supply to the load.
OBJECTS
A primary o~jec~, -then, of the lnven-tion is
to provide an improved power supply sys-tem wherein a
number of power supplies,whose outputs are connected
in common to drive a load,- are forced to share the
load current equally.
Yet another object of this ;nvention is to
provide a system Eor sensing the current level o-E each
power supply in a multiple power supply system, and
provide comparison to the average curren-t output of
each supply for providing control of the power supply
to cause reduction of the current output ~hen it is
sensed that the power supply is providing more than
the average current for all supplies coupled to the
common load.
Still a ~urther object of the invention is
- to provide circuitry for altering the duty cycle oE
an inverter power supply to reduce the output current
when it is detected that the power supply is providing
more than the average of the currents provided by all
power supplies coupled to the common load.
Yet another object of the invention is to
provide a system for providing control signals that will
control pulse-width-modulation circuitry for controlling
the duty cycle of an inverter power supply when it is
sensed that the current provided by the power supply
is greater than the average current provided by all
power supplies coupled to a common load in the system.
These and other more detailed and speci~ic
, ~
objects and objectives will become apparent from a consideration of
the following detail description of a preferred embodiment of the
invention together with the drawings.
~RIEF DESCRIPTION OF THE DRA~INGS
Figure 1 is a block diagram oE a system incorporatin~ a
plurality of power supplies couplecl for drivin~ a common load
together with control circuitry to force the power supplies to share
the load current equally;
Figure 2 is a block diagram of one power supply and its
associated control circuitry for causing it to share load current
equally in the system;
Figure 3 is a circuit and lo~ic diagram and is a
schematic illustration of a power supply and the control circuitry
of ~he present invention;
Figure 3A is a schematic diagram of a bridge rectifier
circuit ~lich may be used in the circuit of Figure 3;
Figure 4 (with Fig. 1) is a timing diagram of the
pulse-width modulator loaic.
DESCRIPTION OF THE PREFERRED E,~BODDMENT
Figure 1 is a block diagram of a system incorporating a
plurality of power supplies coupled for driving a common load
together with control circuitry to force the power supplies to share
the load current equally. It illustrates a load 10 driven by a
plurality of power supplies. Each F~wer Supply, labeled 12-1, 12-2,
~5 and 12-n is identical with all other supplies. m e output volta~e
across the + and - of each supply is a regulated DC voltage. The +
line provides current from each supply to junction 14 which provides
the load current IL to the load 10. The - line of each supply is
coupled to junction 16 and provides the co~mon coupling to the
load. The load current IL is the
sum of the supply currents Il ~ I2 + In. The AC power input ls
provided to all of the supplies on lines 18 and 20. Each power
supply has associated therewith a control circuit M, labeled 22-1,
22-2, and 22-n. Each of the control circuits M includes the
circuitry for sensing the output current of its associated power
supply and averaging the current supplied by all power supplies in
the system. The common couplin~s provided by lines 24 and 26 are
coupled respectively to the 1 and 2 terminals of each of the control
circuits M. mese common couplings provide an average voltage
derived from the average current provided by each supply in the
system designated VIFB (AVG). As will be described in more detail
below, it is the function of the control circuits M to adjust the
resFectively associated Power Supply to produce less output current
when it is determined that the senses output current for that supply
exceeds the average current provided by all supplies in the system.
Figure 2 is a block diagram of one power supply and its
associated control circuitry for causin~ it to share load current
equally in the system. Since each Power Supp]y 12 is the same as
all other supplies, and each Control Circuit M is the same as all
other control circuits, only one combined circuit will be described
in detail. Power Supply-l has been used as a reference, and is
shown in block diagram form enclosed within dashed block 12-1.
Similarly, the control circuitry associated therewith designated Ml
is shown in block diagram form enclosed within dashed block 22-1.
m e Power Supply receives AC power on lines 18 and 20, which are
respectively directed to the RectiEier and Filter 3~. m is
circuitry provides hi~h voltage unregulated DC power across lines 32
and 34. This unregulated power is applied to the Power ~itches 36
w~lich in turn provide si~nals on coupling line 38 to the Rectifier
Circuit 40. me output from the Rectifier Circuit 40 is provided
3G across lines 42 and 44 to the Filter ~6, the output
of which is provided on lines 48 and 50 -to junc-tions
14 and 16 respee-tively. The current flow Il on line
48 is the load current of th~ Power Supply that is
provided to ~oad 10~ The voltage be-tween lines 48
and 50 is designated V01, and in this conEigura-tion
also is provided on line 52 as a feedbclck path for
providing ~eedback voltage VFB. For -the conriguration
shown, the autp~lt voltage V~l is the same as VFB, but
it should be understood that the feedback voltage VFB
could be a scaled down fraction of the output voltage
if so desired. A Pulse Width Modulator cirGuit 54
provides the Drive A signal DR~ on line 56 and the
Drive B signal DRB on line 58 to control the operation
of the Power Switches 36, as will be described in more
detail below. The Power Switches circuitry 36 also
includes circuitry for sensing the current flow in the
Po~er Supply and provides an indication of the current
level on line 60.
The Control Circuitry Ml includes a Current
Feedback circui~ 62,and in response to the curren-t
levels sensed on line 60,provides a signal on line 64
to the Peak Average Nett~ork 66. It functions to
rectify and average the peak values o-E a waveform
- that is proportional to the current flowing through the
Power S~itches 36. T~e signal resulting therefrom is
provided on line 68 and is u-tilized in determining -the
sum of the currents being provided by other power
supplies in the system. A Current Error Sense circuit
70 com~ares the current being provided by Power-Supply
1 to the current being supplied by the other power
supplies in the syste~ by comparison of the voltage
signal derived from the Peak Average Network 66 to the
voltage VIFB (AVG) received on lines 24 and 26. When it
is determined that the siqnal on line 68 is greater
than that indicated by the siqnal on line 24, a siqnal
is provided on line 7 to the Current Error Amplifier 74
thereby causing it to provide an output voltage Vl on
line 76. The Voltage Error Amplifier circuitry 78
receives a re-ference voltage VR on line 80 in addition
to the feedback voltage VFB on line 52. When the feed-
back voltage exceeds the referenced voltage VR, or when
the output voltage V1 is present, the Voltage Error
Amplifier 78 ~ill provide a control voltage VC on line 32
which Eunctions to con-trol -the operation of -the Pulse
Width Modulator 54. The signal on line 8~ ~ill resul-t in
the Pulse ~idth Modulator circuitry being adjusted such
that the drive signals DRA and DRB will cause the Power
Switches 36 to be operated at a lower duty cycle thereby
resulting in a lower output current I1 to the Load. The
reduction of the level of the output current Il will con-
tinue until such time as it i5 sensed that the current
being provided by Power Supply 1 is approximately equal
that of the average of all power supplies in the sys-tem
as indicated by the signal VIFB (AVG~. The functional
- relationship of the circuits described in block diagram
form will ~e illustrated and described in more deta;l
below in logic and circuit schematic diagram representation.
~0 FIG. 3 is a circuit and logic diagram and is a
schematic illustration of a power supply and the con-trol
circuitry of the present inven-tion. This circuit schematic
diagram illustrates in detail an embodimen-t o-E the inven-
tion, as described in a block diagram form in FIG. 2.
Circuit components are functionally identified and rela-ted
to the block symbols previously described. There is
illustrated a porticn of the inverter power supply together
with the control circuitry for effecting the forcing of
equal load sharing, The unregulated ~igh voltage DC
provided from the Rectifier and Filter 30 is applied to
circuit lines 32 and 34. The Power Switches are shown
enclosed in dashed block 36 and include power transistors
QSA and QSB, each of which comprises a power NPN tran-
sistor. The emitter electrodes are coupled in common to
line 34. The collector electrodes are coupled -to respec-
tively associa-ted ends of the primary winding of coupling
transformer Tl. The base electrode of QSA is coupled
C1 5
_ 9 _
to line 55 and the base electrode of QSB is coupled to line 58, for
receiving the pulse width modulation control signals. The
unregulated high voltage DC provided on line 32 is coupled to one
end of the primary winding of current sampling of transformer T2,
with the other end of the primary winding being coupled to the
center tap of the primary winding of coupling transformer Tl. The
signals generated by the P~wer Switches are coupled to the secondary
winding of coupling transfonner Tl, which in turn is coupled to the
Rectifier Circuit shown enclosed in dashed block 40. This Rectifier
Circuit is preferably comprised of a pair of diodes DBl and DB2,
each of which has an anode terminal coupled to its respectively
associated end of the secondary winding and which have its cathode
terminals coupled in common to line 42. me center tap of the
secondary winding is coupled to line 44. The circuit may also be
adapted to use a full-wave bridge rectifier as shown in Figure 3A.
Figure 3A shows a schematic of a bridge rectifier circuit which may
be alternatively substituted for the rectifier 40. Note that in
this configuration a center tap for the secondary oE transformer Tl
is not required. nhe Filter is shown enclosed in dashed block 46
and is comprised of Inductor Ll and Capacitor C. The regulated DC
output voltage is provided across lines 48 and 50, with the feedback
voltage VFB derived fro~ circuit junction 14 on line 52.
nle Pulse Width l~odulator logic circuitry is shown
enclosed is dashed block 54. It includes a clock 90 that provides a
source of regularly occurring clock pulses on line 92 for driving
Toggle Flip Flop circuit 94 and Mono-stable circuit 96. The Toggle
Flip Flop functions to provide a true output signal Q on line 98 and
a complement signal Q on line 100 for one clock cycle, and then
reverses the singals on lines 98 and 100 on the next subsequent
clock cycle. me Mono-stable circuit 96 provides an output signal W
on lines 102 to 102-1, and defines the duration or width W of the
control signals that will activate the Fower Switches, thereby
- 9A -
defining their respective duty cycles. AND circuit 104 receives
input signals from lines 98 and 100 and provides an output signal
DRA to line 56. AND circuit 106 receives
-10-
input signals from lines 100 and 102-1 and provides
an outpuc signal DRB to line 58. The duration of -the
signal provided b~ the Mono-stable circuit 96 will
be determined ~y -the control si~nal provided on line
82.
The Eunctioning of ~he Pulse Width Modulator
circuitry can he further unders-tood ~y consideration
of the timing diagram ill.ustrated in FIG. 4. The Clock
signal has a clock cycle time T. T~e Clock signal
defines regularly occurring -signals Q and Q. The duty
cycle defining signal ~ has a varying duration t
determined by the control signals. The signal W in
conjunction ~tith the signal Q determines the duration
of the Drive A signal DRA, and the W signal in conjunction
with the Q si~nal determines the duration of the Drive
B signal DRB.
The logic circuits that comprise the Pulse
r~idth Modulator circuitry 54 are log~c circuits that
are well known and are availa~le commercially, and
will not be descri~ed in detail as to their electrical
function, it ~eing understood ~y those skilled in the
art that the logical function describes the operation
within the circuit.
Returnin~ to a consideration of FIG. 3, the
~5 Control Circuitry M that embodies -the subject invention
will be descri~ed in detail. The Current Feedback
is shown enclosed in dashed block 62 and comprises
current sampling Transformer T2. The secondary winding
of Transformer T2 has one tèrminal coupled to line 26
and the other terminal of the secondary winding coupled
to line 64 for providing the current feed~ack signal
to the Peak ~verage Net~ork shown enclosed in dashed
block 66. This Ne-twork includes Diode Dl whose anode
terminal is couplea to line 64 and ~hose cathode
terminal is coupled to junction 110. Capacitor Cl
is coupled across junction 110 and common line 26.
3~q ~Q~
-- 11
Junction 110 is coupled by line 112 to junction 114. Resistor Rl is
coupled between junction 114 and line 26.
Transfonner T2 is a current sensin~ transformer of the
type available commercially, and characteristically has a turns
ratio of 50 to 1. ~le pr;mary o Transformer T2 senses tlle current
signals resulting from the operations of Switching Transistors Q6A
and QSB. The signal generated in the secondary is provided to
Network 66 which functions to peak rectify and average the peak
values of the waveforms sensed. When Diode Dl is forward biased, a
lo char9e will be imposed on Capacitor Cl. Resistor Rl provides a
discharge path for Capacitor Cl and results in a signal VIFB at
junction 114. In the preferred embodiment, Capacitor Cl is
characteristically 0.1 micofarads and Resistor Rl is
characteristically 10,000 ohms. The signal provided on line h8 to
the Current Error Sense circuitry, shown enclosed within dashe~
block 70 essentially is compared to the VIFB (AVG) signal received
on line 2~. It includes a sum~ing Resistor R2. If Pbwer Supply 1
is providing more load current than other power supplies in the
system, the signal VIFB will be greater in value than the signal
VIFB (AV~), and there will be a voltage differential V I, such that
the signal level on line 72a will have a value greater than the
signal level on line 72b. Resistor R2 has a value of 100,~00 ohms
for this embodiment.
A signal representing the average load current output of
all of the modular power supplies is derived as sho~n in Figures 2
and 3. me output VIFB of each peak average net~ork 66 is connected
to a common pair of busses 24, 26 through series resistor R2 of
network 7~. The bus thus serves as a summing junction to provide a
voltage signal VIFB (AVG) that is the average of the peak detected
by all Feak detectors for modules Ml, M2, . . . Mn, and represents
the average load current, i.e., the average of the collector current
delivered by transistor ~6A and Q6B of all inverters to the load 1~
-- llA --
through the output transformer Tl. This averaye signal serves as a
reference for each of the difference amplifiers Al for comparison
with the individual rnodule current.
The Current Error ~mplifier shown enclosed in dashed
block 74 is comprised of Operational Amplifier Al together with
compensation network elements including Resistor R3, Capacitor C2
and Resistor R4. Operational Amplifier can be a type LM32~ circuit
available commercially and has its plus terminal coupled to line
40 72b. Resistor R3 has one terminal coupled to line 72a and its other
terminal coupled to junction 116 ~hich in turn is coupled to the -
input of Operational
-12-
AmpliEier Al. T~e ou-tput of -the Opera-tional Amplifier
is coupled to junction 118. Capacitor C2 has one
terminal coupled to junction 116 and its other terminal
coupled to Resistor R~, with the second termlnal oE
R~ coupled to junction 118. Resistor R3 has a value
of one megohm and R4 has a value oE 100,000 oh~s.
Capacitor C2 has a value of 0.1 microfara~s. As
long as the si~nals VIFB and VIFB ~VG) are essentially
balanced, the Operational AmpliEier Al outpu-t Vl will
remain 'high and will reverse bias diode D~ which has
its cathode te,rminal couplecl via line 76 to junction
118. When VIFB is greater than VIFB ~AVG~, -the positive
voltage differential across Resistor R2 will provide a
signal imbalance on line 72a and 72b which will result
in the Operational Amplifier Al to have its output
signal Vl tending to go lo~, thereby forward biasing
Diode D2. Thus it can be seen that Operational
Amplifier Al only affects the power supply operation
when the power supply current exceeds i-ts share o-E'the
load, since in all other cases Diode D2 will be
reversed biased and effectively ~locks any feedback
effect to the Pulse Width Modulator circuitry with
re~ard to the sensed current levels.
The Voltage Error Amplifier is shown enclosed
in dashed ~lock 78. It includes Operational Ampli-Eier
A2 which can be a type LM324 circuit. The anode
terminal of Diode D2 is coupled through Resistor R5
to junction 120. The Reference Voltage VR is coupled
via line 80 through Resistor R6 to junction 120,
which in turn is coupled to the -~ input terminal of
A2. The feedback voltage VFB is coupled via line 52
through Resistor R7 to junction 122 and provided to the
- input of A2. The output terminal of Operational
Amplifier A2 is coupled to junction 124. The
compensation network ccmprised oE Resistor ~8 and
Capacitor C3 is coupled in series between junctions
122 and 124,for this embodiment Resistors R5, R6, R7,
and R8 are each 10/000 ohms and Capacitor C3 is 0.1
~ 2~
-13-
microfarads. When vol-tage Vl tends -to go low and
Diode D2 is forward biased, as a result of the sensed
imbalance o~ current supplied by the power supply,
it results ln a decrease in the reference input to
the plus terminal of Operational ~mplifier A2, as
compared to the feedback volta~e VFB, and causes
A2 to drive its output control vol-tage VC low thereby
controlling the Mono-s-table circuit 96 to shorten the
duration of its output pulses ~, there~y decreasing the
duty cycle of the Power Swi-tches. When Diode D2 is
reversed biased, A2 will compare -the reference voltage
VR to the Eeedback voltage VFB and adjust duty cycle
to maintain a regulated output voltage.
The circuit described in detail can character-
istically respond to an AC input of 65 to 250 volts AC
and at frequencies of 50 to ~00 ~ertz. The system can
be designed to provide regulated output to the Load
for each power supply o-f diferent levels. While
different levels can be provided, the embodiment
described would typically provide a value of V01 oE
5 volts DC. In this confi~uration, the feedback voltage
V~B is e~ual the output voltage and would be nominally
5 volts. Similarly for the voltage resulting from the
current sense circuitry would provide a voltage VIFB
of 5 volts. The average sensed voltage of all power
supplies in the system VIFB (AVG) would also be
typically 5 volts. The difference o-f voltage V~I
occurring across Resistor R2 would approach zero in
the ~alanced state and would only show a voltage
differential ~hen a power supply was supplying an
un~alanced portion of the current to the load. The
re~erence voltage VR would be matched to the ou-tput
voltage and would be typically 5 volts for this
embodiment. The control voltages Vl and VC would be
variable, and would have movement upward or downward
depending upon the balance conditions of the Operational
Amplifiers Al and A2 respec-tively. It is of course
-14-
apparent to those skilled in the art that power
supplies providing different output voltage levels
can ~e designed ~ithout departing from the scope and
spirit oP the invention.
It can be seen from -the foregoing detail
description of a preferred em~odiment that the o~jects
and purposes of the invention have been achieved.
Various changes and modiPications in the circuit oP
the preferred embodiment will be apparent to those
skilled in the art, and without. departing from the
spirit of the invention, ~hat is intended to be protected
by Letters Patent as set forth in the appended claims.
What is claimed:is:
~ .. . .. .... .... .. .. . . . .
