Note: Descriptions are shown in the official language in which they were submitted.
VEHICLE DRIVE CONTROL SYSTEM
, . .. .
BACKGROUND OF THE I~JVENTION
.
Field of the invention
The invention is in the field of control circuits
5 ~or vehicle drive systems and is particularly applicable
for vehicles having a differential mechanism dividing
torque between two outpu~ shafts.
_qcri~tio_ of the Prior Art
Various mechanisms have been devised in the auto-
10 mobile and trucking industry to control excessive slippage
between the driving ~?heels of a vehicle. Such devices
usually serve to equalize the rotational speed of two or
more output shafts which are driven by a main driye or
input shaft. The driven shafts may practically be referred
15 to as output drîve shafts since they are used to drive
vehicle wheels either directly or through some intermediate
mechanical linkage. Some differential in speed between
these shats is necessary ~o permit different rotational
speeds of ~he driving wheels as the vehicle negotiates a
20 turn, encoullters bumps or holes in the roadway,or traverses
rough terrain. Most typlcally, the output d~ive shafts
are coupled by means of a differential to a main driveshaft
or propeller shaft, and the dif~erential provides the mech-
anism for dividing torque evenly between the output driv~
25 sllafts and allowing for different rotational speeds in
the output drive shafts. In the trucking industry, it is
also advantageous to provide multi-axle tandem driye
--2--
assemblies utilizing an inter-axle differential coupling the
main propeller shaft from the engine to the differentials
on each of the two rear driving axles hereafter referred
to as the forward rear and rear rear drive axles.
Under normal operating conditions, when the vehicle is
traveling on gGod roads and under dry weather conditions,
excessive slip between output drive shafts is usually not
encountered and no corrective actions are required. However,
during adverse weather conditions the vehicle may be travel-
10 ing through mud or ice and an exceptional amount of slippage
may occur as when one of the wheels loses traction and begins
to spin excessively, hereafter referred to as a "slip condi-
tion". It has therefore been advantageous to providè lock-
out mechanisms or other control devices to eliminate the
15 excessive difference in rotational speeds of the differen-
tial output shafts.
Mechanical lockout mechanisms for coupling the main
drive shaft to an output shaft of a differential have
been utilized in the trucking industry and examples are
20 shown in U.S. Patent 3,264,901 and 3,390,593. Mechanical
locking devices have also been utilized on inter-axle
differentials of tandem drive road~ay vehicles as illus-
trated in U.S. Patent 2,870,853,
A ratio sensitive electronlc control for limited
25 slip differentials is disclosed in U.S, Patent 3,138,970.
An exemplary teaching o~ an electromechanical
system utilizing selective bralce control to limit the speed
differential between a pair of wheels of a vehicle is
shown in U.S. Patent 3,706,351.
Generally speaking, in a d~;Eferencial mechanism, by
locking any two shafts of the group of three shafts
consisting of the input drive shaft and the two output
drive shafts one locks all three sha~ts and eliminates the
"differential" function. The terms !'lock-out," "lock
35 condition" or "locked condition" generally refer to the
condition wherein the differential mechanism coupling
-3-
the main drive shaft to the two QUtpUt shafts is rendered
inoperable with the result ~hat both output shafts rotate
at the same speed,and torque delivered from the engine is
provided to both output shafts as required by the external
5 resistance each output shaft is subject to.
Lock-out may typically be achieved manually by
the vehicle driver upon sensing a slip condition or may
be achieved under automatic control as for example, in
U.S. Patent 3,138,970 menti~ned above. Slip control may
10 also be provided by means other than locking out a vehicle
differential, and the brake control system of U.S.
Patent 3,706,351 constitutes an alternate approach to
the problem. Electronic circuitry may thus be provided
to control means for eliminating or at least decreasing
15 the amount of slip to within acceptable limits.
Typically, the electronic control is responsive to
sensed input speed signals and provides continuousmonitoring
and control. Such continuous monitoring systems are
susceptible to repeated cycling of the control apparatus
20 inasmuc~ as output shaft speeds tend to become synchronous
almost immediately after lock-out thereby destroying the
error signal before the vehicle is actually out of its
slip condition. The electronic control continues to
monitor the ou~put shaft speeds and if indeed the vehicle
25 is not out of il:s initial slip condition upon release
of the locking device the error signal wil~ be regenerated
and the con~.rol locking device reapplied. Oscillations
may typically occur within the drive system at a rather
lligh frequency of between 1-3 Hz. Such oscillations
30 may adversely affect the vehicle by repeatedly stressing
the drive train components and may disturb the vehicle
operator, particularly if the control system continues
to recycle and the vehicle fails to traverse that portion
of the road presenting the "slip" condition.
-- 4
SUMMARY OF THE INVENTION
It is an object of the invention to eliminate the
disadvantages of the prior art by providing a slip control
apparatus which is not susceptible to rapid cycling, but
which rather maintains the "locked" condition for a
predetermined set time.
' To this end, the invention consists of apparatus
for use on a vehicle having a main drive shaft and first
and second output shafts operable for providing driving
torque to wheels of said vehicle and means for coupling
said main drive shaft to said first and second output
shafts, said apparatus comprising: (a) means for sensing
the relative rotational speed of said first and second
output shafts, and (b) control means responsive to said
sensing means detecting a slip condition and includin~
means for eliminating said slip condition and means for
actuating said means for eliminating said slip condition,
said actuating means being operable for a predetermined
time after actuation thereof.
A feature of a preferred form of the invention is
to provide a control apparatus particularly useful in
coupling mechanisms of the differential type for providing
an extended and fixed locking time interval after excessive
difference in output speeds. Typically the fixed locking
time interval is greater than 20 seconds and may be as
great as several minutes depending upon the type of vehicle
and its application.
~nother preferred feature is to provide a loclc-out
mechanism having an extended lock-out operating tlme ater
actuation for use on inter-axle differentials of a tandem
drive vehicle.
Another preferred feature is to provide a fail-
safe indicating circuitry for a slip control apparatus to
ensure disabling of the lock-out control if a true locked
condition is not sensed after a given interval of time.
The utilization of the fail-safe circuitry permits
verification of operation of the mechanical lock apparatus
and sensor functions.
Another preferred feature is to provide a self-
testing slip control circuit for vehicles which automat-
ically tests operation of the slip control circuitry uponpower-up of the vehicle.
A further preferred feature is to provide a slip
control lock- out device which includes a brake override
circuit to inhibit further lockout commands during braking
of the vehicle.
BRIEF DESCRIPTION_OF THE DRAWINGS
These and other features of the preferred
embodiment of the invention will become clear in
connection with the following specification wherein:
FIGURE 1 is a block diagram illustratin~ the
principles of the electronic control circuitry in
acordance with the invention;
FIGURE 2 is a top plan view of a truck cab and
carrier utilizing an inter-axle differential in accordance
with the principles of the invention;
FIGURE 3 is an enlarged view showing portions of
the inter-axle differential of FIGURE l;
FIGURE 4 is a block diagram of a preferred
embodiment of the control circuitry in accordance with the
principles of the invention;
FIGURES 5A, 5B, 5C and 5D are schematic diagrams
detailing the circuitry of the preferred circuit
embodiment of FIGURE 4.
DESCRIPTION OF THE PREFERRED EMBODIMENT
. . .
FIGURE 1 is a block diagram depicting a slip
control circuitry in accordance with the invention. The
control means generally indicated at 10 is connected to
receive electrical signals from two sensors (not shown)
which detect the rotational speed of any two of the output
drive shafts. Typically, one sensor may be positioned to
-- 6 ~
detect the ~otational speed of the main drive (input)
shaft at the input to a differential, and a second sensor
may be positioned to detect the rotational speed of an
output shaft coming from the differential. The sensors
themselves may be of,conventional design such as magnetic
sensors which provide an output pulse upon passage of each
tooth of a gear or rotor secured to the drive sha~t. As
such, the frequency of the incoming signals is
proportional to the speed of rotation of the shaft. The
sensed signals Wl and W2 are provided along input
lines 11 and 12 to a differential circuit 14 which
measures the difference between the two signal
frequencies. The differential circuit 14 may typically
comprise a comparator (COMP) for comparing the difference
8 between the absolute values of the two input signals as
monitored by adder 7 where the absolute values are
proportional to their respective input frequencies with a
reference value. The reference value may itself be
generated by summing the two input signals by adder 9 and
multiplying at 1~ by a reference value 50.5 for example)
appropriate for the type of comparator utilized. The
differential circuit 14 thus provides an output signal
along line 15 only if the differential in rotational shaft
speed is greater than a predetermined allowable slippage
level. Some slippage is obviously acceptable due to
normal operating conditions of the vehicle as for example
to permit travel during turns and along uneven terrrain
and to accommodate different tire radii.
The output signal along line 15 may be termed an
error signal or DIFF signal indicating an excessive
differential in the rotational speed of the shafts. The
DIFF signal is fed to two timers, Tl, shown at 16 and T3
shown at 18. Timer Tl provides an output pulse after a
nominal turn on delay on the order of .25 - .5 seconds and
is provided to minimize "false" actuation in the presence
of incipient wheel slip. After this turn on delay, Tl,
the output of timer 16 is fed to the set input
--7--
o a RS flip-flop 19 which subsequently provides an output
pulse at the Q output thereof. The output pulse is fed
via a line 20 to power amplifier 21 which subsequently
drives a control device or solenoid 22.
The control device 22 is utilized to actuate
means for eliminating the slip condition detected by the
sensor inputs. A solenoid employed as the control device
22 may be utilized to shift a clutch collar and thereby
place a differential mechanism in a "locked condition."
Such an application will hereafter be described in
greater detail. The control device 22 may also be
utilized in combination with a selective brake control
system similar to that disclosedin U.S.PatentNo.3,706,351
cr in a fo-~r-wheel dri-~e vehicle of the type discllsed
in U.S. Patent No. 3,557,634 to engage a clutch and there-
by provide drivingtorque the forward drive axle of such
a vehicle.
The driving signal from power amplifier 21 also is
fed to a ~imer T2 indicated as 23. Timer T2 is the basic
20 cycle timer and provides a predetermined time interval,
ty~ically on the order of 30-60 seconds, during which the
control device 22 remains actuated. ~t the end of this
predetermined time interval, T2 provides an output signal
to OP~ ~ate 24 ~hich subsequently provides an output to
25 the reset term:inal of flip-flop 19. Upon reset, the Q
output of ~.lip-~flop 19 goes low thus releasing the control
device 22. The reset of flip-flop 19 may also occur after
timer T3, the failsafe timer times out since the OUtp~lt
of 18 is also fed to an input or OR ga~e 24. FailsaEe
30 timer T3 is typically set to be greater than the time
interval T]. and less than a time interval T2. The purpose
of the fail-safe timer is to release the control device 22
in the event the slip condition has not been eliminated
after the time interval T3. For example, the tima
35 interval T2 may be set for 30 seconds, and the time
interval T3 may be set for 15 seconds. If the DIFF sig-
nal on line 15 is still present at the end of 15 seconds,
the failsafe timer T3 resets the flip-flop 19 ~hus
releasing the control device 22. The failsafe timer
-8-
operates on the premise that the previously sensed slip
condition should have been elîminated after the time
interval T3 so that the ~IFF signal along line 15 should
no longer be present. If the DIFF signal is still present,
5 then it is assumed that some malfunction may have
occurred, for example a sensor failure or failure of the
lock-out mechanism. In either event, it is desirable
to release the control device and provide an indication
to the operator of the failsafe condition. The ~ime
1~ interval T3 may be set anywhere within thewi-alow define~by
Tl and T2. For example, one may have the time interval
l2 at 30.5 seconds with the timer T3 at 30.0 seconds.
Such a situation enables a very narrow window for the
timer T3 (from 30.0 to 30.5 seconds) and thus may be
15 utilized to eliminate detection of spurious DIFF signals
due to heavy gear vibrations and the like.
The preferred embodiment of the invention as
utilized in an inter-axle diferential of a tandem drive
vehicle is shown in FIGU~ES 2-5. FIGURE 2 shows a top
20 plan view of a truck cab 20 and a carrier 22. The carrier
22 is supported by a tandem drive rear end having a
forward rear a~le 24 and a rear rear axle 26.
Torque from the vehicle engine is transmitted by
the main drive or propeller shaft 30 to an inter-axle
25 di.fferential 32 supported within a housing 31 which divides
that torque bet:ween the forward rear differential 34 and
the rear rear clifferential 36. The prop shaft 30 is
connected to the inter-axle differential input 38 by a
universal joint 40. The inter-a~le differential 32
30 divides the torque provided to input 38 between a first
output or through shaft 42 and a second output shaft 44.
With reference to ~GURE 3, the output shaft 42 is driven
directly by the left side gear of the differential 32 and
the output shaft 44 is driven by a series of "drop" gears
35 45-47 which in turn are driven by the right side gear of
the differential 32. Output shaft 44 rotates a pinion
gear which drives the ring gear of the forward rear
differential 34. Output shaft 42 is connected by a
universal joint 48 to a propeller shaft 50 which in turn
~C~3~
~9_
drives the ring gear of the rear rear difEerential 36.
~ collar 52 is splined ~o output shaft 42. The
collar 52 is axially movable relative to the shat 42
by a fork (not shown) and may be moved to the left as
5 shown in FIGURE 3 into enga~ement with teeth 54 provided
to the hub of drop gear 45. When the collar 52 is engaged
with teeth 54, the drop gear 45 and the output shaft 42
are mechanically locked together and rotate at the same
speed. The differential 32 is precluded from changing
10 the equal division of speed until the collar 52 is
disengaged from the teeth 54.
A representative tandem axle assembly including an
inter-axle differential and a lock-out mechanism is shown
in U.S. Patent 2,870,853 as well as in Rockwell SFHD,
15 STHD, SUHD Parts Book, Publication No. SP-7646-1 published
by Rockwell International Corporation, Troy, Michigan.
The foregoing references are incorporated herein by
reference.
Two sensors 56 and 58 are carried by the differ-
20 ential housing 31. Sensor 58 is respon~sive to rotarymovement of the teeth of gear 45 and thereby senses the
rotational qpeed of output shaft 42. Sensor 56 i9
responsive to rotary movement of a toothed rotor 60
carried by the casing of differential 32 and thereby
25 senses the rotational speed of the main drive shaft 30.
Sensors 56 and 58 provide output signals along lines 62
and 64 to the control means or controller 66 located on
the housing 31 of inter-axle differential 32. Upon
sensing a speed differential ln response to the signals
30 along the input signal lines 62 and 64, the control means
66 provides an output signal along line 68 to air solenoid
valve 70 which operates in a conventional fashion to
move collar 52 and lock-out the inter-axle difEerential
32. Upon actuation of a lock-out condition, control means
35 66 provides a signal to indicator light 72 which is visible
to the driver of the vehicle.
Control means 66 is powered by the brake light
circuit and includes means to disable the lock-out
-10-
mechanism upon operation of the vehicle brakes. FIGURE 2
shows a battery indicated at 74 connected to a stop light
switch 76 closed in response to operation of treadle valve
7~. The inter-connection of the control means 66 to the
5 brake light circuitry also enables detection of an open
line condition. In this case, the open brake circuit would
be detected by the control means 66 which would disable
the lock-out operation.
FIGURE 4 is a block diagram showing the main com-
10 ponents of the control means 66. Input signals fro~l
sensors 56 and 58 are fed along the input lines 62 and 64
to respective signal shapin~ circuits 80 and 82. The sig-
nal shaping circuits 80 and 82 effectively convert the
sinusoidal input signals to square wave forms which are
15 subsequently fed along lines 84 and 86 to gated trigger
circuits 88 and 90. The gated trigger circuits 88 and 90
are alternately gated by ~eans of an oscillator 92 so
that either a pulse is provided along an output line 94
or 96. Lines 94 and 96 are connected to inputs of OR
20 gate 98 whose output is connected to an up/down counter 100
via a line 102. ~he signal along line 102 is indicat~ve
of the speed pulse from either one or the ott~er sensors,
and the ~requency of the pulse is directly proportional
to the rotational speed as of the shaf~s 30 and 42
25 measured by the sensors 56 and 58. Oscillator 92 also
provides a signal along line 10~ to the up/down counter
100 so that the signal along line 102 can be correlated
as co~ing~ either from the gated trigger circuit 88 or
gated trigger circuit 90. One gated trigger circult i9
30 utiliæed to provide up counts in the up/down counter 100
while the other gated trigger circuit provides the down
counts. The signals along line 104 from oscillator 92
essentially enable operation of the counter 100 in either
the "up" mode or the "down" mode depending upon which oE the
35 particular signal sensors is being counted. Up/down
counter 100 is preset as, for e~ample, to the binary v~lue
. Counting down on up/down counter 100 indicates that
one sensor, for e~ample sensor 56, is providing more
-11-
signals per unit time than the other sensor, as for example
sensor 58. Counting up on the up/down counter 100indica~s
the reverse condition. The count up and count down time
window is provided by means of an oscillator 110 and
5 sample window generator 112. Typically, the window time
frame may be on the order of 200 milliseconds. The up/
down counter 100 is preset with the binary value 4. If a
zero COUht is reached within the sampling time window,an
output signal,DIFF,is provided along line 114 at the out-
10 put of up/down counter 100. Similarly, if a binary 8 isreached within the sampling time window on the up/down
counter 100 a DIFF signal is similarly generated along
line 114. The DIFF output signal is fed to a lock flip-
flop (F/F) 116 and to one input o~ a NA~D gate 118. The
15 DIFF signal serves to set the lock flip-flop 116 so that a
signal is provided along the Q output thereof to a driver
circuit 120 along line 122. The output of driver circuit-
ry 120 feeds a solenoid 71 which drives the collar 52 of
the inter-axle differential to lock-out the differential
20 32. Driver circuitry 120 also provides a visual indication
to the vehicle operator by means of energizing indicator
lamp 72.
Lock flip-flop 116 is reset upon receipt of ~he re-
set pulse from a coùnter 124 at the passage of a predeter-
25 mined time preset in counter 1~4 and started upon genera-
tion of the DIFF signal. The counter is thus enabled and
begins to coun~ upon receipt of a count enable signal from
lock flip-flop 116 along a line 123. The reset signal from
counter 124 is provided to the lock flip-flop 116 along a
30 line. 128. The reset si~nal along line l2~ will occur 435
seconds after generation of the DIFF signal along line114
in the embodiment described. The control circuit ~ay of
course be modified to provide fixed time intervals of dif-
ferent duration~, preferably greater than about 20 seconds
35 for other embodiments of the invention. A second output
from the counter 124 is provided along a line 130 to the
second input of NAND gate 118. This second output corres-
ponds to the failsafe timer T3 of FIGURE 1. A~ain, the
count enable signal along line 126 is utilized to provide
40 the count starting rererencefor enabling coun~er 124.
-12-
The output of NAI~D gate 118 is utilized to set a
failsafe flip-flop 136 provided that the DIFF signal
along line 114 is present at the same time the output of
counter 124 provides a signal on line 130. This condition
5 effectively requires that the DIFF signal be present at
the time T3 utilizing the nomenclature of FIGURE 1. Upon
setting of the failsafe timer 136, a signal is provided
along a line 138 to a driver circuit 140 which in turn
energi7es a failsafe indicator 144. An output o' fail-
10 safe F/F 136 along line 125 to the up/do~n counter 100also serves to shut down or disable the control apparatus
so that no further operation of driver circuit 120 is
possible.
FIGUR~ 5A, 5B, 5C and 5D are schematic circult
15 diagrams showing the details of the block dia~ram of FIGURE ~.
Signal shaping circuits 80 and 82 are identical and only
one circuit wiîl thus be described. Signal shaping cir-
cuit 80 comprises a voltage comparator 180, zener diode Dl,
and filter networks provided by resistors R:l, C15 and R2,
20 C16 and C4. Resistors R5 and R9 form a voltage divider
and provide a reference voltage to one input of the
voltage comparator 180 with the other input fed by the
signal from the sensors. Conventional sensors may be
utilized such as the variable reluctance magnetic
25 pickup-type which provides a sinusoidal input to the
- shaping circu:it 80. The output of comparator 180 is
e~fectively a squarewave and is fed to gated trigger
circuit 88. For ease of description, it will be assumed
that the output of voltage comparator 180 is fed
30 directly to the input of the gated trigger circuit 88 and
the three N~ND gates (elements 380, 382 and 38~ here-
be~ween will be e~plained below. Gated trigger circuit
88 comprises a D flip-flop 190 which is set upon receipt
of the output signal from voltage comparator 180 and
35provides at its output a high logic signal in response
thereto. The ~ output of flip-flop 190 is fed to one
input of a four input AND gate 192 whose other three
inputs are provided by a counter output to be described
hereinafter. The gated trigger circuit 88 further com-
40pr~ses a buffer/inverter driver 194 which feeds a logic
~,
-13-
~AMD gate 196. The output from ~AND gate 196 is apositive
pulse of about 20 microsecnnds width and is fed to the out-
put line 94 from the gated trigger circuit 88. A similar
20 microsecond pulse is provided along the output line
5 96 of the gated trigger circuit 90. Lines 94 and 96 are
fed to OR gate 99 which is fabricated from a NO~ gate 200
connected to an inverter 202. The output o~ OR gate 99 is
ed to the up/down counter 100 which may, for example,
be of a presettable binary type.
Oscilla~or 92 may comprise a sampling oscillator
210 coupled to a four bit bînary counter 212. Counter
212 provides an outPut code along lines 214 a, b, c and
d. Output lines 214a-c provide binary codes identified
as A, B and C respectively. Codes A, B, C provide condi-
15 tion code inputs to A~D gate 192 of the gated trigger
circuit 88. Likewise, condition codes A, B, C provide
inputs to the corresponding AND gate of gated trigger
circuit 90. The dif~erent condition codes insure that
only one o~ the gated trigger circuits 38 and 90 will be
20 triggered at a~y given time. Oscillator 210 may typically
be a 40 KHz oscillator and ~he sampling rate provided
by the four bit counter to each of the gated trigger
circuits 88 and 90 as typically on the order of 5 KHz.
The sampling time is chosen to be much larger than even
25 the fastest expected sensor rate which is in the range
of 0-1 KHz.
The four bi~ binary counter 212 provides an output
along line 104 to the up/down control input of the up/down
counter 100. Consequently, up/down counter 100 will co~mt
30 either in the up or down direction depending upon the
state of the control input along ~ine 104 which continual-
ly alternates ~rom one sta~e to the other in synchronism
with the gating o~ the gated trigger circuits 88 and
90 .
Also shown in FIGURE 5A are the oscillator 110
and sample window generator 112. Oscillator 110 provides
a pulse having a period of 13.3 ms at its output terminal.
This pulse is fed to the sample window generator 112
along line 220. Sample generator 112 may comprise a
-14-
divider circuit and is configured to divide the incoming
signals by 16 thereby providing a nominal 200 ms output
signal along a line 222 feeding one input of NAND gate 224.
The other input of NAND gate 224 is conditioned by the
5 output of N~ND gate 22~. The output signal of NAND
gate 224 is fed to the up/down counter 100 and presets the
co~mter to the binary 4 state every 200 ms. Consequently,
the up/down counter 100 has a window for receiving speed
pulses along line 102 for a period of 200 ms before being
10 reset to the preset binary 4 value. During ~his 200 ms
window, the up/down counter 100 may either count down to
the value zero or count up to the value 8 depending upon
the difference in frequency of the pulses from ~he input
sensor lines 62 and 64. If a binary 8 count is reached
15 an output pulse is provided along a line 230 from the
up/down counter lO0 to one input of AND ~ates 232. If a 0
count is reached) the output of up/down counter 100 is fed
along a line 234 via inverter 236 to the second input of
AND gate 232. The output of ~ND gate 232 is connected to
20 NOR gate 238, wh:ich provides an output DIFF signal along
line 114. The DIFF signal is high (logical 1~ whenever
the output of the up/down counter 100 reaches either the
binary count 8 or the binary count 0 thereby indicating
a significant difference in rotational speed of the two
25 measured shafts. The high DIFF signal along line 114 is
fed to the lock flip-flop 116 via an inverter 240. Lock
flip-flop 116 comprises cross connected NAND gates 242
and 244, the outyut of NAND gate 242 being fed to inverter/
driver 246. The output of inverter/driver 246 i9 fed along
30 a line 122 to the driver circuitry 120 consisting o~ tran-
sistors 150, 152 and 154. ~ solenoid 71 is powered by tlle
drive circuit 120 as well as the indicator 72 indicating
a locked condition.
The output of NAND gate 242 is also fed to the
35 count enable terminal of co~mter 124. Counter 124 may be
p~eset for a period predeterminedtimeor a fixed timeinter-
val of 7,27 or 435secondsandafter expiration ofthe fixed
timeinterv~lsupplies a clock signalalong lines128 and130
respectively. Counter 124 is set for a fixedtime intervalof
40 435seconds in theembodiment described herein. Line128 i~
cludes an RCtimeconstant255which providesatimedelay of
about one-half second. The signal along line 123 goes
high at the end of the preset time interval as, ~or
example, 435 seconds during which the lock condition is
5maintained. During the preset time interval the lock
condition will be maintained regardless of the value of
the DIFF signal on line 114 since the fli~-flop 116 remains
locked until reset by the delayed time interval signal
along line 128. To this end, the timing si~nal along line
10128, delayed for one-half second by time delay 255, is
connected to one input of ~JAND gate 256 which has its
output feeding an input of NAND gate 242. The second
input of NAND gate 256 is provided by a clock signal
along line 126 coming from oscillator 110. NAND gate 256
15is utilized to prevent any race condition of the lock
flip-flop 116. The output of NAND gate 256 is driven
low upon the simultaneous occurrence of the clock pulse
along line 126 and the delayed time signal derived from
line 198. The low output of NAND gate 256 drives NAND
20gate 242 high which ~orces the inverter/driver 246 low
thus turning off solenoid 71 and indicator 72. Simulta-
neously, the high output o NAND gate 242 resets the
counter 124.
The timing signal along line 130 is the same signal
25as the signal along line 128 but is not subject to delay.
The timing signal along line 130 is fed to NAMD gate 118
and thence to failsafe flip-flop 136 consisting of two
cross connected NAND gates 260 and 262. MAND gate 260
also receives a signal along line 264 from a brake circuit
30270 to be described hereinafter. The output of NAND
gate 260 supplies a signal termed the FS or Eailsafe sig-
nal which is normally low when inoperative and goes to a
high (logical 1~ state during a failsafe mode in which the
circuitry is to be shut down. For example, if the DIFF
35signal along line 114 is still present,(high, logical 1)
at the time the timing signal is generated along line 130
(one-half second before the delayed signal on line 128),
the output of NAN~ gate 260 will go low generating a
logical 0 FS signal. Simultaneously, the output of NAND
40gate 262 is driven lo~ so that FS goes low (logical 0).
-16-
The FS signal from NAND gate 260 is fed to an
input of NAND 226 (FIGURE SA). Gate 226 in turn emits
a signal to ~AND gate 224 which continually presets
up/down counter 100 and thereby disables operation of
5 the control circuit. The signal from gate 262 provides a
low output along line 138 to inverter/driver 274. The
output of inverter/driver 274 feeds the driver circuit 140
which consists of transistors 276, 27~ and 280 similar to
the driver circuit 120. A failsafe indicator 144 is
10 energized when the system is operating in the failsafe
mode.
An additional feature shown in FIGURES SA and 5B
is the incorporatio~ of the brake circuit 270 into the
apparatus of FIGURE ~. Brake circuit 270 detects both the
15 brake on condition and an open circuit condition which may
result, for example, from filament burn out or wire dis-
connections. Line 290 is connected -to the brake circuit
with the vehicle battery and brake lamps. With brakes
applied the voltage on line 290 is normally approximate].y
20 13.6 volts. ~rake circuit 270 comprises resistors R25,
R36, R26, capaci~or C21 and diodes as shown. Further,
vol~age comparators 292 and 294 are provided as well as
inverter 296, AND gates 298 and 300 and NAND gate 302.
Resistors R7, R49 and R8 form a voltage divider .~eeding
25 one input of voltage comparator 294 which has its other
input connected to line 290 via resistor R25. If the brake
switch is actuated, voltage comparator 294 is driven high
at its output at line 304 which feeds inverter 296 driving
same to the low state. Inverter 296 is connec~ed to NOR
30 gate 306 which subsequently ~orces the output oE line 114
low tlogical 0) via the NOR gate 238. As such, by main-
taining DIFF low during actuation of the brake switch, the
lock out circuitry is prevented from being operated.
Inhibition of lock out during braking is desirable to
35 prevent inter-a~le differential lock up resulting from
non-synchronous wheel rotation during braking.
Brake circuit 270 further permits detection o
an open brake circuit by means of voltage comparator 292
-17-
which is held low upon an open brake circuit condition and
normally receives a voltage between one-third and two-thirds
of the regulate~ power supply voltage resulting from the
biasing network of resistors R36, R25 and R26. During an
5 open brake circuit condition, the logical output of voltage
comparator 292 and voltage comparator 294 is fed to AND
gate 298, which subsequently feeds NA~ID gate 302 which in
turn feeds AND gate 300. An output along line 264 is pro-
vided to an input of NAND gate 260 o~ the failsafe flip-~lop
10 136 setting same thereby generating a high failsafe signal
(logical 1). The FS signal continually presets the up/dow~t
counter 100 via NAND gate 226 as heretofore described thus
prohibiting further generation of the DIFF signal along
line 114.
Although both a brake applied or brake switch closed
condition and an open or floating connection to the stop-
light circuit are effective to prevent operation of the
solenoid driver circuit. 120, the open circuit condition
activates the failsafe flip-flop 136 which remains actlvated
20 until manually reset whereas the brake applied condition
merely temporarily inhibits generation of any DIFF signals
along line 114 via the NOR gate 238. In the latter case,
once the brake lights are turned off, the control circuit
becomes effective to operate the solenoid driver circuit 120.
Yet an acLditional feature shown in the circuitry of
FIGURE 5A D is a ~ower up self--test circuit 330 consisti~g of
cross connected NAND gates 332, 334, inverters 336 and 33~
and NAND gate 3~0. The power up self-test circuit further
comprises capacitor Cl~, ~esis~or ~27 and ~ND gate 342
30 FIGURE 5l.~. ~he voltage regulator shown in FI5URE 5C pro-
vides a regulated output voltage, V, of approximately 6
volts. During startup the 6 volt pulse provides a PUP
~power up signal) held for approximately 2 seconds by
means of RC time constant provided by resistor R27 and
35 capacitor Cl0. The power up signal insures a logical 0
signal at the output of N~ND gate 342 which is fed via a
line 344 to NAND gate 332. This signal provides a means
for testing the circuitry upon a power up sequence by pro-
viding TEST and.TEST signals which simulate a sensor input
-18-
by providing simulated counts utilizing NAND gates 380 and
382. A D coded signal is also provided by the four bit
binary counter 212 which is fed to one input of NAND gate
380. Consequently, after the vehicle ignition is turned
5 on and the voltage regulator stabilizes, pulses are provided
at the output of NAND gate 384 which feeds the D flip-~lop
190 generating simulated counts which are sampled by means
of the sampling oscillator 210 and binary counter 212.
The gated trigger circuit 90 does not, however, receive any
10 simulated counts and therefore a DIFF signal is generated
along line 114. The DIFF signal is fed to NAND gate 340
along with the TEST signal which resets the power up sel-
test flip-flop 330 (set by the PWR RST signal) and likewise
resets the failsafe flip-~lop 136. The failsafe indicator
15 144 will nevertheless be energized ~or approximately 2
seconds which is the time frame during which the power re-
start (~WR RST) signal is present. After the PWR RST signal
goes to 0 the failsafe indicator will no longerbeenergized
unless a malfunction is detected in the circuitr~. The
20 output of NAND gate 342 also serves as a power reset tPWR
RST) and is utilized with the P~P signal as a signal to
NAND gates 210, 242, 332 and 300 to reset the counters and
flip-flops assoc:iated with those NAND gates. Thus, power
up sequence provldes initialization of the system as well as
25 positive indication that -the failsafe indicator and the
electronic components of the control circuit are working
properly.
-19-
Integrated circuit components which may be utilized
in the circuitry shown in FIGURES 5A and 5B are set
forth by way of example in the following table:
Reference Nos. Part ~llo
82, 180, 292, 294 LM 2901
190 CD 4013
196, 210 CD 4093
192 CD 4082
194 CD 4007
100, 112, 212 F 4029
202, 236 336, 338, CD 4049
240, 246 274, 296
110 LM 555
242, 260, 340 CD 4023
118, 224, 226, 244, CD 4011
256, 262, 302, 332,
33~, 380, 382, 384
124 CD 4040
200, 238, 306 CD 4001
232, 298, 300 CD 4081
-20-
Representative values of the circuit components
utilized in FIGURES 5A and 5B are set forth by way of
illustration and example in the following table:
TABLE
5 Element Value Element Value
Rl lOK R22 470
P~2 lOK R23 470
R3a ~ R25 1.3K
R3b * R26 lOK
R4 lOK R27 58K
R5 1.5K R28 20
R6 160K R29 300
R7 4.7K R31 150
R8 4.7K R32 220
R9 1.5K R34 180
R10 27K R35 220
Rll lOK R36 7.5K
R12 lOK R39 8.2K
R13 lOK R40 4.7K
R14a * R41 lK
R15 lOK R42 8.2K
R16 1.5K R43 4.7K
R17 160K R44 lK
R18 1.5K R49 4.7K
R19 lOK R50 3K
R20a * R51 3K
R20b * R52 lOK
R21a * R60 47
R21b * R61 150K
* Selected for desired ~utput.
-21-
Element Value Element Value
R62 6.2 D20 MZP4746
Cl l50pf D21 lN5395
C2 .Oluf Ll 2.2uh
5 C3 150pf
C4 lOuf
C~ 150pf
C6 .Oluf
C7 .04~
10 C8 lOuf
C10 47uf
Cll .Oluf
C12 .OOluf
C13 lOuf
lS C14 lOuf
C15-C21 .OOluf
C22 .001
C50 .luf
C51 2.2uf
20 C60 lOOOpf
Dl lN5221
D4 lN5221
D6 lN4001
D7 lN4734a
D8 lN5395
D9 lN4736
D10 lN4755
Dll lN4004
D12 lN4002
D13 lN4755
D14 lN4004
D15 MZP4746
D16 lN4001
-22-
The invention may also be embodied in other specific
forms without departing from the spirit or essential charac-
teristics thereof. The foregoing description is therefore
to be considered as illustrative and not restrictive, the
5 scope of the invention being defined by the appended claims
and all changes which come within the meaning and equival-
ency.of the claims are therefore intended to be embraced
thereby.
