Note: Descriptions are shown in the official language in which they were submitted.
BACKGROUND OF THE INVENTION
__ _
Thi~ invention relates in gen~ral to means for
varying the speed of an AC (alternating current) motor,
and in particular to means for varying the frequency and
amplitude of the power supplied l:o the motor.
Lar~e volume submersible pumps typically are located
thousands of feet into a well. The pump assembly includes
a centrifugal pump which is driven by an AC motor mounted
below it. The motors may range :Erom 15 to 750 horsepower,
thus require a large supply of power. Normally, 60 cycle,
thxee phase power is ~upplied, with voltage phase-to-phase
being 480 volts or more. Common rotational speeds of the
motor are about 3500 rpm (revolutions per minute).
Most of these types of pumps are ~ingle speed pumps.
Because of different viscosities, densities, well flowing
characteristics and the lik~, it would be desirable to
vary the spePd of ~he m~tor.
One way in which to vary the speed is to vary the
fr~quency of the power beiny supplied. Normally, the line
power comes from a utility company, and cannot be changed
from the standard 60 cycle per se~ond. There are ci~cuits
that will convert the standard fre~uency to different
frequencies. These circuits also change the amplitude in
proportion to the frequency change for efficient operation
o~ the mo~or. In the past~ SCR circuitry ~silicon
controlled rectifier) has been used. One disadvantage of
an SCR is that it will not ~witch off until the current
drops to zero. This requires complex commutating
circuitry, making these control systems expensive~
r~,
Sl)~ ARY OE' Tl~ INVI~NT-I:ON
The con~rol c:ircuit o~: this inven-tion first uses a
rectif.ie:r to convert the ~C t:hree phase power .supply into
a DC (direct current) voltacJe, A FET (field efect
transistor) .i5 connected betweerl the negativ2 rail ancl one
of the power conductor~ lcading to the motor fol- each of
the three phases. Similarly, t,hree FET switches connect
the posi.tive rail'to each of the three power conduc~orsJ.
These F~T sw.itches are ~witched on and off to produce a
desirecl alternat.inc~ cuxrent wave~orm o~ a selectc(l
frequ~,ncy. Means are also employed to vary the amplitude
in propc~rtion to the ~requency selected.
To accomplish ~hese functions, a variable fre~uerlcy
~S oscil].ator .is employed to provide pulses of frequency
depending on ~he input selected. A binary counter counts
these pulses up to a certain number, th~n xepeats. For
each count, the coun~er provides a binary output. A ROM
(read only memory) receives the binary outputs and
provides a proc~rammed output for each of the FET switches
to control the switching as determined by the frequency of
the oscillator.
In the preferred embodiment, the ROM is proyrammed to
provide a ~eries of pulses of widths that have been
sel.ected to synthesize a sine wave. Consequently, during
one. half of a sine wave period, either the negative or the
positi.ve FET switch for that particular phase wi.ll be
switched on and off numerous times and with various
durations to synthesize one half of a sine wave. Thes~
pulses are averaged by an integrating circuit comprisinc~
; an incluctor and capacitor to provide a smooth waveform to
the motor.
In the preferred embodiment, the oscillator provides
a trian~ular wave of the same Erequency as the puls~es that
drive the coun-ter. Thi.s triangular wave is compared to a
DC level that is proportional to the input to the
i
t~,J
oscillator. The difference between the DC level and
triangular wave results in uniform pulses of widths in
proportion to the frequency selected. In the preferred
embodiment, these pulses enable the computer to provide
its output pulses and determine the duty cycle of each
output pulse. At the highest f:requency, the ROM is
fully enabled, and the series of pulses are at their
maximum widths. At one half the maximum frequency, the
enabling pulses will be one half their width, and will cut
in half the width of each pulse in the sine wav0 series,
thus reducing the total amplitude in proportion to the
frequency ~elected.
In an al~ernate embQdiment, the enabling pul~es vary
the DC rail voltage, rather than enable the computer. In
another alternate embod;ment, rather than a series of
pulses of differing widths for synthesizing a sine wave,
each F~T switch is lef~ on for the full period, thus
providing a square wave to the motor. The amplitude of
the square wave i~ varied by varying of the DC rail
voltage with the enabling pulses.
'7
-4a-
According to a broad aspect, the invention relates
to means for varying the speed of a motor powered through
power conductors by a three phase ~C power source, comprising
in combination: rectifying means for converting the AC vol.tage
supplied by the power source to positive DC voltage on a
positive rail and negative DC voltage on a negative rail;
three positive switches, each connecting the positive rail
to one of the power conductors; three negative switches, each
connecting the negative rail to one of the power conductors;
oscillator means for supplying pulses of frequency which can
be varied to select a desired motor speed; counter means
for repeatedly counting the pulses to a selected number and
providing a binary output for each pulse counted; a read only
memory ~mit havin~ six output gates, each of which is
connected to and directly controls only one of the switches,
the memary unit being connected to the binary outputs of the
counter means and being programmed to provide simultaneously
for each binary output received an output at each gate that
determines entirely the state of each switch in a full three
phase waveform; and means for varying the amplitude of the
waveform produced in propo.rtion to the requency selected.
-4b-
According to a further broad aspect, the invention
relates to means for varyiny the speed of a motor powered
by a three phase AC power source, comprising in combination:
rectifier means for coverting AC voltage supplied by the
power source to positive DC voltage on a positive rail
and negative DC voltage on a negative rail; a pair of
swi.tches for each phase, one connecting the positive rail
to a power conductor to the motor, the other connecting the
negati.ve rail to the power conductor; oscillator means for
supplying pulses of a frequency which can be varied by chang-
ing the level of a DC input and or supplying a triangular
wave; counter means for repeatedly counting the pulses to
a selected number and providing a binary output for each
pulse counted; differential amplifier means for comparing
a triangular wave with a DC level proportional to the DC
input applied to the oscillator means, and for producing
enabling pulses of widths equal to the width of the
triangular wave that exceeds the DC level; a read only
memory unit haying six output gates, each of which is
connected to and directly controls only one of the switches,
the memory unit being connected to the binary outputs of
the counter means and being programmed to provide simultaneously
for each binary output received an output at each gate that -
determines entirely the state of each switch in a full three
phase waveform; the-mamory unit being enabled by the
enabling pulses to produce a pulse only during the width
of each enabling pulse; and integration means between the
switches and the motor for inteyrating the pulses created
by the opening and closing of the switches to produce a
.smooth waveform.
,. ~.
, .,
'7
--~c--
According to a further broad aspect, the invention
relates to means for varying the speed of a motor powered
through power conductors by an AC power source, compri.sing
in combination: rectifying means for converting AC voltage
supplied by the power source to DC voltage with a negative
rail and a positive rail; frequency switch means having a
negative and a positive switch connecting the negative rail
and the positive rail, respectively~ with each conductor,
for alternately supplying negative and positive voltage to
the motor; oscillator means for supplying pulses of frequency
which can be varied to select a desired motor speed; counter
means ~or repeatedly counting the puIses to a selected
number and providing a binary output for each pulse counted;
a read only memory unit having six output gates, each of which
is connected to and directly controls only one of the switches,
the memory unit being connected to the blnary outputs of the
counter means and being programmed to provide simultaneously
for each binary output received an output at each gate that
determines entirely the state of each switch in a full three
phase waveform; amplitude switch means connected into one of
the rails for switching on and o~f the DC voltage; and
pulse width means for providing amplitude pulses of duration
proportional to the frequency of the oscillator means and
for actuating the amplitude means with the amplitude pulses
to vary the DC potential between the rails.
'7~
~ RAWINGS
Fig. 1 represents the positive half of a sine wave.
~ig. 2 portrays schematically a series of pulses for
synthesizing the sine wave o Fig. 1.
Fig. 3 illustrates a three phase AC current supply.
Fig. 4 illustra~es schemati.cally a series of pulses
for each phase for synthesizing the three phase supply of
Fig. 3O
Fia. 5 lllus~rates schematically the data output of
the ROM used with this ~nvention for ~ach binary input.
Fig~ 6 is a block diayram i.llu~tra~ing one em~od.iment
of this invention.
Fig. 7 is a electrical ~chematic illu~trating part of
the circuitry of the embodiment of Fig. 6.
Fig. 8 represents a continuation of the elec~ricai
schematic of FigO 7, illustrating ano her part of ~he
circuitry of the embodiment of Fig. 6.
Fig. 9 is another block diagram furth~r illustrating
part of the embodiment of ~ig. 6.
~ ig. 10 is a block diagram illus~ra~ing another
embodiment of ~he invention.
Fig. 11 schematically illustrates the enabling
pulses for the memory unit.
DESC~IPT:~ON OF' TI~E PF~EFER~EI) EMBODIMENT
.Re~errinc3 to Etig. 3/ power normally avallabl.e at ~
well si.te .is a three phase s.inusoidal waveform, compris1ncJ
Phase ~, Phase B & Phase ~, as indica~ed. Each phase
alternates between posi~lve and negat:ive in a sine wave.
Phase B is shown la~gin~J Phase A by 120 and leading Phase
C by 120.
Wav~form 11 oE Fi~3. 1 i5 one half cycle oE one si.ne
wave of r~lig. 3. The area under wave~orm 11 at each
particular pOi~lt can be synthesized by the area under the
series 13 of pulses shown in F:ig. 2. The widths of the
pulses are var.ied to provide the s~me area uncle.r wavefc~rm
11 at any p~rticular point. 5witching on an~ off a DC
level to provide series 13 will synthesize a simulation of
waveform 11.
As shown in Fig~ 4I the positive half of Phase A can
be synthesized by repeating the same series 13 of pulses
as shown in Fiy. 2/ with an equal space betweerl eacll
series~ The neyative half of Phase ~ will have an
identical series 13 of pulses when -the positive half of
Phasc A is o~'L~ Phases B and C are synthes.ized similarly.
The series 13 of pulses in Phase A lags those in Phase B
by 120. The series 13 o:f pul~es of Phase C lags the
series o~ Phase B by 1~0. To increase the Ere~uency,
each series 13 is repeated at more frequent int~rvals.
Each pulse in the series will be the same relative width
to other pulses in the series regardless oE the ~requency.
In the preferred embodiment, khe ampli.tude is varied
in proportion to the change in ~r~quency by proportionally
changin~ the widths oE each of the pulses in each series
13. ~t maximum fre~uency, all ~h~ pulses will be at their
maximum widthsa At one-half the maximum frequenc~, all of
the pulses will reduced by one-half their widths. 7rhe off
3S period between pulses doubles. This result~, in a
reduction of the duty cycle, which is the cumulative
amount that the pulses are on durin~ one-half of a sine
t~
wave. Cutting the duty cycle re~uces the total am~litude
o~ the waveform 11 by t~le same Eactor. That is, if the
pulses are cut in ha]f for one half rnaximum frequency, -the
RMS (room mean square) amplitude of the w~veform l] will
be one half the maximum.
Fig, 5 illustrates how -the pulses L3 are. generated.
Each of ~he six da~a outputs is connected to a negative or
positive switch for supplyin~ the motor power conductors
with either negative or positive ~C vo:ltac~e. Memory
outputs 0 and 1 represent the positive and negative
portions of Phase A~ Memory outputs 2 and 3 represent tlle
positive and negative portion~; of Phase B, and memory
outputs 4 and S represent the positive and negative
portion~ o~ Phase C. On the left, the numbers 0 to ~55
represent counts by a binary counter of pulses generated
by a variable frequency oscillator. The 25S counts
repre~ent a full sine wave, 0 to 2 ~ . At each pulse, the
counter will provide a binary number. For example, at the
number 10 pulse, the counter will provide an eight bit
binary number of 00001010. Each of these eight bits will
address one of the eight gates (0 to 7) of the memory
unit.
The memory unit, depending upon the 0 or 1 received,
will provid~ a programmed output, which will be either a 0
or 1. For example, at the number 10, the data output on
line 0, which is positive Phase A, could be either a 0 or
1 since it is in a data position or in the middle of
providing a series 13 (Fiy. 4) of pulses. The negative
half of Phase A will be off at this point. The positive
half of Phase B will be off. The negative half of Phase B
will be on and could be either a 0 or 1 depending upon
what point within a group of series 13 that the numeral 10
provides. The positive half o Phase C will be either 0
or 1, and the negative half of Phase C will ~e o~f. In
this manner~ six switc~es can convert DC into the three
phase signal similar to Fig. 3.
The overall block diagram for one embodiment is shown
in Fig. ~. The three phase power supply 15 is normally
the power received from the util-ty company, after
txansforming to the proper voltage, which is likely t~ be
les~ ~han or equal to 480 volts AC phase-to-phase~ Thi~
three phase power ~upply is rec:tifi~d by rectifiers and.
filters 17 into a po~i~ive DC Yoltage on rail or line 19
and a negative DC voltage on negative rail 21. The FET
switches 23 are altern~tely switched, as explained in
connection with Figs. 1-5, to provide the ~eries 13 (Fig.
4) of pulses to a power integra1:or 25. Power integrator
intPgrates the pulses, averaging and smoothing them
into an approximat~ waveform of that ~hown in Fig. 3. The
three phase power is suppli~d through three powPr
conductors 27 to a motor 29. Motor 29 is a ~hree phase
squirrel cage induction type motor~
The control circuitry for tAe FET switches 23
includes a ~peed con.rol selector 31, ~hown to be a
potentiometer, which provides varying voltage to a signal
conditioner 33. The signal conditioner ~upplies a DC
voltage to a voltage controlled oscillator 35. Oscillator
35 pr~vides a square pulse output to an inverter buffer
37, which in turn provides ~he pulses for counting to a
binaxy counter 39. Cou~ter 39 coun~s the pulses ~rom 0 to
255, then repeats. For each count, it provldes an eight
bit binary number t~ a programmable ROM 41. The ROM 41
provides 0 and 1 outputs on six lines~ representing a
programmed outputfor the particular pulse counted, to
interface circuits 43. The interface circuits 43 provide
a barrier between ROM 41 and FET ~witches 23, and also
control FET switches 23.
To vary the ~mplitude in proportion to the ~requency~
the oscil}ator 35 al50 provides a triangular wave to a
comparator 45. The triangular wave is of the same
frequency as the square wave output from oscill~tor 35.
Comparator 45 compares this triangu~ar waYe to a level DC
input fxom the signal conditionex 33. Enabling pulses are
~ . . .
provided to the ROM 41 that have widths equal to the
portion of the triangulax wave that is at a greater level
than the DC level provided by signal conditioner 33.
These enabliny pulses are at the same frequency as the
output pulses of the ROM 41, but have a duration or width
that is proportional to the frequency.
The enabling pulses will enable ~he ROM 41 to provide
a pulse for a series 13 ~Fig. 4) only for the duration of
the enablillg pulse. If the DC signal Erom ~he signal
conditioner 33 is at its lowest poin~, then enabliny
pulses are p~oduced that are the full widths o the pulses
from counter 39 and the ROM 41 will be enabled to produce
full width pulses for series 13 (Fig. 4), resulting ir.
maximum amplitude. Correspondingly, if the DC level from
lS signal sonditioner 33 is at one half its maximum, then the
enabling pulses provided to ROM 41 will be only one-half
the widths of the pulses from counter 39, and will enable
the ROM 41 to provide only output puls~s for series 13
(Fig. 4) of one half the full width. Comparator 45 al50
receives an input from a voltage regulation circuit 47
that senses voltage fxom the three power conductors 27.
Voltage regulation circuit 47 will modify the enabling
pulses from comparator 45 if the ~in~l output amplitude
has varied from that selected by speed control 31.
Fig. 7 illustrate~ more details of the embodiment of
Fig. 6. The speed control selector 31 (Fig. 6) includes a
resistor ~9 supplied with a source 51 of DC power. A
zener diode 53 is connected between resistor 49 and ground
for regulatin~ the DC supply~ A potentiometer 55 has one
side connected batween diode 53 and resistor 49 and the
other side to ground. The wiper of potentiometer 55 is
connected to the positive input of a differential
ampli~ier 57, the input also being connected through a
capacitor 59 to ground~ ~mplifier 57 providPs gain
control or level shifting for the DC input pro~ided by
potentiometer 55. This signal conditioner 33 portion of
the circuit also includes a resistor 61 at the output of
amplifier 57, which leads to the negative input of a~other
amplifier 63. Ampli~ier 63 includes a trim resistor 6S
connected in a line from its output to its negative input..
The positive input of amplifier 63 is connec~ed to a
potentiometer 67, which is ~upplied with DC power.
The OUtpllt O~ amplifier 63 leads to pin 5 of
osclllator 35 through a resistor 69. Oscillator 35 is a
conventional voltage controlled oscillator that is
connected in a normal manner. Pin 7 is connected through
a resistor 71 to ground, while pin 1 is grounded. Pin 8
i9 connected through a re,sistor 73 to pin 5. Pi.n 6 is
connected through a resistox 75 to pin 8. Pin 6 is also
connected through a capacitor 77 to pin 5.
Pin 3 of oscillator 35 provides a squar~ wave 78
(Fig. 11) that depends upon the setting of potentiometer
55. Square wave 78 passes through a capacitor 79 to the
base of a transistor 81. The emitter of transistor 81 is
connected to ground, and the base of transistor 81 is
connected ~o ground through resistor 83~ The collec~or is
connectad to a DC power supply through a resistor 85. The
square wave 78 (Fiy. 11) from pin 3 will be amplified by
transistor 31 and produced on line 87 leading from its
collector. ~ine 87 leads to the ~inary counter 35, shown
in Figs. 6 and 8.
Oscillator 35 provides a triangular wave 88 (Fig. 11)
on pin 4 with a frequency the same as square wave 78 (Fi~.
113. Triangular wave 88 proceeds through a capacitor 89
to an amplifier 91. A diode 93 i5 connected from the
output of amplifier 91 to its negativ~ input. The
positive input of amplifi~r 91 is ~rounded. The output of
amplifier 91 leads to the positiYe input of a diferential
amplifier 95. The positive input of amplifier 95 is also
~rounded through a resistor 97.
The negative input of amplifier 95 receives~l level
DC that is proportiona]. to the setting of ~oten.tiometer
55. This level DC proceeds throu~h various stages in gain
control circuitry that inGludes a potentiometer ~9
11
connected to the output o:E amplifier 57. The wiper of
pot:enti.ometer 99 is connected through a resistor 101 to an
amplifier lQ3. The amplifier 103 is connected to the
nega~lve input of the ~omparator amplifier 95. Further
S conditioni~g for the level sicJnal includes an ampliEier
105 that has its negative input connected through a
resistor 107 to the wiper of potentiometer 99. The
negative input of amplifier 105 is connected to the output
of amplifier 105 throuyh resi,stor 109. The output of
~mplifier of 105 is connected through a diode 111 ancl a
resistor 113 to the negative input of amplifie~ 63. The
positive input of amplifier 103 is also grounded through a
resistor 115. The negative input to amplifier 103 and the
positive input to ampli~'ier 105 are connected into voltage
regulation circuitry 47, to be described subsequently.
The triangular wave 88 (Fig. 11) from pin 4 o~'
oscillator 35 is thus supplied to the positive input of
amplifier 95, while the negative input of amplifier 95
receives a level DC voltage depending upon the setting of
potentiometer 55. The output waveform 125 on line 117
from diferential amplifier 95 is shown in Fig. 11~ The
dotted line 123 represents a selected DC level that is
applied to th~ negative input of amplifier 95. The
resultiny output of square enabling pulses 125 have a
width that is the same as the exce~s amplitude of the
trianyular wave 88 over the DC level 123. Enabling pulses
125 will be at the same frequency as the square pulses 78
supplied to counter 39 (Fig. 6 and 8), but will have
vhriable pul e widths. At maximum frequency, the DC level
123 will be at its lowest point, providing pulses 125 that
have widths equal to the spaces between each pulse 125 and
equal to the widths of the square wave pulses 78. At
one-half the maximum frequency, the DC level 123 will be
higher, providing pulses 125 that have widths equal to 35 one-half the clistance between each pulse 125 and o,ne-half
the width of pulses 78.
7~'7
:1~
Referrlng to ~ig. 8, line 87 from Fig. 7 transmits
the squa.re pulse output 78 (Fig. 11) and leads to counter
39. Line 117 transmits the Pnabling pulses 125 (Fig. 11)
and leads to ROM 41. Counter 39 is supplied with power
and provides the eight bit binary number to ROM 41. ROM
41 has six data outputs, each of which is connected to an
amplifier 127 for shaping purposes. Each ampli~ier 127 i~
provided with a s.ource of DC power at its input through a
resistor 1~9~
Each amplifier 127 provides the data outputs of ~eros
and ones to an inter~ace circuit 130, only one of which is
~hown, the other 5iX interface circuits 130 being
identical. Interface circuit 130 contains a coIIventional
optical isolator 131 that is connected to the output of
amplifier 1~7 by means of a resistor 133. Optical
isolator 131 has a light emitting diode 135 con~cted to a
source of DC power~ Pulses cause the diode 135 to conduct
and emit light for reception by a photo transistor 137.
The base of transistor 137 will conduct upon rec~ption of
light from diode 135, thus isolating diode 135 from the
higher powex necessary for controlling the FET switches 23
(Fiy~ 6). -
The remaining portivns of the interface circuit 130are of conventional nature an~ include a Schmidt krigger
139 connected to the emitter of transistor 137. A
capacitor 141 is also connected to the input of Schmidt
trigger 139. A resistor 143 is connected in paxallel with
capacitor 1410 The input of Schmidt trigger 139 also is
connected to a resistor 145 which leads to a line 147.
The output o~ Schmidt trigger 139 is comlected to the
bases of a pair o~ txansistors 149 and 151 through a
xesistor 153. The bases of the transistors 149 and 151
axe also connected ~o line 147 ~hrough capacitor 155~ The
emitter of transistor 151 is connected ~o the collector of
transistox 149, both of which are connected to a line 157.
The emitter of transistor 149 is onnected to line 147.
r~;~ t~ I
13
The photo transistor 137 has its collector connected
to the collector of transis~or 151 for receiving DC
voltage. The collectors of transistors 137 and 151 are
connected through a zener diode 159 and capacitor 161 to
line 147. The collectors of ~ransistors 137 and 151 are
also connected to a line 163 through resistors 165 and 16?
connected in series. A capacitor 169 lead~s Erom the
junction of the two resistor 5 165 and 167 to the
collectors of tran~istors 137, 151~
The interEace circuits 130 receive pulses through
ampllfiers 127, which puls~ khe l.ight emitting diode 135,
causiny transistor 137 to concluct, operating the Schmidt
trigger 139. Pulses axe produced on line 157 for
controlling the F~T switches 23 ~Fig. 6). A potential
will exist between lines 163 and 147.
Re~erring to Fig. 9, each interface circuit 130 is
shown with its output 157 leading to the gate of a FET
switch 171. There are six FET switches 171, two for each
of the khree phases. Each of the positive FET switches
171 has its drain conn~cted to the positive DC rail 19.
Each of the negative FET switches has its source connected
to the negativ~ DC rail 21. The sources of the positive
FET switches 171 are ~onnected to the drains of the
negative FET switche~ 171. The common connection of the
positive and negative FET switches 171 ~or Phase A is
connected to a line 173, for Phase B to a line 17S, and
Phase C to a line 177. One or more resistors ~nd
capacitors are connected betwPen the rails 19, 21 for
filtering, such as resistor 179, and capacitor 181.
Each output line 173, 175, and 177 has an inductor
183 connected into the line between it and motox 29. Each
output line has a capacitor 185 with one lead connected to
the negative rail 21 and the other lead connected one of
the output lines between inductor 183 and motor 29. Each
interface circuit 130 has its lines 147 and 163 connected
across the source and drain of one of the FET switches
171. A zener diode 187 is connected across lines 147 and
157 of each interface ~ircuit 130. Block 188 provides
wave data and amplitudc control to the lnterface circuits
and represents the circuitry of Figs. 7 and 8.
In operation, the AC three phase power is rectified
by rectiier 17 into positive voltaye on rail 19 and
negative on rail 21. Referring also to Fig. 7 and 8,
setting potentiometer 55 controls the frequency of
oscillator 35, which provides pulses to counter 39.
Counter 39 address ROM 41 which provides a series 13 (Fig.
4) of pulses to each interface circuit 130. The "on"
duration within each .series 13 is controlled by enabling
pulses received in ROM ~1 ~rom comparator amplifier gs.
Each interface circuit 130 switches on and off its FET
switch 171 with a series 13 (Fig . 4 ) of pulses .
When a FET switch 171 is provided with a series 13 of
pulses, i~ will con.nect the respeckive positive or
negative rails, 19 and 21, to the outpUt lines 173, 175
and 177 leading to the motor~ For example, if FET switch
171 ~or Phase A i~ being provided wi~h puls~S o~ varying
width, it will pulse as shown in Fig. 4 J each pulse
sending posi~ive DC vol~aye ~hrough DC rail 1~ to output
line 173. Thase pulses will be integrated by the~ power
inteyrator comprising inductor 183 and capaci~or 185.
This averages and smoothes the pulsated s~ries into a
synthesized sine wave for driving the motor ~9. While the
FET switch 171 for the positive Phase A is pulsin~, the
FET switch 171 for the negative side of Phase A will.be
off.
Additional circultry for monitoring the output and
protectiny against overload is shown in Fig. 7. The
voltage regulation circuit 47 aSsUr~s that khe ac~ual
amplitude on power lines 27 is the proper selected
amplitude. A pair of resistors 189 and 191 are connected
to two of the power conductors 27 leading to mo~or 290
Resistors 189 and 191 lead to the inputs of an amplifier
193 for amplifying the AC between two of the phases. A
resistor 195 leads from the output of amplifier 193 to its
t~
negative input. The positive input also is connected to
ground through a resistor 197. The output of amplifier
193 is connected to a potentiometer 199, the wiper which
leads to the negative input of an amplifier 201.
Amplifier 201 has its positive input grounded and its
output connected to a diode 203. Diode 203 is connected
to the positive input of an amplifier 205. The positive
input of amplifier 205 is also connected to the negative
input o~ ampliflex 201. The output of amplifier 205 i5
connected to the negative input o~ amplifier 103 through
resistors 207 and 209. The negative input o~ amplifier
103 is connected to the positive input of amplifier 105
through resistor 209 and a resistor 211. The positive
input of ampliEier 105 is grounded through a resis~or 213.
The negative input of amplifier 103 is grounded through a
resistor 215 and capacitor 217 connected in series. The
junction of resistor 215 and capacitor 217 is also
connected to the output of amplifier 103.
The differential amplifier 193 senses the magnitude
of the vol~age between two of the phases a~ line 27, drops
the voltager amplifies and rectifies the signal for
application to amplifier 103. Amplifier 1~3, as
previously explained, provides the DC level to the
comparator amplifier 95. The DC level provided at th~
output o ampli~ier 205 to amplifier 103 shifts the DC
level if the actual output has not been properly
proportioned to the frequency selected.
Ano~her portion of th~ circuit shown in Fig. 7 is a
protection for overload. This portion of the circuitry i5
conventional and includes three lines 219, each of which
i~ conn~cted through a current transformer (not shown) to
one of the power condu~tors 27 for monitoring current.
Lines 219 lead to a rectifier comprising diodes 221 which
provide positive and negative voltages filtered by a
resistor ~23 and capacitor 225 connected in parallel
between the output lines 227 and 229. The DC voltage on
lines 227 and 229 is compared with a preset DC voltage at
7~'7
16
the differen~lal ampliier 231. The preset DC voltage i5
supplied through a potentiometer 233. The output from
amplifier 231 proceeds through a resistor 235 to an
amplifier 237. The positive input of amplifier 237 i5
connected to the output of amplifier 205 through a
resistor 239. A capacitor 2~1 has one slde connected
between resistors 207 to 209 and the other to ground. The
connection between resistors 207 and 239 also leads to the
negative input o amplifler 103 through resistor 209.
Amplifier 205 has its output conneated through resistors
243 and 245 to ground~ The neyative input of amplifier
205 is connected to the junction o~ resistors 243 and 245.
~ Amplifier 237 provides an output throuqh a diode 247
to a relay 24~. Relay 249 has its contacts 251 connected
into a line 250 for interrupking the power being supplied
to the conductors 27 iE the relay ~49 i-q deenergiæed. The
output lin~, of amplifier 237 is also connected through a
capacitor 253 to ~he negative input of amplifier 231.
In the operation of the overloa~ protection, current
20 i5 monitored through the lines 21~, then rectified by
diodes 2210 If the current exceeds a preset amount
through potentiometer 233, amplifier 231 will pro~ide a
positive output to the negative texminal of amplifier 237.
A positive input at the negative terminal of amplifier 237
causes a negative output, which deenergizes coil 249,
opening switch 251 to stop power to the motor.
Fig. 10 discloses an alternate embodiment to the
system shown in Fig. 9. Prime symbols will be used to
indicate components in the circuit of Fig. 10 that are the
same as in Fig~ 9. As in ~ig. 9, a rectifier 17'
rectifies the three phase pow2r supply from the utility
transformer. This current is rectified into a positive DC
voltage on rail 19' and a negative DC voltage on rail ~1'.
Resistor 179' and capacitor 181' provide filtering. ~n
interface circuit 130' exlsts for each of the FET switches
171'.
17
In this second embodiment, the wave data block 254
may have the same compon~nts as the circuit of Figs. 7 and
8. Rather than providing a series 13 (Fig. 4) of pulses
of varying width to synthesize a sine wave, however, the
ROM 41 ~Fig. 8) is pro~rammed to open and close each FET
switch a single t.ime for each half cycle of a sine waYe.
This provides a six step square wave output on lines 173',
175' and 177l to motor 29'. Since each FET switch 171'
remains on or off for a full halE cycle, the integr~tion
means comprising inductor 183 and capacitor 185 oE Fig. g
is not requir0d between the motor 29' and FET switches
171. The frequehcy supplied to the motor 29' will, as in
the ~irst embocliment, b~ determined by the oscillator 35
(Flg. 7)~ which opexates in the same manner. The counter
3~ (Fig. 8) will also operate in the same manner. In the
second embodiment, ROM 41 (Fig. 8) is always ~ully e~abled
and does not receive enabling pulses 125 ~Fig. 11) on line
117.
In th~ second embodiment, to vary the ampl:itude in
proportion to the fr~quency, an amplitude switch 255 is
placed in one o the rails, such as the positive rail 19l.
Amplitude switch 255 i~ switched on and off to pro~ide a
square wave output, with the widths of the pulses being
variable with respect to the distance between pulses,
similar to the enabling pulse wave~orm 125 o~ Fig. 11. An
inductor 257 is conr~ected into positive rail 19'. A
capacitox 2s9 is connectPd between rail 1~' and rail 21'.
A diode 261 is connected betweerl the rails 19~ and 21'.
Inductor 257 and capacitox 25~ integrate the square wave
provided by the amplitllde switch 255 to provide a variable
DC voltage between the rails 19' and 21'. The difference
in poten~ial depends upon the on duration of the amplitude
switch 255 with respect to the off duration.
Amplitude switch 255 is controlled to v~ry the
amplitude of the DC xail woltage in proportion to the
frequency selected by a pulse width control circuit 263.
The pulse width control circuit 263 is the same portion of
'7
1~ ~
the circuit shown in Fig. 7 that provides enabling pulses
12S (Fig. 11) on line 117 -to the ROM 41 shown in Fig. 8.
Referriny to Fig 7, as previously explained, the
triangular wave 88 (Fig. 11) is generated on pin 4 of
oscillator 35. Triangular wave 88 is then compared to a
~C level 123 (Fig. 11) that is supplied through
potentiometer 5S and various level shifting circuitry to
amplifier 95. The portion of t.he triangular wave 88 that
exceeds the DC level 123 in ampli-tude provides a square
pulse 125 (Fig. 11), ~he width of which is less khan the
width between the pulses for less than the maximum
frequency. In the first embodiment, thase ~quare pulses
125 are provided to the ROM 41 for ~nabling. In the
second embodiment, the same pulses 125 are provided ~o the
amplitude switch 255 (Fig. 10) for reducing the magnitude
of the DC rail voltage in proportion to the frequency
selected.
In the first embodiment (Figs.6-9), a synthesized
sine wave is generated by varying the widths of the pulses
in series 13 (Fig. 4). The amplitude is varied by
enabling the ROM 41 to provide pulses for seri.e~ 13 of
widths in proportion to the frequency selected, thereby
reduciny the amplitude for frequencies less than maximum
frequency. In the second embodiment ~Fig. 10), a squAre
wave is provided by closlng each FET switch 171' open or
the full half of each period. Amplitude is varied by
varying the rail voltage through the same enabling pulses
that were previously used to enable the ROM 41.
These two embodiments can be combined into third and
fourth embodiments. In the third embodiment, pulses are
provided for synthesizing a sine wave as in Fig. 9.
Rather than using the enabling pulses to enable the memory
unit, the enabling pulses are provided to the amplitude
switch 255. This system would appear as shown in Fig. 10,
b~t would require the addition of the power integrating
circuit for each conductor. The dotted lines indica~e the
inductor 1~3' and capacitor 185' required for integrating
_____
19
the pulses produced during each period by the FET swi~ches
171'. Inductor 183' ~nd c~pacitor 185' are shown only for
the Phase A conductor 173', however, similar inductors and
capacitors would be required for each phase, as indicated
in Fig. 9~
In the fourth embodiment, ROM 41 (Fiy. 8) is
proqrammed to provide the series 13 pulses of Fiy. 4 at a
certain frequency range in which a sine wave more
efEicienkly operates the motor. At higher frequencies,
where a square wave may he more eEficient, the ROM
provides square pulses, each of duration equal t~ one halE
of a cycle. In both of these cases, the amplitude would
be varied by using the amplitude switch 255 and pulse
width control circuit 263 as shown in Fig. 10. This
fourth embodiment is also illustrated by Fi~. 10.
In this invention, the rectifier 17 serves as
rectifying means for converting the AC voltage supplied by
the power source to DC voltage. The FET switches 171
serve as switch means for alternately providing negative
and p~itive DC voltage to the power conductor.
Oscillator 35 serves as oscillator means for supplying
pulses of frequency which can be varied to se}ect a
desired motor speed. Counter 39 serv~s as counter means
for repeatedly countiny the pulses to a selected number
and providing a binary output for each pulse counted. ROM
41 serves as memory means for providing a programmed
output to the FET switches 171 for each binary output
received~ In the first em~odiment selectively enabling
ROM 41 provides means for varying the amplitude o the
waveform in pxoportion to the frequency.
The pulse width control circuit 263 and the amplitude
switch ~55 of ~ig. 10 in the second embodi~ent provide
means for varying the amplitude of the waveform in
proportion to the frequency. The interface circuie 130 of
Fig. 8 disclo~es interface means for receiving t~ pulses
from the memory 41 and controlling each switch 171 in
response thereto. Inductor 183 and capacitor 185 (Fig.
. " --
._ .
9) disclose inteqration means for integrating ~he pulses
created by -the openin~ and closing of the sw1tches 171 to
produce a smooth waveform.
More specirically, cornparator amplifier 95 of Fig. 7,
the triangular wave being produced from the oscillator 35
and the associated circuitry for providing a DC level to
the amplifier 95/ serve as enabLing means for changing the
width of each pulse in each series by a factor e~ual to
the frequency selected over the maximum motor frequency~
The amplifier 95 s~rves as clifferential amplifier for
receiving the triancJular wave from the oscillator 35 and a
DC input in proportion to the DC level applied to the
oscillator, for producin~ enahling pulses of width e~ual
to the width of the txiangular wave in excess oE the DC
input.
In connectivn with the second embodiment, the
arnpli~ude switch 255 serves as amplltude switch means for
switching on and off the DC voltage. The triangular wave
from oscillator 35 and the various circuitry associated
with comparator amplifier 95 serve as pulse width means
for providiny amplitude pulses of width proportional to
the frequency of the oscillator and for actuating the
amplitude switch 2S5 with the amplitude pulses to vary the
DC potential between the rails. In the second embodiment,
the inductor 257 and capacitor 259 serve as integration
means between the amplitude switch 255 and the motor 29'
for integrating the pulses created by the amplitude switch
255.
All of the various components making up the circuits
are conventional. Amplifiers 95, 231 and 237 are
preferably hM 339 amplifiers, and the rest of the
amplifiers are preferably LM 324 amplifiers. Counter 39
is preferably a C~ 4040 counter, ROM 41 a 2716 eraseable
ROM, oscillator 35 a LM 566 oscillator and ~optical
isolator 131 a 6N136 circuit.
The invention has significant advanta~es. It
provides speed control of an AC motor without the need for
21
using SCR circu.itry. The frequency can be varied over a
wide range, with the amplitude ~eing varied in proportion
to the frequenc.y change. Both three phase sine wave ancl
six step squa.re waveforms can be generated. If desired,
the circuit will generate a sine wave at start up, then
automatically switch ~o a square wave at higher
frequencies. Large energy storing devices that were
necessary in prior art systems are not recluired. The
system can be used with very hi.gh power motor~O
Wh.ile the invention has been shown in only a few of
its forms, it should be apparent to those skilled in the
art that it is not so limited but is suxceptible to
various changes and modifications without departing from
the spirit of the invention.
