Note: Descriptions are shown in the official language in which they were submitted.
~39 I S
This invention relates to input protection circuits for
integrated circuit devices.
Integrated circuit devices such do CMOS (complementary
meta~-oxide-semiconductor) devices generally have a maximum input
voltage range of -0.3 volts to V t 0.3 volts relative to ground (O
volts), where Vcc is the supply voltage for the device and is
typically 5 volts. Complying with this maximum range presents a
problem where an input of a CMOS device may be subject to an
externally-applied voltage which may greatly exceed this range.
This problem can be overcome by connecting
appropriately-poled diodes between the CMOS device input and the
respective supply voltage lines so that the input voltage can not
swing by more than the forward voltage drop of the diodes beyond the
supply voltages. In this case in order to limit the forward voltage
drop of each diode to the maximum permissible value of 0.3 volts, the
forward current of the diodes must be limited by a high-value
resistance connected in series with the CMOS device input. If the
CMOS device is intended to monitor precisely a voltage which is
normally within the maximum input voltage range, such a high-value
series resistance has the disadvantage of adversely affecting such
precise monitoring.
An object of this invention, therefore, is to provide
an improved input protection circuit which enables the above
disadvantage to be avoided.
According to one aspect this invention provides a
circuit arrangement comprising an integrated circuit device, two
supply voltage lines connected to said device for supplying respective
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predetermined supply voltages thereto, and a protection circuit
connected between an input terminal and an input of said device, the
protection circuit comprising a first resistor connected between the
input terminal and a junction point, a first clamping diode connected
between the junction point and one of said supply voltage lines, a
second resistor coupled between the junction point and the device
input, and a second clamping diode connected between the device input
and said one of said supply voltage lines, each of said diodes being
poled to be reverse-biased in response to voltages between said supply
voltages being applied to said input terminal.
Thus the first resistor and first clamping diode serve
to limit voltage swings beyond the relevant supply voltage to a
certain extent, and such voltage swings are further reduced by the
second resistor and second clamping diode so that at the device input
they are within the permissible range for the device. The use ox
first and second current limiting resistors and clamping diodes in
this manner enables the total resistance of the two resistors to be
very much smaller than would be necessary for the same protection
afforded by a single resistor and clamping diode.
The integrated circuit device may be a CMOS integrated
circuit device such as an analog-to-digital converter an analog signal
input of which constitutes said input.
The first diode may have a forward voltage-current
characteristic with a greater voltage drop than that of the second
diode; for example the first diode may be a silicon diode and the
second diode may be a germanium or Skeptic barrier diode.
The circuit arrangement preferably includes a third
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diode, having characteristics similar to those of the first diode,
connected between the junction point and said other of the supply
voltage lines, and a fourth diode having characteristics similar to
those of the second diode, connected between the device input and said
other of the supply voltage lines, each of the third and fourth diodes
being poled to be reverse-biased in response to voltages between the
supply voltages being applied to said input terminal.
According to another aspect this invention provides a
circuit arrangement comprising a CMOS integrated circuit
lo analog-to-digital converter having an analog signal input, two supply
voltage lines connected to said converter for supplying respective
predetermined supply voltages thereto, and a protection circuit
connected between an input terminal and said analog signal input, the
protection circuit comprising a first resistor connected between the
input terminal and a junction point, a first pair of diodes, each
diode of the first pair connected between the junction point and a
respective one of the supply voltage lines, a second resistor
connected between the junction point and said analog signal input, and
a second pair of diodes, each diode of the second pair being connected
between said analog signal input and a respective one of the supply
voltage lines, the diodes being poled to be reverse-biased when a
voltage between said supply voltages is applied to the input terminal.
The circuit arrangement conveniently includes a
resistor connected between the input terminal and one of the supply
voltage lines and a circuit to be monitored connected between the
input terminal and the other of the supply voltage lines, whereby a
digital output of the converter represents the state of the circuit
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to be monitored. The circuit to be monitored for example comprises
contacts or a switch which may be open or closed, or a transistor
which may be conductive or nonconductive, and may
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include resistive components -to enable distinction of the states of the
circuit being monitored from an open-circuit or short-circuit of a line
connecting -the circuit being monitored to the remainder of the circuit
arrangement.
The invention will he further understood from the following
description with reference -to the accompanying drawing, which
schematically illustrates a circuit arrangement including an input
protection circuit in accordance with an embodiment of the invention.
Referring to the drawing, the circuit illustrated therein
serves to monitor the voltage at an input terminal 1 with respect to
ground or O volts at a terminal 2, and to convert the monitored voltage
into a digital value for serial transmission over a wire 3, which may be
constituted by a telephone line or a dedicated data link. Although only
one is shown, a plurality of such input terminals 1 may be provided, each
coupled to a respective one of inputs ION to IN of an analog-to-digital
converter 4 via a respective input protection circuit as described below,
for monitoring a respective voltage level for any of a variety of purposes
such as remote metering, sensing temperatures, smoke, water, etc., and
security monitoring. A voltage TV is also monitored as described below by
being coupled to an input IN of the converter 4.
The converter 4, which is for example a National
Semiconductor ADC0809 integrated circuit, is a CMOS device which has its
power supply inputs Vcc and GOD connected respectively to a +5 volt supply
line 5 and a ground line 6, to which the terminal 2 is connected.
Reference voltage inputs REV+ and REV- of the converter 4 are also
connected respectively to the lines 5 and 6. For selecting one of its
inputs ION and IN and initiating an analog-to-digital conversion process
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the converter 4 is supplied by a microprocessor 7 via lines 8 with an
alluders and control signals, and returns a signal to the microprocessor 7
via one of -these lines at the end of its conversion process, in response
to which the microprocessor 7 produces the serial data on the line 3 from
the parallel digital data available from outputs of -the converter 4 via
lines 9.
It is assumed for example that the -terminals 1 and 2 are
connected as shown via a 2-wire line 10 of arbitrary length and a series
resistor 11 to a security switch 12 the open or closed state of which is
being monitored. A resistor 13 is connected in parallel with -the switch
12, and a resistor 14 is coupled between the line 5 and the input terminal
l. For example the resistors 11, 13, and 14 have resistances of 1.8k~,
3.3kQ, and ok respectively so that the four possible states line on
open-circuit, switch 12 open, switch 12 closed, and line 10 short-circuit
produce distinct voltages of 5, 3.1, 1.9, and 0 volts respectively at the
input terminal 1. inn the input terminal 1 is selected by the address on
the lines 8, the relevant voltage at this terminal can be converted to an
8-bit digital value by the converter 4, the two most significant bits of
which can be selected and applied serially to the line 3 by the
microprocessor 7 to identify each of the four possible states.
Although in normal operation the voltage at the input
terminal 1 does not exceed the supply voltage range of the converter 4, an
external voltage outside this range could be applied between the terminals
1 and 2. In order to prevent damage to the converter 4 in this event, the
terminal 1 is coupled to the input IN not directly, but via an input
protection circuit 15. In accordance with the invention, the circuit lo
comprises two protective stages, each comprising a series resistor lit and
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17 and a pair of clamping diodes lo, 19 and on, 21. [n addition, the
circuit lo includes a smoothing capacitor 22 connected between the input
IN and the ground line 6.
The diodes 18 and 19 are silicon diodes which have a -forward
voltage drop of about 0.7 volts when they conduct a current of about lima.
In order to limit the current conducted by either diode 18 or 19 to about
lima for external voltages up to about +40 volts applied to the input
terminal 1 with respect to the terminal 2, the resistor 16 has a
resistance of 39kQ. As a result of the clamping action of the diodes 18
and 19, the voltage range at the junction between the resistors 16 and 17
is limited to -0.7 volts to +5.7 volts.
The diodes 20 and 21 are germanium or, preferably, Skeptic
barrier diodes (e.g. Hewlett Packard type 5082-2800) which have a forward
voltage drop of less than 0.3 volts when they conduct a current of about
Moe. For voltage extremes of -0.7 or +5.7 volts at the junction
between the resistors 16 and 17 as described above, the current through
the diodes 20 and 21 is limited to this value if the resistor 17 has a
resistance of 10kQ. Thus the voltage extremes at the input IN of the
converter 4 are limited to -0.3 volts and +5.3 volts, which are the input
voltage extremes tolerated by the converter 4.
Thus the converter 4 is protected by the circuit 15 from
relatively large voltage levels applied to the input terminal 1. The
total series resistance of the resistors 16 and 17 is less than 50kQ,
which is negligible compared with the input impedance of the converter 4
at the input IN and so does not impair the conversion accuracy of the
converter 4. In contrast, if the diodes 18 and 19 and the series resistor
16 were omitted from the protection circuit, then for the same forward
current for the diodes on and 21, and the same voltage extremes a-t the
input terminal 1, the resistance of the resistor 17 would have to he
increased to about ems' to protect the converter 4. Such a high series
resistance is comparable with the input impedance of -the converter 4 and
consequently would seriously impair the conversion accuracy of the
converter. The two protective stages of the circuit 15 avoid this
disadvantage.
It should be noted that, if it were desired to protect the
converter 4 from only positive or only negative voltages applied -to the
input terminal 1, then the diodes 19 and 21 or I and 20, respectively,
can be omitted from the circuit 15.
The capacitor 22 has a capacitance of, for example, 2.2~F,
and serves with the resistors 16 and 17 to smooth voltage fluctuations at
the input IN. Thus noise voltage spikes which may occur at the input
terminal 1 are prevented from being applied to the converter 4, where they
could disturb a conversion operation especially if the converter 4 has no
input sample-and-hold circuitry. Furthermore, the smoothing circuit
formed by the capacitor 22 and the resistors 16 and 17 has a time constant
of about 110ms, so that it also serves to eliminate voltages induced from
arc. supplies.
nether input terminals can be coupled to the other inputs of
the converter 4 via similar protection circuits. For the input IN, the
drawing illustrates an arrangement for monitoring the voltage TV, which
may be a supply voltage from which the +5 Volts supply on the line 5 is
derived. For example, the voltage TV may be a supply voltage which is
derived from an external arc. supply backed up by a battery, the voltage
being lower in the event of failure of the arc. supply than during normal
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operation. Thus monitoring of this voltage can indicate the presence or
absence of the arc. supply and the state of charge of the back-up battery.
In the drawing, the voltage TV of, for example, nominally
9.5 volts is divided by a potential divider comprising resistors 23 and 24
of resistance ~.8kQ and 4.7kQ respectively to produce a voltage which is
within the permissible input voltage range of the converter 4. This
voltage is coupled to -the input IN via a single protective stage
comprising a series 51kQ resistor 25, clamping Skeptic barrier diodes 26
and 27 and a 2.2~F smoothing capacitor 28, whose functions will be
apparent from the foregoing description. Only a single protective stage
is used here because the voltage being monitored is an internal voltage of
predictable magnitude; however two protection stages as in the circuit 15
could be provided in this case if desired.
Thus the input IN of the converter 4 is used for monitoring
the voltage supply of the circuit arrangement. In this case, in view of
the non-linear voltage-discharge characteristic of a battery, the digital
value of all of the outputs of the converter 4 may be used by the
microprocessor 7 to derive a, for example, Betty serial data signal on -the
line 3 to represent the state of charge of the battery underlaid, as
represented by the monitored voltage TV.
Although in the circuit 15 as described above -the diodes 18
and 19 are of a different type (silicon) to the diodes on and 21
(germanium or Skeptic barrier), this need not necessarily be the case.
For example, all of the diodes 18 to 21 could be germanium or Skeptic
barrier diodes having the same forward voltage-current characteristics.
Furthermore, although the circuit 15 includes only two protective stages,
a greater number of series-connected protective stages could be provided
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if desired. In addition, a smoothing capacitor such as the capacitor 22
can be provided individually for each protective stage if desired.
In addition, although the embodiment of the invention
described above relates to input connections to a CMOS dnalog-to-digital
converter the invention is equally applicable to input protection of
other CMOS devices and other integrated circuit devices generally.
Thus whilst a particular embodiment of the invention has
been described in detail, numerous modifications, variations, and
adaptations may be made thereto without departing from the scope of the
invention as defined in the claims.
