PROGRAM CODE FETCH ARRANGEMENT

DISPOSITIF D'EXTRACTION DE CODES DE PROGRAMME

English Abstract

PROGRAM CODE FETCH ARRANGEMENT
ABSTRACT OF THE DISCLOSURE
The present invention permits any number of pages of
data memory to contain program code without the loss of access to
the corresponding page of the program code memory. The memory
select lead derived from a central processor's control leads is
employed by the memory decoding circuitry to distinguish between a
program code and a data fetch. This arrangement forces the memory
to produce a code fetch from data space of memory, when any one of
the pages dedicated to program code is accessed. A fetch control
circuit is included between the central processing unit and
memory. This fetch circuit obtains program code from the data
space in memory when a latch of an input/output port controlled by
the central processor unit is set, indicating that a program
request is to come from data memory and one of the pages of memory
containing program code in the data space is referenced As a
result, the memory decoding circuitry detects this request for a
fetch as a data fetch, although the processor indicated the fetch
as a program code fetch. If the input/output port is not set by
the CPU to force a program fetch from data space in memory,
program code from the program code memory will be fetched.

Claims

WHAT IS CLAIMED IS:
1. In a real time on-line computer processing system,
a program code fetch arrangement comprising:
a CPU;
memory including a plurality of pages of program code
memory and a plurality of pages of data memory;
a data bus connected between said CPU and said memory,
said data bus providing for writing data into said memory or for
reading data from said memory;
a control bus;
an address bus;
latching means connected to said address bus and
operated to produce a first output signal indicating that a
program code fetch is to occur from data memory;
decoding means connected to said address bus and
operated to produce a second output signal for selection of a
memory page indicated by said address bus;
first means for detecting a request for data memory,
said first means for detecting connected between said CPU, via
said control bus, and said memory;
second means for detecting a request for program code
from a page of data memory in combination with the selection of a
page of memory, said second means for detecting connected between
said latching means said decoding means and said memory, said
second detecting means operated to produce a third signal for
transmission to said memory, whereby in response to said program
code fetch request of said CPU, program code is fetched from said
data memory and at the completion of all said program code fetches
from said data memory, program code fetches reoccur from said
program code memory.

2. A program code fetch arrangement as
claimed in claim 1, wherein said latching means includes:
a latch;
first program means operated to set said
latch indicating that all program code fetches are
to occur from data memory.
3. A program code fetch arrangement as
claimed in claim 2, wherein said latching means further
includes:
second program means operated to reset said
latch whereby all program code fetches reoccur from
said program code memory.
4. A program code fetch arrangement as
claimed in claim 1, wherein said control bus includes
a plurality of status leads connected to said CPU
for transmitting indications of whether the next fetch
from said memory is to be a program code fetch or
a data fetch.
5. A program code fetch arrangement as
claimed in claim 4, wherein said first means for
detecting includes:
inverter means connected to a first one
of said status leads;
first gating means connected to at least
a second and a third status lead of said plurality
of status leads and said first gating means connected
to said inverter means whereby said first gating means
is operated in response to a memory fetch request
from said CPU to produce a third signal which dis-
tinguishes between a request for a data fetch and
a program code fetch.
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6. A program code fetch arrangement as
claimed in claim 5, wherein said address bus includes:
a plurality of leads representing a memory
address to be written into or read from;
a plurality of page leads indicating which
one of said plurality of pages of data memory or
alternatively which one of said plurality of pages
of program code memory from which to fetch the data
or program code respectively.
7. A program code fetch arrangement as
claimed in claim 6, wherein said decoding means includes:
OR gating means:
a connection from each of said plurality
of page leads to said OR gating means:
and a connection to said second means for
detecting.
8. A program code fetch arrangement as
claimed in claim 7, wherein said second means for
detecting includes:
second gating means connected to said latching
means and to said OR gating means and operated in
response to a program code fetch request from data
memory in combination with a selection of one of said
plurality of said memory pages as indicating that
page leads to produce a fourth signal indicating that
a program code fetch is to occur from data memory.
9. A program code fetch arrangement as
claimed in claim 8, wherein said second means for
detecting further includes:
third gating means connected to said memory,
to said first and to said second gating means and
fifth signal indicating that data is to be fetched
from said data memory or alternatively said third
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gating means operated in response to said fourth
signal to produce a sixth signal indicating that
program code is to be fetched from said data memory,
10. A program code fetch arrangement as
claimed in claim 5, wherein said first gating means
includes a NAND gate connected to said second and
third status leads and to said first status lead via
said inverter means.
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Description

PROGRAM _ODE FETCH ARRANGEMENT
BAC KGROUND OF THE I NVENT I ON
The present invention pertains to central
processing unit access to memory and more particularly
to an arrangement for executing program code from
data memory without any loss of corresponding program
code memory.
Present day computer central processor units
(CPUs) provide control information indicating the
status of whether a memory read is a program code
fetch or a data fetch. This control information has
been used in the past in memory decoding circuitry,
so that both data memory and program code memory could
each utilize the full addressing capability of the
CPU. For example, a processor with a 16 bit address
would be able to access 64K words of data and 64X
words of program code. This implementation does not
provide for certain pages of the data memory to con-
tain program code.
Other memory decoding circuitry may alot
certain pages of the data memory to contain program
code, but the corresponding memory page of the program
code m~mory then could not be used for program code
storage.
Accordingly, it is the object of the present
invention to provide for the allocation of program
code to data memory storage without the 105S of the
corresponding page of the program code Eor the storage
of program code.
SUMMARY OF THE INVENTION
The present invention permits any number
of pages of data memory to contain program code with-
out the loss of access to the corresponding page of
the program code memory. The memory select lead
derived from a central processor's control leads is
employed by the memory decoding circuitry to distin-
guish between a progra~ code and a data fetch. This
arrangement forces the memory to produce a code fetch
from data space of memory, when any one of the pages
.,
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dedicated to program code is acces~ed. A fetch con-
trol circuit is included between the central processing
unit and memory. This fetch circuit obtains program
code from the data space in memory when a latch of
an input/output port controlled by the central pro-
cessor unit is set~ indicatin~ that a program reques~
is to come from data memory and one of the pages of
memory containiny program code in the data space is
referenced. As a result, the memory decoding circuitry
detects this request for a fetch as a data fetch,
although the processor indicated the fetch as a program
code fetch~ If the input/output port is not set by
the CPU to force a program fetch from data space in
memory, program code from the program code memory
will be fetched.
At the completion o the execution of the
program in data m~mory, the previously set latch of
the input/output is reset. Execution control is then
transferred to the program which initiated the transfer
to the program in data memory. As a result, all
program code fetches occur from program code memory
and all data fetches occur from data memory.
DES~RIPTIO~ OF THE DRAWINGS
Figure 1 is a block diagxam of the CPU/memory
interface of the present invention.
Figure 2 is a schematic diagram of the fetch
circuitry oE Figure 1.
Figure 3 is a memory layout depicting program
control and execution.
DESCRIPTION O.F THE PREFERRED EMBODIMENT
Referring to Figure 1, a CPU such as the
Intel 8086 microprocessor, is shown connected via
address, control and data buses to memory. Intel
is a registered trademark. A fetch control circuit
iæ shown connected between the CPU and the memory.
An I/O port, which provides CPU settable latches,
is connected between the CPU and the fetch control
circuit. In addition, an address decoder is con
nected between the CPU and the fetch control
circuit via the address bus. The address bus
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of the Intel*8086 is 16 bits. However, an additional
4 bit~ are employed to select different page~ o~ 64K
memory.
Referring to Figure 2, control leads SO,
Sl and S2 of the CPU's control bus indicate that the
current address on the address bus is a request for
program code when these signals present the binary
values 1 0 1, respectivelyO Inverter 10 and NAND
gate 20 distinguish between a data etch and a program
code fetch. NAND gate 20 provides a logic O output
when a code Eetch is being performed. This lead would
normally be transmitted directly to the memory decoders
to distinguish between program code and data fetchesO
An output signal of an IjO port latch is
connected to one of the inputs of AND gate 40~ The
other input to AND gate 40 is output of OR gate 30
which decodes a selection o~ any memory page. ~AND
gate 20 and AND gate 40 are connected to OR gate 50,
which has its output connected to the memory.
In normal operation, I/O port latch input
to gate 4~ is reset by the CPU program. This causes
AND gate 40 to provide a logic O to the input oE OR
gate 50. A~ a re~ult, the output of OR ga~e 50 w111
reflect the ~tatus of the data ~etch signal output
by NAND gate 20 and all program code fetches will
occur from the program code memory space of memory
and all data fetcnes will occur ~rom the data ~pace
of memory.
Referring to Figures 2 and 3, program one
resident in page E of the program code space requires
that program two, which is located in page E of the
data space, be given control. Program one transfers
intermediate control to the SET FLIP-FLOP program
indicated by transfer 1 in Fig. 3. The SET ~LIP-FLOP
program sets the lat~h connected to the inpu~ to OR
gate 40 and transfers control to program two indicated
by transfer 2. As a result, for memory references
made to page E, the corresponding program ope~ation
codes are fetched from the data space of page E.

Since the I/O port latch is set and OR gate 30 is
set, AND gate 40 will produce a logic 1 signal which
will be transmitted through OR gate 50 indicating
that data is to be fetched from memory. In actuality~
this apparent data will be program code from the data
space. However, control leads S0, Sl and S2 indicate
that the processor requested a program code fetch.
Thereby, program two will have been executed while
being resident in the data space of page E.
~hen the execution of program two is com-
plete, control will be returned to program one via
another intermediate program RESET FLIP-FLOP indicated
by transfer 3. The RESET FLIP-FLOP program resets
the previously set latch of the I/O port and then
returns control to program one indicated by transfer
4~ The CPU then reverts back to its normal mode o-f
processing all program code fetches from program code
memory and all data fetches from data memory.
It is to be noted that the intermediate
20 programs SET FLIP-FLOP and RESET FLIP-FLOP cannot
be located on the same program code page on which
the target program located in the data space, program
two in the preceeding example.
Although the preferred embodiment of the
invention has been illustrated, and that form described
in detail, it will be readily apparent to those skilled
in the art that various modifications may be made
therein without departing from the spirit of the
invention or from the scope of the appended claims.