Note: Descriptions are shown in the official language in which they were submitted.
1 ELECTROMAGNETIC SIGNAL RECEIVER AND PROCESSOR
FOR PROVIDING FREQUENCY DATA OF
RECEIVE~ SIGNALS
.
This invention relates to electromagnetic signal
receivers, and more particularly to a device capable of
processing received signals and providing frequency data for
both shor. and long duration pulses including continuous wave
(CW) signals.
Heretofore, two types of receivers have been
available which are capable of processing RF signals and
determining the frequency of the received signals, but each
receiver had its own particular advantages and disadvantages,
and none combined the desirable advantages of both the
available types of receivers.
For e~ample, one type of receiver in extensive use
today to determine the frequency of received RF signals,
particularly in the radar frequency spectrum extending from
below 2 GHz to above 6 Ghz, is the IFM Receiver
(Instantaneous Frequency Measuring Receiver) such as ANAREN
20 Digital Frequency Discriminator (DFD), Model 18260 which is
commercially available from Anaren Microwave~ Inc~ of
Syracuse, New York. For such an IFM receiver to work
properly, it is necessary to remove the ma~or amplitude
varîations of the power level of the incoming signal which is
25 generally accomplished by a limiting amplifier such as the
AML-2000 Series GaAs FET amplifier which is
commercially availa~le from Avantek, II1C. of Santa Clara,
California. For the purpose of the ensuing description and
the appended claims, the term IFM receiver includes the
3o limiting amplifier which contro's the power level of the
incoming signal.
1 One of the great advantages of the IFM receiver is
its short response time which enables it -to determine the
rrequency of the received radiation and output this frequency
in digital format in between 50 and 250 nanoseconds. Another
advantage of the IFM receiver is its large band width which
may extend from below 2 GHz to above 6 GHz. For applications
involving countermeasures and other military objectives, such
as friend-foe recognition, the short response time and the
large bandwidth are most desirable qualities and are the
10 primary reasons for the popularity of the IFM receiver.
However, the IFM receiver also has a number o~ limitations
which detract from its usefulness and which include its
inability to process more than one received signal at any
given time and, if receiving more than one signal at one
15 time, of always selecting the stronger one for processing.
This makes it susceptible to jamming when a strong signal,
having a long pulse duration or a continuous wave (CW)
signal, is received, the IFM receiver then processes only the
jamming signal and is not receptive to the important or
20 significant signals whose detection is the primary purpose of
the receiver. Another disadvantage of the IFM receiver is
its inability to provide amplitude data of the received and
processed signal.
For the sa]~e of completeness, it should be
25 understood that the conventional IFM receiver normally has at
least three inputs and three outputs, only some of which will
be important in connection with the present invention. The
three inputs to the IFM receiver are the received ~F signal,
the DATA READ signal and the DATA ACKNOWLEDGE signal, and its
30 output signals are the DIGITAL FRE~UENCY signal, the ~IGNAL
1 PRESENT signal, an~2 the DATA READY siynal. The IFM receiver
also contains a built-in threshold detection circuit which is
adjustable and which prevents the receiver from processing
any siqnals having an amplitude below a set threshold thereby
5 preventing the receiver from being triggered by noise or a
noise like signal. This threshold detection circuit
generates the SIGN~L PRESENT output only if the received RF
signal is above the selected threshold and is being processed
to provide the DIGITAL FREQUENCY signal. The SIGNAL PRESENT
signal occurs usually 50 nanoseconds after receiving the RF
signal. After another 50 to 250 nanoseconds the DIGITAL
FREQUENC~ signal is developed and placed in an internal
storage register, a condition normally indicated by the
occurrence of the DATA READY signal. The data in the
15 internal register is generally read out of the register upon
the application of the DATA READ signal, and after the
successful transfer of the frequency signal out of the
storage register to utilization device, the DATA ACKNO~LEDGE
signal is generated which will reset the IFM receiver for the
20 processing of further received signals.
Another receiver in use today which was aeveloped
after the IFM receiver, is the IFT receiver (Instantaneous
Fourier Transform) such as the ITEK IFT Model 200-1 which is
commercially available from the Applied Technology Division
25 Of Itek Corporation of Sunnyvale, California. This receiver
utilizes a HeNe gas laser, in conjunction with an
accousto-optic device capable of providing frequency and
amplitude measurement of received signals. The output of the
IFT receiver is derived from a linear array of
3o photodetectors, which, unlike ~he IFM receiver r produce an
output measure of the frequencies present as well as
amplitudes of a number of simultaneous signals.
* Trade mark
~9~ 5
,~
1 One of the great advantayes of the IFT receiver,
therefore, is its ability to measure the frequency of a
number of simultaneously occurring signals, as well as their
amplitudes, so that it is not subject to jamming by
simultaneous signal events and is able to provide frequency
data for all signals simultaneously received. The IFT
band-width is much smaller than that of the IFM receiver and
extends normally only through a frequency range of 500 to
1000 MHz. Further, the IFT receiver has an output response
time which is long when compared to that of the IFM receiver,
due to the nature of the detector readout process.
The data derived from the IFT receiver is analog in
form as far as amplitude is concerned and is normally applied
to an analog-to-digital converter to obtain digital amplitude
15 data. Further, frequency information is provided by
photodetector position in the array so that reformatting of
the data is required to put it in the same form as the output
from the IFM receiver for further processing by a utilization
device.
The present invention provides an electromagnetic
signal receiver and processor for determining received signal
frequency information which includes the advantages of rapid
response and great band width of the IFM receiver and the
simultaneous frequency capability and amplitude determination
25 facility of the IFT receiver.
The present invention provides an electromagnetic
signal receiver and processor for developing frequency
information which is ordinarily not subject to long pulse or
CW jamming and which provides frequency data of received
30 signals heretofore not even available by the use of separate
IFM and IFT receivers.
~ ~3'1~S
1 The invention combines the advantages of the IF~q
and IFT receivers and can operate under condi-tions under
which either the IFM or the IFT operating separately would
~ail.
The invention provides an indication when the IFM
receivex is receiving simultaneous or overlapping signals so
that its output frequency signal measurement may be dfscarded
as unreliable. Moreover, the invention is responsive to a
listing of frequency data of certain known signals, and is
operative to take a predetermined action upon recognizing
those frequency data.
The electromagnetic signal receiver and processor
of the present invention essentially includes an antenna
responsive to received electromagnetic signals to provide
15 received RF signals. An IFM receiver is responsive to the
received RF signals to provide digital data on the
frequencies present in the received RF signals. A pulse
status unit also responds to the received RF signals, and
provides an unblanking signal only when a received RF signal
20 has a pulse width greater than a predetermined width. A
mixer is also responsive to the received RF signals, and
provides intermediate frequency signals. A circuit receives
the intermediate frequency signals, and delays the signals by
a predetermined time interval. An IFT receiver is responsive
25 to the delayed signals to provide spectral data on the
frequencies present in the delayed signals. A blanking
circuit is disposed between the delay means and the IFT
receiver and normally blanks a signal applied thereto.
However, the blanking circuit is responsive to the unblanking
30 signal to allow the delayed signals to pass the IFT receiver
for normal processing.
~3'~
-6-
1 Figure 1 is a schematic block diagra~ of the
electromagnetic signal receiver and processor of the present
invention.
Figure 2 is a more detailed schematic block diagram
of the pulse status unit shown in Figure 1 which is used for
controlling, inter alia, the blanking of the input signal to
the IFT receiver.
Figure 1 depicts the electromagnetic signal
receiver and processor of the present invention in block
diagram form, and shows a suitable antenna 12 for receiving
the electromagnetic (RF) signals of interest which, normally,
are within a range extending from below 2 GHz to above 6 GHz.
The RF signals from antenna 12 are applled to a conventional
signal splitter 14 which divides the signal into three
15 portions which are applied, respectively, to lines 16, 18 and
20. Line 16 is connected to a conventional IFM receiver 22
which~ normally but not necessarily, has two other input
signals, namely the DATA READ signal on lead 24 and DATA
ACKNOWLEDGE signal on line 26. The conventional IFM receiver
20 also has, as already mentioned, three output signals, namely
the DIGITAL FREQUENCY signal on line 28, the SIGNAL PRESENT
signal on line 30 and the DATA READY signal on line 32.
The received signal on line 16 is an RF signal and
the DIGITAL FREQUENCY signal on line 28 is a multi-digit
25 signal derived from an internal storage register in IFM
receiver 22. The remaining signals, such as the DATA READY
signal, the DATA ACKNOWLEDGE signal, the DATA READ signal and
the SIGNAL PRESENT signal are normally digital signals which
are either zero or one, as well known to those skilled in the
3o art.
1 The received RF signal is also applied to a
conventional mixer 34 which is controlled by a mixer
~requency select network 36 for the purpose of converting the
frequency of the received RF signals, which are in 2 to 6 GHz
range, to a lower frequency range, such as 1000 MHz since the
conventional IFT receiver can only handle lower ranges of
frequencies. Typically, mixer 34 and mixer frequency select
network 36 converts the incoming frequency to a band of 500
MH~ centered at 1 GHz. The down-conversion of the frequency
of the received RF signal is well understood to those skilled
in the art and comprises the mixing of two high frequency
signals to generate an output which is commensurate with the
difference between the two frequencies, utilizing the normal
heterodyne principle.
The down-converted received RF sigrlals are then
applied, via lead 38 to a delay line 40 which delays the
signal to the IFT receiver by a short time interval, such as
by 5 microseconds. The delayed output signal is then
applied, via lead 42, to an attenuator/blanking network 44,
20 which may be a conventional attenuator with a control lead,
which includes a passive attenuator section at the input
section and a logical control section which is enabled by a
control signal on lead 46 generated by an IFT blanking logic
network 48 which may be a conventional OR gate. The delayed
25 output signal from attenuator/blanking network 44 is then
applied, in the case of an enabling control signal on line 46
which unblanks network 44, via lead 50 to a conventional IFT
receiver 52 for generating frequency and amplitude data of
the received radiation, as well known to those skilled in the
3o art.
1 The receivecl RF signal on line 18 is also applled
to a pulse status unit 54 (PSU) which provides at least two
different output signals, namely SIMULTANEOUS SIGNAL DETECI'OR
signal, also referred to as the SSD signal and the PULSE
~IDTH DISCRIMINATOR signal also referred to as the PWD
signal. Pulse status unit 54 will be explained in more
detail in connection with the description of Figure 2. Also
applied to pl~lse statu~ unit 54 is the SIGNAL PRESENT signal
from IFM receiver 22 which functions as an enabling signal
for the signals developed by PSU 54 as will also be explained
hereinafter.
One output signal of pulse status unit 54, namely
the PWD signal, is utilized to control blanking network 44 to
allow the selective processing of the delayed signal by IFT
15 receiver 52. With respect to control line 46, "enable" means
unblank and "inhibit" means blank.
There is further provided a memory 56, which is
usually in the form of a memory array for the storage of a
large number of frequencies within the frequency range of
20 interest of the received RF signal. Memory 56 is normally
divided into at least two groups of memories, one for storing
frequencies which are definitely of interest and one for
storing frequencies which are definitely not of interest.
Memory 56 provides a control signal on lead 58 which ls
25 normally of digital form and which is also applied to IFT
blanking logic network 48 to provide enabling signal to
unblank network in case of a frequency of interest and to
blank or inhibit that network in case of a frequency of no
interest. In this manner, many frequencies detected by IF~1
3o
- 9 -
1 receiver 22, which are not of interest, are prevented either
from being detected by IFI' receiver 52 or, if so detected,
from being sent on along associative memory output line 60 to
an operator or a computer or some other utili~ation network
5 which utilizes the frequency and amplitude determinations
made by the receiver~processor of the present invention.
In this connection, it should also be noted that
the digital frequency output signal from IFM receiver 22 is
applied, via output lines 28 and 62, to one of the inputs of
lO associative memory 52 and that the many fre~uency signals
devel.oped by IFT receiver 52 are, after suitable conversion
into digital form by an A/D converter unit 64, are likewise
applied to me~lory 56 along lead 66. Even though the output
signals from IFM receiver 22 are available on line 28, the
15 preferred embodiment of this invention, contemplates
screening these signals b~ memory 56 before passing them on to
~urther processing along output signal lead 60. The same is
true of the frequency data developed by IFT receiver 52 which
are available on output line 53, but which are preferably
screened by memory 56 before being passed on to output signal.
line 60.
Referring now to Figure 2 of the drawings, there is
shown a more detailed block diagram of pulse status unit 54.
Basically pulse stat:us unit 54 comprises a power signal
splitter 100 to which the received RF signal from lead 18 is
applied and which splits up the received RF signal into two
branches, one being applied to a simultaneous signal detector
102 which develops the SSD signal and the other being applied
to the series combination of a threshold signal detector 104
3o which develops a TDS signal, and a pulse width discri~inator
--10--
1 106 whi.ch develops the PWD signal. At the output end of PSU
54, the output form the two subnetworks just mentioned are
applied to AND gates 108 and 112, respectively, each of which
is enabled by the SIGNAL PRESENT signal from IFM receiver 22
on lead 30. More particularly, the output signal of ~ND
gate 108 is referred to as the SSD signal which is developed
by simultaneous signal detector 102, and the output signal of
AND gate 112 is the PWD signal which is developed by pulse
width discriminator 106.
Simultaneous signal detector 102 includes, in the
order stated, a suitable band pass filter 114 having a 2 to 6
GHz passband, a homodyne detector (mixer) 116 which develops
the difference frequency between two simultaneously received
signals, a low pass filter 11~ having a cutoff frequency of 2
15 GHz, a video detector 120, and a high gain comparator 122
which is trigyered when the difference between any two
simultaneous signals received by band-pass filter 114 has a
difference of 2 GHz or less~ such triggering providing a
digital output signal which is either high or low.
It is of course immediately recognized that the
lowpass filter determines the frequency separation between
any two simultaneously occurring events for which detector
102 will provide a ~S~ signal. In the illustrated detector,
a SSD signal is only developed when the simultaneously
25 occurring events are separated by not more than 2 GHz. Other
selections of the cutoff of the lowpass filter are possible.
The operation of simultaneous signal detector is as
follows. Assume two simultaneous pulse si~nals occurring at
3 and 4 GHz, both passing through the bandpass filter 114 and
3o mixing in the homodyne detector 116 to produce a difference
l frequency of 1 GHz which is below the cutoEf of lowpass
filter 118. The 1 GH~, signal is detected in detector 120
and if it is of sufficient amplitude, it triggers the
threshold amplifier 112 to indicate a simultaneous event
which is an output of AND gate 10~.
The operation of threshold detector 104 and pulse
width discriminator 106 is as follows. The received signal
is applied to a video detector 124 where it is detected, and
a ~ideo signal is developed which is applied to a log video
amplifier 126. The detected and amplified video signals are
then compared with an adjustable .reference level in a
comparator 128 which provides a digltal output slgnal which
is high for all signals greater than the reference signal.
In other words, if the output of amplifier 126 is larger than
15 the input from the reference level, a digital output is
developed which, after passing through AND gate 110, becomes
a TDS signal. The TDS signal is a required input signal to
pulse width discriminator 106 to assure timely response to
the leading edge of an incoming signal.
Pulse width discriminator 106 only receives a
signal if threshold signal detector 104 has a high output,
and this output is split into a two path network, one of
which includes a one-shot monostable multivibrator 130. The
outputs of both paths are applied to a comparator 132 which,
25 in this manner, will compare the leading edge of the pulses
with the time interval set by the mono-stable multivibrator
130 and, if the lagging edge of the pulse arrives after the
one-shot multivibrator 130 has fired, comparator 132 produces
a negative output for pulses having a pulse width less than
3O the one-shot mono-stable multivibrator 130 and a positive
~12-
1 output for pulses having a pulse width greater than the cycle
time of the one-shot multivibrator 130. This output is then
applied to a diode 134 which eliminates the negative going
signal and the output of dicde 134 is then applied to a
second comparator 136 which produces a digital signal when
the detector output is positive.
The operation of the electromagnetic signal
receiver and processor of the present invention will now be
explained with the aid of varying input signals that antenna
12 may see. For a better understanding of the operation of
the present invention, the explanation will be divided into
six different cases, each case illustrating a particular set
of received signals.
Assume as a first case that the received signal
15 comprises only a single long pulse which includes the case of
a CW signal. The received signal is applied to IFM receiver
22 via lead 16 t and assuming the signal being above the
minimum threshold to which the IFM receiver is adjusted, it
is processed by the receiver. About 50 nanoseconds after
20 receipt, the receiver provides a SIGNAL PRESENT signal on
line 3~ and about 5~ to 200 nanoseconds later a DATA READY
signal will appear on line 32 indicating the storage of the
frequency data in digital form in an output register. If it
is desired to immediately transfer the frequency data to line
25 2~ for receipt by other equipment, as will be discussed
hereinafter, a DATA READ signal is applied to line 24 to
cause IFM receiver 22 to release th2 frequency data, and upon
reception of the frequency data by some auxiliary equipment
such as a computer (not shown), the computer will acknowledge
30 receipt of the data by sending a DATA ACKNOWLEDG~IENT signal
s
-13-
1 which resets IFM receiver 22 to be ready for processing the
next received signal. As a practical mat-ter, and for the
purpose of the ensuing description of this invention, the IFM
receiver may be modified, as well known to those skilled in
the art, by dispensing with the DATA READ signal on line ~4
and the DATA ACKNOWLEDGMENT signal on line 26 and by
transmitting the frequency data as soon as available, and
upon transmitting the frequency data as soon as available,
and upon transmission of these data have the receiver reset
itself automatically to be ready for the next step. The long
pulse or CW signal is applied, at the same time, to pulse
status unit 54 where the threshold is determined and,
assuming that it is above a minimum predetermined level, a
THRESHOLD DETECTION signal is developed and applied to pulse
15 width discriminator 106 which makes the determination whether
the pulse width of the received signal is above or below a
predetermined width. The network is set by adjustment of
one-shot multivibrator 130 to make a distinction between long
pulses and short pulses for the purpose of generating a
"high" PWD signal only if the pulse widtn of the received
signal is larger than the predetermined pulse width so that
network 44 can be unblanked. ~or the purpose of this
inven'ion, if the pulse width of the received signal is
greater than a predetermined p~llse width, the received signal
25 can also be a CW since discriminator 106 distinguishes only
between pulses which are shorter or longer than a
predetermined pulse width. Since it was assumed in this case
that the incoming signal is either CW or a pulse 1onger than
a predetermined pulse width, a "high" PW~ signal will be
3O developed by discriminator 106 and will become available from
-14-
l logic network 112. The received signal is also applied, via
lead 20, to mixer 3~ and to delay 40 where it is held for 5
microseconds to give pulse s-tatus unit 54 sufficient time to
make a determination whether the pulse in the received signal
is a long pulse or a short pulse and develop the PWD control
signal to unblank blanking network 44 in case of a long
pulse. Since in this case we postulated a long pulse or CW
signal, a PWD control signal is developed which will
unblank network 44 to allow the received signal to pass
through it and to be applied to IFT receiver 52 which will
process the same and develop an output of frequency and
amplitude data of the received C~ siynal. Another way of
stating this is that pulse width discrimination network 106
develops a blanking signal for a pulse less than the pre-
15 determined width and an unblanking signal for a pulse greaterthan the predetermined width.
Assume as a second case tha-t the received signal is
a short pulse only, which means that it is a pulse whose
width is less than a predetermined width so that the PWD
20 control signal developed ~y pulse s-tatus unit 54 is in the
logical state which will not unblank network 44 thereby
preventing the short pulse from reaching IFT receiver 52.
The short pulse is applied, via line 16, to IFM receiver 22
which, with its fast characteristic speed, develops frequency
25 data of the received signal for storage in its output
register~ Likewlse, a signal present is developed on line 30
but since the pulse status unit 54 does not develop a PWD
signal indicative of a long pulse; and since delay 40 is
sufficiently long to prevent the short pulse form reaching
30 the IFT receiver 52 ~efore development of appropriate PWD
control signal, the received signal is never applied to IE'T
receiver 52.
-15-
l Assume as a third case that the received signal is
a short pulse of high amplitude in the presence of the CW
or long pulse at lower amplitude. Since it is a
characteristic of IFM receiver 22 to select only the highest
amplitude received signal, a further assumption has to be
made. Assuming that both of the received signals have the
same leading edge so tha~ IFM receiver 22 will lock on to the
higher amplitude short pulse and will immediately develop the
appropriate frequency dataO Pulse status unit network 54
likewise receives both of these pulses and simultaneous
signal detector 102 will develop an output signal indicative
of the fact that more than one signal is present. This
signal, referred to as the SSD signal, provides an indication
that the output of the IFM receiver 22 is not trustworthy
15 because more than one pulse was received, and the frequency
data should be disregarded. This is particularly true if IFM
receiver 52 starts processing a lower amplitude pulse and a
higher ampli~ude pulse comes along before processing of the
low amplitude pulse is completed, in which case the IFM
20 receiver 22 will lock on the higher amplitude pulse and give
unreliable results. Pulse status unit 54 will also develop
a short pulse indication signal which prevents the signal on
line 20 from reaching IFT receiver 52. However, after a
short time, the short pulse is no longer present and instead
25 IFM receiver 22 is faced with a long pulse. It will then
develop the frequency data of the long pulse, provide a
SIGN~L PRESENT signal while the pulse status unit 54 develops
a long pulse signals for the PWD signal to allow the long
pulse signal to reach IFT receiver 52 where the long pulse is
30 analyzed and frequency data are provided.
~16-
l Assume as a fourth case a received signal which has
multiple long pulses of varying amplitude. In this
particular case, IFM receiver 22 will provide frequency data
with ^espect to the highest amplitude long pulse it receives
and also provide a SIGNAL PRESENT signal on line 30. Pulse
status unit 54 will see several long pulses and develop a PWD
signal which will allow the received signal to pass to IFT
receiver 52 where all pulses, assuming them to be within the
relatively narrow band width compatible with the IFT
receiver, are analyzed with the appropriate ~re~uency and
amplitudes being provided. In this case, the SIGNAL PRESENT
signal on line 3Q is also an indication to the remainder of
the system that IFM receiver 22 is busy, has a signal, and
wants IFT receiver 52 to take whatever comes in. In other
15 words, jamminy of IFM receiver 22 by a strong CW signal
converts the SIGNAL PRESENT signal into the equivalent of a
"busy" signal and since the CW is a long signal it will open
blanking network 44 to allow short and along pulses and
whatever else is received to go to IFT receiver 52 to be
analyzed, assuming the pulse in the received signal being
long enough for analysis purposes.
Assume as a fifth case that the received signal
comprises multiple short pulses of di~ferent amplitudes. The
received radiation will be processed by IFM receiver 22, and
since all pulses are short, pulse status unit 54 will not
enable blanking network 44 so that no pulses reach IFT
receiver 52. In this connection it should be noted that
simultaneous signal detector 102 will provide a logical
output signal whenever pulses occur simultaneously, or at
3o least close enought to be within a predetermined time
-17-
l in~erval, to indicate to a user of the frequency data that
the data are unreliable. For example, if the first pulse to
be processed by IFM receiver ~2 is a higher amplitude pul~e,
and a seco~d incoming pulse is a low amplitude pulse, there
is no problem because the IFM receiver 22 will continue with
the processing of the higher amplitude pulse and the output
data are reliable. However, if the first pulse received by
IFM receiver 22 is a lower amplitude pulse than the
sùbsequently received pulse, then the IFM receiver will start
processing the higher amplitude pulse upon receipt making the
data unreliable. The SSD signal from pulse status network 54
is preferably entered into the IFM output register as a digit
which can be read during subsequent utilization of the
frequency data to apprise the user that the data is
15 unreliable.
Assume as a sixth and last case that the received
signal comprises multiple long and short pulses of varying
amplitudes, a situation that is most often encountered in
actual use. IE'M receiver 22, will, at all times, process the
20 strongest pulse to which it is exposed regardless of whether
it is a short or long pulse. Accordingly, the various pulses
in the received signal will contend for being processed by the
IFM receiver 22 with the strongest one at any one time being
the one processed. In the event of the arrival of
25 simultaneous pulses, an SSD signal will be developed which
will warn the user that the IFM frequency data may be
unreliable. At the same time, and as a signal is being
processed, a SIGNAL PRESENT signal appears on line 30 which
will enable the various AND gates in pulse status unit 54.
30 Likewise, as long as the AND gates are enabled, PWD signals
are continually being developed for pulses that are long
which enable blanking network 44 to allow these various
pulses to reach IFT receiver 52 for processing.
a3~ .3 5
-18~
l If the frequency detected by IF~I receiver 22 is one
that is of no interest at all, and stored as such in
associative memory 56, the memory provides a signal on output
line 58 to logic network 48 to advise it that this is a
5 non-interest signal and therefore to enable blan]cing network
44 to prevent burdening IFT receiver 52 with processing
unnecessary or unwanted data. Likewise, output signals from
memory 56 on line 60 exclude frequency data not of interest
so that the utilization device to which output signal line 60
is connected does not include many frequencies that are
either undesired or that should perhaps be treated with some
priority~ Output signal path 60, even though shown as being
a signal line, preferably comprises two lines, one being a
priority line which carries only frequency data of recognized
15 important frequencies while the other line carries the
remainder of the frequency data of the received signal.
There has been described an electromagnetic signal
receiver and processor which develops frequency data on
received signals which includes most of the advantages of the
IFM receiver, such as speed and bandwidth, as well as the
advantages of the IFT receiver, such as frequency data for
multiple signals and amplitude information with respect to
the various signals. Likewise, the device is not subject to
ordinary jamming since any attempt to jam the IFM receiver
25 will provide a signal present which enables certain logic
networks which allows all other signals to be received by the
IFT receiver for processing.
3o
