Note: Descriptions are shown in the official language in which they were submitted.
~5~
This invention relates to a method of, and a terminal for,
transmitting bytes on a bus.
It is known ~o transmit by~es bit-serially on a bus to which
a plurality of terminals are connected~ A problem with known
arrangements, however, arises whenever two terminals simultaneously wish
to transmit bytes. In such a situation, the terminals contend with one
another for access to the bus, and this contention must be resolved in
some manner, such as according the terminals different priorities and
awarding the bus to the terminal having the highest priorityO
In a case where the terminals comprise telephones producing
digital signals, generally known as digital telephones, known schemes for
resolving contention for the bus are subjectively disadvantageous~ For
example, if two dlgital telephone extensions are connected to the same
bus, speech signals from only one of them can be carried by the bus at any
instant. Determining which telephone is to be awarded the bus gives rise
to difficulties and problems, and the results can be subjectively
annoying.
Accordingly, an object of this invention is to provide a
method of, and a terminal for, transmitting bytes on a bus, which enable
disadvantages of known arrangements to be avoided or reduced, and which
are particularly applicable to digital telephone arrangements.
According to one aspect of this invention there is prnvided
a terminal for transmit~ing data by~es of a digital da~a signal on a
serial data bus, the terminal comprising: first means for providing bytes
for transmission bit-serially with magnitude bits first, in order of
decreasing significance, and any sign bit following the magnitude bits;
second means for applying a signal to ~he bus in response ~o each serial
bit having a first binary value; and third means for inhibiting the
application of such signals ~c the bus by the second means9 for the
~1`.`,`,
remaining serial bits of the current data byte, in response to such a
signal occurring on ~he bus during a serial bit having a second binary
value9 whereby each byte is only transmit~ed to the bus if its magnitude
is not less ~han ~hat of any data byte simultaneously on the busO
The third means preferably comprises receiving means for
receiving signals from the bus and producing a corresponding bit stream,
means for comparing bits of the bit stream with the serial bits of each
data byte provided by the first means, and means for inhibiting the second
means for the remainder of the current byte if the compared bits have
different binary values. The means for comparing bits can convenien~ly
comprise an exclusive-OR gate~
The terminal preferably includes means, responsive to said
bit stream and to the means for inhibiting the second means, for receiving
from the bus bytes during which the second means has been inhibited. Thus
the terminal can receive bytes from the bus as well as transmitting them
thereto, whereby the bus can be used for transmitting bytes in both
directions thereon. At the start of each byte, the terminal is set to
transmît a byte, and if transmission of this by~e is interrupted then the
terminal is set to receive the greater magnitude byte which occurs on the
~O bus.
The flrst means and the means for receiving bytes can
together comprise shift register means, such as two shift registers for
respectlvely supplying bits of a byte for the bus and receiving bits of a
byte from the bus, and a coder-decoder, genPrally referred to as a codec.
This is particularly convenient in tne case that the terminal is a
telephone.
Preferably the firs~ means includes means for providing each
data byte for transmission with a final parity bit so that each byte has
even parity. Convenien~ly the second means comprises means for applying a
pulse to the bus in response to each serial bit which is a binary one,
successive pulses having opposite polarities and the first pulse of each
byte having a predetermined polarity.
According to another aspect this inven~ion provides a method
of transmitting data bytes on a serial data bus having terminals coupled
thereto, comprising the steps of: synchronizing the terminals to transmit
data bytes simultaneously and in synchronism; and, in each terminal:
providing each data byte for transmission bit serially with the bits in
order of decreasing significance; applying a pulse to ~he bus in response
to each serial bit of one binary value; detecting any pulse on the bus
during each serial bit of another binary value; and inhibiting the
application of said pulse for the remaining serial bits of the current
data byte in response to such detection; whereby ~he most significant data
byte of the simultaneous data bytes prevails on the bus.
The method preferably includes the step of, in each
terminal, receiving from the bus each data byte which has not been
transmitted by that terminal.
Preferably the bus is a balanced line, the pulses are
applied to the bus with alternating polarity, the first pulse of each data
byte From each terminal having the same polarity, and each data byte
includes a final, even parity, bit to maintain the balance of said line~
The invention also provides apparatus comprising a serial
ddta bus and at least two terminals coupled thereto each for transmitting
data bytes of a digital data signal thereon, each terminal comprising:
first means for providing each data byte ~or transmission bit-serially
with magnitude bits first, in order of decreasing significance, and any
sign bit following the magnitude bits; second means for applying a pulse
to ~he bus in respons~ to each serial bi~ which is a binary one; third
means for inhibiting the application of pulses ~o the bus by the second
means, for the remainder sf the current byte~ in response to a pulse
occurring on the bus during a serial bit which is a binary zero; and means
for synchronizing the first means so that ~h~ terminals transmit data
bytes simultaneously and in synchronism; whereby only ~he greatest
magnitude data byte, of data bytes for simultaneous ~ransmission from a
plurality of the terminals, is fully transmitted ~o the bus. At least one
terminal is preferably a telephone.
Preferably each terminal further comprises receiving means9
responsive to the third means, for receiving from the bus da~a bytes which
have not been transmi~ted by that terminal. In this case preferably the
third means comprises means For enabling the second means and inhibiting
the receiving means at the start of each data byte, and for inhibiting the
second means and enabling the receiving means in response to a pulse
occurring on the bus during a binary ~ero serial bit provided by the first
means.
Preferably the bus comprises a balanced two-wire line and
the second means oF each terminal applies pulses to the bus with
alternating polarity. Preferably also, for each terminal~ the first means
~ncludes means for providing each data byte for transmission with a final
par~ty bit so that each byte has even parity, and the second means is
arranged to apply the first pulse of each data byte to the bus with a
predetermined polarity.
The invention will be further understood from the following
description with reference to the accompanying drawings, in which:
Fig. 1 schematically illustrates an arrangement oF terminals
in~erconnected via a time compression multiplexed (TCM) bus J
~9~
Fig. 2 schematically illustrates an arrangement of terminals
interconnected via a bidirec;-tional bus;
Figs. 3 and ~ illustrate the principles of give-up and max
schemes used in the arrangements of Figs~ 1 and 2 in accor~ance with
embodiments o~ the invention;
Fig. 5 is a schematic circuit diagram illustrating part of a
terminal in the arrangement of ~ig~ 2~ and
Figs. 6 and 7 are timing diagrams illustrating operation of
the circuit of Fig. 5.
Referring to Fig. 1, two terminals A and B are each
connected via a serial data bus ~0 to a terminal C. The data bus 10 is a
time compression multiplexed (TCM) bus having an upstream channel from the
terminals A and B to the terminal C, and a downstream channel from the
terminal C to the terminals A and B, denoted in Fig. 1 by lines 12 and 1
respectively. The terminal C is coupled via a line 16 to a remote
terminal D~
In the following description, it is assumed that the
terminals A, ~, and D are digital telephones, and the termina'l C is a
network termination between the serial data bus 10 and a digital
subscriber loop constituting the line 16, the terminal D being coup'led via
a cligital telephone exchange (not shown). Such an arrangernent is known
for example from "ISDN Subscriber Loop Pro-tocol" by S~ Lacher et al.,
Internationdl Zurich Seminar on Digital Communications, March 19~2.
However, the terminals need not necessarily be digital telephones, and
instead may be any type of digital terminal,
In analog te7ephony, two telephones can be connected in
parallel on the same subscriber line and can be used simultaneously, with
their signals superimpose~, witho~t any problems. This manner of
providing analog extension telephones can not, however, be applied to
digital telephones. For example~ if the terminals A and B of Fig~ 1 were
used simultaneously as digital extens-ion telephones, digital signals
transmitted by the two terminals ~ and B would corrupt one another on the
upstream channel 12. Accordingly, a difficult problem arises in providing
digital extension telephones.
The present invention enables -this problem to be overcome
expedient'ly, as described in detail below. Furthermore, embodiments of
the invention enable the same channel to be used for distribution of
signals on the bus in both directions. This is illustrated in the
arranyement shown in Fig. 2.
The arrangement in ~ig. 2 differs from that of Fig. 1 in
that all of the terminals ~, B, and C are coupled in the same manner to
the serial data bus 10~ on which in this case the same channel is used for
both transmission directions between the terminals. Thus the arrangement
of Fig. 2 requires only half the bandwidth on the bus 10 of that required
by the TCM arrangelnent of Fig. 1~ The manner in which this is achieved is
expl di ned in detail below.
2~ Not all of the termina'ls A to C need be provided;
oonversely, more than three terminals could be coupled to the bus 10.
Sinlilarly, the terminal D cou'ld be extended by a bus arrangement like that
of ~;he terminals A to C.
The inven-tion is based on two schemes9 which are referred to
herein as the "give-up" scheme and the "max" schemeO These are explained
below with reference to Figs. 3 and 4. In order to implement these
schemes, each terminal transmits each byte to the bus 10, bit~serially
with the magnitude bits first, in order of decreasing significance~ and
any sign bit last~ In addition, the terminals are synchronized with one
another so that corresponding bits ~ransmitted by different terminals are
transmitted at corresponding times.
The bus is arranged so that a logic "1" on the bus overrides
a logic "O"; thus the bus 10 acts as a distributed wired-QR gate. Each
terminal is arranged to transmit the bits of each byte to the bus
regardless of the possible presence of other terminals, except that each
terminal monitors the state of the bus whenever the terminal transmits a
"O". If it detects a "1" on the bus during this monitoring the terminal
transmits "O"s for the remainder of that particular byte; in other words,
it gives up transmission of its own byte.
In consequence, if a plurality oF terminals try to transmit
respective bytes silnultaneously to the bus~ then the byte which has the
maximum value remains on the bus, and each terminal which tries to
transmit a byte of smaller value gives up its transmission at some point
wi-thout affecting the byte on the bus.
For example, with reference to Fig. 3, suppose that the
terminals A and B simultaneously wish to transmit to the bus 10 the bytes
11001011 and 10111010 respectively, the bits being in order of decreasing
si(Jnificance as described above and as shown in Fig. 3. During the most
signi~icant bit (MSB) time, both terminals transmit a "1" to the bus.
During -the next bit time, the terminal B transmits d l'UII and monitors the
state of the bus, whereas the terminal A transmits a "1" which prevails on
the bus and is consequently seen by the terminal B. In corsequence~ the
terminal B gives up transmitting its byte3 as sh~wn by a broken line in
Fig. 3. The terminal A continues transmitting its byt~, and during the
~s~
"0" bits sees only "O"s on the bus because the terminal B is no longer
transmitting (i.e. is transmitting zeros), so that the byte from the
terminal A is ~ransmitted on the bus. This process is repeated
individually for each byte.
As can be seen from the above description, the maximum
magnitude byte remains on the bus at all times. Referring to Fig. 4, if
signals to be transmitted by the terminals A and B are represented by the
dashed and dvtted lines respectively, and the lines on the horizontal axis
t represent sampling instants9 then the successive bytes which remain on
the bus are represented by the large dots and correspond to an envelope
signal shown by a solid line. Thus the max scheme is implemented, each
byte on the bus being the maximum of those from the terminals A and e. In
other words each byte is represented by A MAX B for two transl~itting
terminals A and 3 as shown in Fig. 1, or A MAX B MAX C for three
transmitting terminals as shown in Fig. 2.
Fig. 5 illustrates in detail circuitry of a terminal A, B,
or C for the arrangement of Fig. 2. This circuitry is equally applicable
to the terminals A and B for the arrangement of Fig. 1, except that in
these terminals the receive circuitry would be separate to receive signals
from the separate downstream channel 14. The terminal C in Fig. 1 does
not require the give-up scheme circuitry because no other terminal
competes with it for transmitting on the downstream channel 1~.
Referring to Fig. S, the bus 10 is illustrated as being in
the form of a 2-wire balanced line, as is conventional for analog
telephony~ comprising wires 18 and 20. Signals from a transmit path 22
are coupled to the bus 10 via a J-K flip-flop 23, two line drivers 24~ and
a transformer 25, and signals on the bus 10 are coupled to a recei~e path
26 via the transformer 25, resistors 28, voltage-limiting diodes 29, and a
rectifying differential amplifier 30 which converts bipolar signals on the
bus 10 into rectangular unipolar pulses on the path 26. The signals on
the transmit path 22 are produced from signals on a lead 32 by an AND ga~e
36 when a transmit enable signal TE on a lead 34 is a logic "1".
A synchroniziny circuit 42 is supplied with the signals on
the receive path 26 and serves in known rnanner to regenerate timing
signals START, CK9 SM, and STOP which are shown in each of Figs~ 6 and 7
ancl which are further described below. The signal SM is applied via a
lead 62 to a strobe input ST oF the amplifier 30 and to a clock input C of
a shift register 44, to shift the bits of each byte on the receive path 26
into the shift register 44 via a serial input SI. The signal CK is
applied to a clock input C of a shift register 46 to shift the bits of
each byte to be transmitted from the shift register 46 via a serial output
SO to the lead 32. A parallel input PI of the shift register 46 is
coupled via 8 lines 48 to d transmit port T of a codec (coder-decoder) 50,
which has a receive port R coupled to an 8-bit parallel output PO of the
shiFt register 44. The sign bit connections between the ports T and R of
the codec 50 and the respective shi~t registers 44 and 46 are ~Icrossed
~O overll the magnitude bit connections to relate the desired bit order ir.~ the
shift registers (sign bit last) correctly to that required by the codec
50. The codec 50 is coupled for example to a telephone dial pad and
handset 51 to constitute a digital telephoneO
The signal START produced by the synchronizing circuit 42 is
supplied via a lead 58 to load inputs L of the shift register 46 and LT o~
the codec 50, to cause an 8-bit byte to be transmit-ted to be loaded from
the codec 50 into the shiFt register 46 in response to the signal START
s~
becoming a logic "0"~ A pari~y generator 49 associate~ wi~h the shift
register generates a ninth, parity, bit to produce in the shift register
46 a 9-bit byte which has an even number of logic "l"s, As explained
further belowl this ensures that d.c. balance of the bus 10 is maintained.
The 8 non-parity bits of a 9-bit byte received via the receive path 26 and
shifted into the shift regis~er ~4 are loaded into the codec 50 in
response to the signal STOP, produced by the synchronizing circuit 42 and
supplied via a lead 66 to a load input L~ sf the codec 50, becoming a
logic "1", provided that a signal applied to a load enable input LE of ~he
co~lec 50 by an AND gate 52 is also a logic "1". The AND gate 52 is also
supplied with the signal STOP from the lead 66 and controlled by a signal
on a lead 54, which signal is complementary to the ~ransmit enable signal
TE on the lead 34.
The leads 34 and 54 are connected to the outputs Q and Q,
respectively~ of a flip flop 56, whose state is controlled by the signal
STOP supplied to a reset input R From the lead 58, and by a give up signal
GU produced by a NAND gate 60 and applied to a set input S. The gate 60
has two inputs, to one of which is supplied the signal SM from the lead 62
and to the other of which is applied the output of an exclusive-OR gate 6
whose inputs are connected to the receive path 26 and the lead 32.
As illustrated in Fig. 5~ the signal CK is also supplied to
an input of the AND gate 36, the output signal AO of which is supplied via
the transmit path 22 to a clock input C of the flip-flop 23 and to enable
inputs E of the line drivers 24. The signal START on -the lead 58 is also
supplied to a set input S of the flip-flop 23, the outputs Q and Q of
which are connected to inputs of the line drivers 24 ~hich produce drive
signals Q1 and Q2 to drive the bus 10 via the transformer 25
~s~
The gates 60 and 64 and the flip-flop 56 serve to control
the gates 36 and 52 in such a manner that if a particular byte being
transmitted from the shift register 46 is not exceeded in magnitude b~
another byte simultaneously applied to the bus 10 from another terminal
connected thereto, then the signal TE is a logic "1" so that this
particular byte is fully transmitted but no byte is received by the codec
50 because the gate 52 is not enabled. Conversely, i~ the particular byte
being transmitted is exceeded in magnitude by a byte simultaneously
applied to the bus 10 by another terminal, then the signal TE becomes a
logic "0" to inhibit the gate 36 to give up the transmission of the byte,
and the gate 52 is enabled to allow the maximum magnitude byte on the bus
to be received by the codec 50.
Thus the codec receives only those bytes on the bus 10 which
it has not transmitted, and the bytes transmitted by the codec 50 only
prevail on the bus 10, to enable them to be received by other -terminals
connected to the bus9 if they are not exceeded in magnitude b~
simultaneous bytes transmitted by such other terminals. This alternative
full transmission or recep-tion of bytes in a particular terminal, which is
further described below with reference to Figs. 6 and 7, enables the same
channel to be used for both directions of transmission on the bus 10, with
the bandwidth-saving advantage already mentioned.
Each of Figs. 6 and 7 illustrates the signals START, CK, SM,
and sroP produced by the synchronizing circuit 42, a serial output signal
S0 produced on the lead 32 by the shift register 46, the gi~e-up signal GU
produced by the gate 60, the transmit enable signal TE produced on the
lead 34, the signal A0 produced by the gate 36~ the signals Q1 and Q2
produced by the line drivers 24~ a bipolar or alternate-mark-inversion
~9~8
(AMI) signal present on the bus 10, and the consequent serial input signal
SI produced by the amplifier 30 on the receive path 26 and applied to the
serial input of the shift register 44, Fig~ 6 illustrates the case of
full transmission of a byte to the bus lQ, and consequently no reception
of this byte by the codec 50, and Fig. 7 illustrates the case in which
give-up of the transmission of a byte to the bus 10 occurs, with
consequent reception by the codec 50 of a greater magnitude byte
prevailing on the bus 10.
Referring to Fig. 6, for each byte each of the signals CK
and SM comprises a sequence of 9 pulsesO On each rising edge (O-to-1
transition) of the signal CK a bit is clocked out of the shift register 46
to the lead 32, and on each falling edge (l-to-O transition) of the signal
SM a bit is clocked from the receive path 26 into the shift register 44.
Prior to the pulses the signal START=O occurs on the lead 58~ in response
to which a byte for transmission is loaded from the codec 50 into the
shift register 46, the flip-flop 56 is reset to produce the signal TEa1 on
the lead 34 to enable the gate 36 for such transmission~ and
correspondingly to disable the gate ~2 via the lead 54, and the flip-Flop
23 is set to ensure that the first logic "1" bit of the byte for
transmission is represented by a positive AMI pulse on the bus 10.
In Fig. 6 it is assumed that the byte 11010011 is loaded
from the codec 50 into the shift register 46 For transmission, and that no
greater magnitude byte occurs on the bus 10 simultaneously to cause
transmission of this byte to be given up. Consequently with the final,
parity, bit the shift register 46 contains the 9-bit byte 110100111, as
shown in solid lines in Fig. 6 for the signal SO~ For each logic 1 of
this byte, with the signal TE=1 the gate 36 produces a pulse of the signal
s~
AO, the falling edges (1-to-0 transitions) of which pulses toggle the
flip-flop 23 to produce alternate logic l'1l' pulses of the drive signals Q1
and Q2 as shown in Fig. 6s The characteristics of the transformer 25 and
its coupliny to the bus 10 are selected in known manner to cause the drive
signa1s Q1 and Q2 to produce on the bus 10 the resultant AMI waveform
shown in Fig. 6. When not enabled, the drivers 23 have high output
impedances, so that during each "O" bit of the byte the amplifier 30 can
properly monitor any signals on the bus 1~. The resultant amplified and
rectified signal SI on the receive path 26 has the waveform shown in Fig.
6.
The exclusive-OR gate 64 produces a logic 1 output whenever
the signals SO for transmission and SI on the receive path differ from one
another. If such a difference occurs during a sampling time in the middle
of a bit duration, when the signal SM=1 enables the gate 609 then the gate
60 produces a logic O (signal GU) outpu~ to set -the flip-flop 56 to give
up transmission and enable reception of a byte. As illustra~ed in Fig. 6,
this does not occur, so that the byte is fully transmitted, and reception
of this same byte by the codec 50 is prevented, as is desired.
The ~-bit byte 11010011 1 oaded from -the codec 50 into the
~0 shift register 46 for transmission as illustrated in Fig. 6 has an odd
nulnber of logic 1 bits. The parity bit added by the parity generator 49
provides an even number of logic l bits in the transmitted 9-bit byte, so
that there are equal nulrlbers of posi-tive and negative pulses on the bus
10, whereby the balanced state of the bus is maintained. In order to
avoid cancellation of logic 1 bits from different terminals, which would
occur on the bus 10 if two different terminals simultaneously transmitted
logic 1 bits with opposite polarity pulses, each terminal is arranged to
transmit khe ~irst logic 1 bit of each byte as a positive pulse on the bus
10, as shown in FigO 6. This is achieved by the initial setting of the
flip-flop 23 by the signal START as described above.
Thus the transmissicn of the additional, even parity~ bit
ensures that the bus 10 does not become unbalanced~ Furthermore, the
transmission of the first logic 1 bit of each byte always with the same
polarity (positive as described here9 but it could alternatively be
negative) avoids cancellation of pulses from difFerent -terminals without
requiring each terminal to monitor the state of the bus continuously.
Such monitoring would result in undesired complexity of the terminals and
prevent their portability, which is undesirable for the case of
remote-powered terminals, such as digital telephones~
IF, instead of being as described above, the 8-bit byte
loaded into the shift register 46 from the codec 50 contained an even
number of logic 1 bits, then the parity bit would be a logic O. This is
illustrated by the broken lines in Fig. 6l for transmission of the 8-bit
byte 11010010, illustrating that ayain in this case the balanced condition
of the bus 10 is maintained.
Referring now to Fig. 7, it is assumed that the ~-bit by-te
~O ll001000 is loaded from the codec 50 into -the shift register 46 for
transnlission as a 9-bit even parity byte 110010001, and tha-t the greater
magnitude 9-bit even parity byte 110100100 is simultaneously appliecl to
the bus 10 ~rom another terminal. The first three bi-ts of these bytes are
the same, so that transmission occurs as described with re~erence to Fig.
6~ The ~ourth bits are different. Thus during the fourth bit duration,
with the signal SM=1 on the lead 62, the exclusive-OR gate 64 produces a
logic 1 output and the give-up signal GU=O is produced to set the
14
c~
flip-flop 56. This also happens during the seventh bit duration, when it
has no effect because the flip-flop 56 is already set.
~ s a result of the setting of the flip-flop 56, the signal
TE=O is produced for the remainder of the byte, so that the gate 36 is
inhibited and the signal AO remains a logic O~ Consequently transmissior,
of the lower-magnitude byte is given up. In addition, via the lead 54 the
gate 52 is enabled so that with the signal STOP=1 at the end of the byte
the 8 non-parity bits of the 9-bit received byte 110100100 prevailing on
the bus 10 are loaded into the codec 50 from the shift register 44.
Although par~icular embodiments of the inven~ior have been
described in detail, it should be appreciated that numerous modifications,
variations, and adaptations ma~ be made thereto without departing from the
scope of the invention, which is defined by the claims.
In particular, for example, it is observed that -the bus may
comprise an optical fiber, instead of being an electrical line as
described above, and the means in each terminal for applying pulses -to the
bus may comprise means for applying op~ical pulses to the bus. In such an
arranyement the additional 9 parity, bit of each byte described above may
be omitted, and the optical pulses rnay be unipolar, because there is no
2() need to maintdin a balanced condition of an optical bus. The bus would in
this case have to be appropriately arrangedD with optical reflectors
and/or splitters, to convey the optical pulses in both directions on the
bus between arbitrary terminals coupled thereto.
