Note: Descriptions are shown in the official language in which they were submitted.
5~34
Polycrystalline Thin-film Transistor
The present invention relates to a transistor, the
material of which is a polycrystalline semiconductor layer
formed on an insulating body.
The transistor of the present invention is useful
when utilized as, for example, a semiconductor device that
is unitary with the displaying substrate of a flat display
device employing liquid crystal, electroluminescence or
the like and which drives the display device.
As a flat display device employing liquid crystal,
there has heretoore been adopted a system wherein, on a
substrate, e.g., a single-crystal Si substrate, an integrated
circuit is formed in which a two-dimensional switching matrix
of MOS transistors and peripheral scanning circuitry are
made unitary, and wherein the liquid crystal that fills up
the interspace between the single-crystal Si integrated
circuit elements and counter electrodes is driven by the
single-crystal Si integrated circuit elements. In this case,
since the substrate is the single crystal~ the size of the
substrate that can be prepared is limited. Hence, the size
Of the screen of the display device that can be fabricated
is limited. By way of example, the maximum diameter of a
Si wafer that can be produced at present is 5 inches, so
that a screen of a size corresponding to a cathode-ray tube
larger than the 5-inch type cannot be fabricated. It is a
serious disadvantage that a large area cannot be attained as
~ a picture device.
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To the end of eliminating this disadv~ntage, there
has also been proposed a method according to which an
amorphous semiconductor layer or a polycrys~alline semi-
conductor layer is formed on an amorphous substrate and
integrated circuit elements as described above are formed
by employing the amorphous semiconductor or polycrystalline
semiconductor as the material thereof and are used for
driving a flat display device. Since, in this case, the
semiconductor layer is formed on the amorphous substrate by
a process such as vacuum evaporation, a large area in excess
- of a diameter of 5 inches can be attained and the area of
the flat display device can be made relatively large.
When employing an amorphous semiconductor layer,
however, the carrier mobility of this layer is conspicuously
low and leads to the disadvantage that the characteristics
of the transistors formed in the layer are inferior. On
the other hand, when employing a polycrystalline semi-
conductor layer, the carrier mobility is high enough to ba
used as the display device. However, if the grain size and
the curren~ path (channel) length of the element are
approximately equal, the presence of a grain boundary leads
to the disadvantage that the characteristics of the
respective fabricated elements disperse. More specifically,
the current path of a certain element can traverse the grain
boundary, whereas the current path of another element does
not. Thus, the conduction of carriers i5 affected by the
grain boundary in some elements and not in the others~ As
a result, the individual transistor elements differ in kheir
characteristics, for example, transconductance.
As examples of polycrystalline silicon devices, there
can be mentioned those described in the following references:
(1) THIN-SOLID FILMS, vol. 35, June 1976, No. 2, pp. 149-153
(2) ELECTRICAL DESIGN NEWS, vol. 18, no. 13, July 1973,
pp. 30-31
(3) IBM TECHNICAL DISCLOSURE BULLETIN, vol. 14, no. 10,
March 1972, pp. 2900-2901
(4) Applied Physics Letters, vol. 35, 15th July 1979, no. 2,
pp. 173-175
~.~957~
~5) IBM TECHNICAL DISCLOSURE BULLETIN, vol. 17, No. 8,
January 1975, pp. 2455-2456
(6) SOLID STATE ELECTRONICS, vol. 15, No. 10, October 1972,
pp. 1103-1106
An object of the present invention is to avoid or
minimize the disadvantages of the prior art described above by
providing a thin-film transistor having excellent transistor
characteristics and assured uniform characteristics.
To this end the present inven~ion consists of a poly-
crystalline thin-film transistor wherein a polycrystalline
silicon layer is formed on a substrate, said layer including
at least a pair of electrode regions for causing carriers to
move, and a gate electrode, wherein the length of each region
in which the carriers move is at least 50 times greater than
the mean gLain size of the polycrystalline silicon in the
general moving direction of the carriers, and said mean grain
size is not less than 150nm in at least each said region.
In the drawings which show embodiments of the
invention
Figure 1 is a graph showing the relationship between
the thickness of an evaporated layer and the grain size;
Figures 2a - 2h are sectional views showing a process
for producing a MOSFET by the use of a polycrystalline semi-
conductor layer;
Figure 3 is a characteristic diagram of a MOSFET of
an embodiment of the present invention; and
Figure 4 is a graph showing the relationship between
the mean grain size and the transconductance.
As stated above, when a polycrystalline semiconductor
layer is formed on a predetermined substrate and a semi-
conductor device is formed using the polycrystalline
semiconductor layer, the present invention is characterized
in that at least the length of a region in which carriers
range (the channel length) is made equal to or greater than 10
times the grain size (the longer diameter when a crystal grain
is flat). In the specification and claims, the grain size
~.~ 357~
shall signify the "mean grain size".
More specifically, the characteristics of elements
depend upon the number of grain boundaries that the
carriers encounter in the course of ranging. Since a
sufficiently large number of crystal grains exists in the
region in which the carriers range, these carriers are
affected by a large number of grain boundaries. Therefore,
when a large number of semiconductor devices are manufactured,
their characteristics have good uniformity. From the view-
point of the dispersion of the characteristics, it ispreferable that the length of the region in which the
carriers range is equal to or greater than 50 times the grain
size, so that any dispersion of the characteristics can be
better suppressed.
On the other hand, however, if the grain size is too
small, the characteristics (for example, the mobility of the
carriers) of the semiconductor material degrade. For this
reason the grain size should preferably be at least 150 nm.
Of course, even if the grain size is smallex than
this value, the relationship between the length of the
ranging region of the carriers and the grain size is useful
for reducing dispersion of the characteristics of the
elements and rendering them uniform.
A semiconductor layer having a mean grain size of
or below approximately 300 nm is desirable for ease of
manufacture. Such a siz~ can be satisfactorily achie~ed
and controlled by evaporation in an ultra-high vacuum, as
described below.
If the length of the ranging region of the carriers
(in, for example, a field effect transistor, the length
corresponds to the channel length) is determined in advance
in the circuit design of a semiconductor device, the poly-
crystal grain size can be adjusted accordingly. On the
other hand, if the grain size is limited by any restriction
imposed by the formation of the polycrystalline layer, the
elements and the circuit need to be designed in conformity
with such limited grain size.
As thus far described, it is important to construct
~ ~ ~5~
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a semiconductor device by employing a polycrystalline semi-
conductor that has a mean grain size of at least 150 nm,
i.e., a polycrystal in which most grain sizes are at least
150 nm, and under the condition that the length of a
region in which carriers range is at least 10 times greater
than the mean grain size in the substantial ranging direction
of the carriers.
The length of the ranging region of the carriers has
no theoretical upper limit in design, but it will be at most
100 ~m in practical use. In addition, although the lower
limit of the grain size is difficult to set specifically,
the mobility of the carriers can be secured with grain sizes
of at least 100 A in practical use. Accordingly, the ratio
between the length of the ranging region of the carriers and
the grain size will become 10,000 or so as its upper limit in
practical use.
The thickness of the semiconductor layer may be at
least 100 nm, because a channel may be formed in the layer.
Further, a thickness of at least 500 nm is preferable~
Useful as the substrate is an amorphous or poly-
crystalline substrate such as a glass substrate or a ceramic
substrate. One consideration is price, and the glass sub-
strate is inexpensive. Further, it ena~les use of a light-
` transmitting substrate.
It is also important for realizing semiconductor
devices of slight dispersion that the ratio (Csub/Csemi)
between the coefficient of thermal expansion (Csub) of the
substrate and the coefficient of thermal expansion (Csemi)
of the semiconductor material is set within a range of from
0.3 to 3Ø Although details of the physical reason for
this requirement are not clear, it is based on the stressed
state of the semiconductor layer attributed to the difference
of the coefficients of thermal expansion of the substrate
and the semiconductor layer.
The preferred method of evaporating the polycryst-
alline semiconductor layer is as follows.
A vacuum evaporator capable of attaining an ultra-
high vacuum, which may be a conventional evaporator, is used
The degree of vacuum during evaporation is kept so high that
the pressure is below 1 x 10 8 Torr. Further, oxygen in the
residual ~as during evaporation has particularly undesirable
effects on the characteristics, so that the partial pressure
of oxygen is kept below 1 x 10 Torr. The evaporation rate
is 1,000 ~/hour to 10,000 A/hour.
As regards control of the grain size, this can be
accomplished by controlling the ~hickness of the evaporated
layer, the temperature of -the substrate, the rate of
- evaporation and the degree of vacuum. Figure 1 is a graph showing the relationship between the thickness of an
evaporated silicon layer and the mean grain size thereof, the
layer having been evaporated under the conditions of a sub-
strate temperature of 600 C, an evaporation rate of 5000
~/hour and a vacuum during evaporation of 8 x 10 9 Torr.
The thickness of the layer was measured with a quartz
oscillator.
In some cases, the grain size can be controlled by
such means as laser annealing.
To fabricate a semiconductor device by processing a
polycrystalline silicon layer, several steps of manufacture
must be performed. Heat-treatment temperatures in these
steps are kept below 820 C, this being the softening point
of very hard glass, to enable the advantages of the present
invention to be fully exploited. When employing a glass
substrate of low softening point, the heat-treatment
temperatures should be kept still lower, for example, below
550 C. The following description relates to a case in
which a MOS field effect transistor is formed on a glass
substrate of low softening point.
In producing a gate insulator, the thermal oxidation
of a silicon substrate is ordinarily resorted to. Since,
however, thermal oxidation requires a high temperature of
at least 1000 C, it cannot be used for the present purpose.
In this example, Si~4 and 2 are reacted at a
temperature of 300 C to at most 500 C, or SiH4 and NO2 are
~.3 ~
-- 7 --
reacted at a temperature of 400 C to at most 800 C, whereby
an SiO2 film is formed by chemical vapor deposition. This
SiO2 film is used as the gate insulator.
To form a source region ancl a drain region, the
method of forming p~ layers or n~ layers by thermal diffusion
has heretofore been commonly adopted. Since, however, this
method requires a heat treatment at about 1150 C, it cannot
be used for the present purpose of forming a transistor on
a glass substrate of low softening point. In the present
method, thermal diffusion is replaced by the method of forming
p layers or n layers by ion implantation. After ion
implantation, heat treatment for electrical activation is
performed. The temperature of this heat treatment needs to
be kept lower than the softening point of the substrate usedO
Therefore, there is adopted, for example, a method in which
ions such as BF2+ are implanted, permitting high activation
through heat treatment at a low temperature of about 550 C,
or a method in which, after ions such as B+ are implanted,
a heat treatment is performed at a temperature of about 500 C-
600 C immediately before the reverse annealing effect takesplace. In the case of P ions, As ions, etc., the reverse
annealing effect is not so remarkable as in the case of the
B ions, but the impurities can be satisfactorily a~tivated
by heat treatment at about 500 C - 600 C. Accordingly, both
the p+ layer and the n+ layer can be formed by a low~temper-
o oature process at about 500 C - 600 C. When employing a
substrate (such as very hard glass) whose softening point is
higher than 800 C, it can of course be heat-treated at a
temperature of 800 C.
By employing this manufacturing method, the semi-
conductor layer can be made large in area or elongate, and
a semiconductor material having a carrier mobility of at
least 1 cm2/V.sec can be produced.
A specific embodiment of the present invention will
now be described in detail.
Referring to Figures 2a - 2h for explaining the
manufacturing steps, there will be described an n-channel M~S,
57~
field effect transistor having a structure wherein a poly-
crystalline silicon layer is formed on a glass substrate and
a channel is provided in the surface of the silicon layer.
First, a substrate is set in a vacuum evaporator
that can achieve an ultra-high vacuum~ The evaporator may
be a conventional one. On the glass substrate 1
(aluminosilicate glass; coefficient of thermal expansion =
32 x 10 7/ C) a silicon layer 2 is deposited to a thickness
of 1.5 ~m by vacuum evaporation with a substrate temperature
of 600 C, a vacuum during evaporation of 8 x 10 9 Torr and
an evaporation rate of 5000 A/hour (Figure 2a). The layer 2
so formed is of p-type polycrystalline silicon, slightly doped
with boron and having a grain size of about 2000 A and a
carrier mobility of about 2 cm2/V~sec. The coefficient of
thermal expansion of this silicon layer is about 25 x 10 7/
C (300 K).
Subsequently, an SiO2 film 3 is deposited to a thick-
ness of 5000 A by vapor growth at a substrate temperature of
400 C tFigure 2b). Next, as shown in Figure 2c, the film 3
is provided with windows for source and drain regions, the
interval between these regions being 20 ~m. Accordingly,
the channel length of the MOS field effect transistor
becomes 20 ~m. Subsequently, P~ ions having energy of 100
keV are implanted at a dose of 1 x 1016 /cm 2, and the
resultant substrate is heat-treated in an N2-atmosphere at
600 C for 30 minutes, whereby n+ layers 4 are formed in the
source and drain regions (Figure 2d). At the next step, as
shown in Figure 2e, the film 3 is removed with a field oxide
film 5 left behind. An SiO2 film 6 is deposited for a gate
oxide film to a thickness of 7500 A b~ chemical vapor
deposition (Figure 2f). Further, electrode contact holes
are provided, as shown in Figure 2g, by a photoetching
process. After Al has been evaporated on the whole surface,
it is processed by photoetching, to form a source electrode
7, a drain electrode 8 and a gate electrode 9 (Figure 2h).
Thereafter, the resultant assembiy is heat-treated in an
H2-atmosphere at ~00 C for 30 minutes. By the above steps,
~.~95~
g
a thin-film MOS field effect transistor has been fabricated
in which a channel 20 llm long is provided in the surface of
the polycrystalline silicon layer. This semiconductor device
exhibits ~ood and stable characteristics as the transistor.
Figure 3 shows an example of the characteristic at
room temperature of a MOSFET actually manufactured by wa~
of experiment. The characteristic is the drain current ID
versus the drain voltage VsD with a third parameter being
the gate voltage VG.
In this example, the grain size is approximately
2000 A with respect to the channel length of 20 ~m.
Accordingly, a sufficiently large number of crystal grains
exists in the ranging direction of carriers, and the carriers
are influenced by a large number of grain boundaries. The
effect is that, when a large number of elements is
manufactured, their characteristics become uniform.
Silicon lavers having various mean grain sizes were
formed, and semiconductor devices similar to the above were
manufactured. The transconductances of the devices were
compared, and the results of the comparisons are illustrated
in Figure 4. In this figure, the values of the trans-
conductances are given as relative values by making the
typical value of the transconductance of the layer having
a grain size of 150 nm unity. It is apparent that, when
the mean grain size is less than 150 nm, the transconductance
drops sharply. MOS field effect transistors ~aving various
gate lengths were manufactured using semiconductor layers
whose mean grain sizes were 150 nm, 200 nm and 300 nm, and
the dispersions of the transconductances of the transistors
were tested. When the ratio of the ranging distance of
carriers to the mean grain size was below 10, a dispersion
of the order of ( 1) was exhibited with respect to trans-
conductance (relative value) = 1. The condition of trans-
conductance = 0 signifies that operation is, in effect,
impossible.
On the other hand, when the above ratio was 10 to 50,
-- 10 --
dispersion was of the order of +0.7 to +0.8, and when the
ratio exceeded 50, dispersion was of the order of tO, 3 to
+0.4. Even when the ratio was approximately 200 to 1000,
dispersion was of the order of +0.3 to ~0.4.
It is accordingly understood that the ratio between
the ranging distance of carriers and the mean grain size
ought to be made at least 10, preferably at least 50.
Similar MOS field ef~ect transistors were manufact--
ured using various examples of substrates, and their trans-
lC conductances (gm) were measured. The results are listed in
Table 1. In the manufacture, heat treatments were carried
out at temperatures not higher than 500 C. With quartz glass
or soda-lime glass, a transistor having good characteristics
cannot be produced. The ratio between the coefficients of
15 thermal expansion of the substrate and the semiconductor
layer to be placed ther~on should be set at a predetermined
favourable value.
Table 1
Coefficient of
of substrate Ratio ~m
Substrate ( 10-7 = Co (Sub) (VG = 10 V)
quartz glass 5.5 0.22 1 to 9 ~s
boro-silicated
glass (I) 32 1.28 10 to 50 ~s
boro-silicated
glass (II) 46 1.84 10 to 100 ~s
boro-silicated
glass (III) 50 2,0 10 to 100 ~s
aluminosilicate
glass 54 2.16 10 to 100 ~s
soda-lime glass
(I) 87 3.48
soda-lime glass
(II) 94 3.76
