Note: Descriptions are shown in the official language in which they were submitted.
-1- RCA 77254 DIV A
1 ADAPTIVE RECONSTRUCTION OF l'HE COLOR
.
CHAN~ELS OF A COLOR TV SIGNAL
.... _ ...
The present invention is divided from application
serial no. 406241,29 June 1982, and relates to transmission
systems and more particularly, to plural channel color
television systems with different channel bandwidths.
A props~ed televi~ion syst~m has a wide
bandwidth lumin~nce e:hannel llnd narrow-~andwidth c:hroma
channel~. In p~rtic:ular, the lumirlance channel is
10 ~ampled ~t iEour t~n~s the ch~oma subcarrier fre~uency,
while two chroma chans!els are sampled at only twice
s~id ~requency ts~ co:n3erve bandwidth; this is known as the
4: 2: 2 ~ystem. ~owever, in this ny6tem the c:olor ~ignal
resolution is llmited to one hal the l~amina~ce signal
15 re~olution to avoid aliasing in the narrow bandwidth
color chann~ls.
It i~ therefore desira~le to have a system
where all channels have a more nearly equal resoluti~n
without increasing the bandwidth of the charlnel through
2 0 which ~hey pass .
In accordalnce with the principles of the
invention of the parent ap?lication,
aliases are removed from at least a first component
signal o~ a video signal, using one alias-free component
~5 of said video signal, by determining from said
alias free component the directioll of least resolution
and averaging said ~lias containing component in said
direction .
The present invention relates to a method and
apparatus for encoding the video signal in a novel manner
permitting such alias removal to be readily achieved on
decoding.
According to the invention, a video signal having
at least two CompQnents is encoded by periodically sampling
35 at least a first signal component with offset samples, said
first signal component having frequency componen-ts that can
exceed one half the sampling frequency, and sampling a second
signal cornponent at a frequency at least about -twice the
maximum of its highest frequency and about twice the sampling
~ 3
. -2- RCA 77254 DIV A
1 frequency of said first cornponent signal.
In the drawings:
Figure 1 shows an encoder in accordance with the
invention,
Flgure 2 shows sample patterns on a scanning
raster; and
Figure 3 shows a decoder in accordance with the
invention;
Figures 4,5,6 and 7 illustrate block diagrams of
filters used in Figure 3;
Figure 8 shows a block diagram of a minimum-error
l~gic circuit used in FIGURE 3;
Figure 9 shows a block diagram o~ a digital delay
line used in Figures 4-7;
In Figure 1, Y (luminance) and I and Q (chrominance)
signals are applied to ~PFs ~low pass filters~ 1601, 1603,
and 1605 respectively~ The output signals fr~m the LPFs
1601, 1603 and 1605 are applied to ADCs (analog to
digital converters) 1607, 1609, and 1611, respectively.
20 A clock signal at about four times the color subcarrier
fre~uency ~4xSC) i~ generated by generator lS13 and applied
as a sampling signal to ADC 1607 and to divide-by-two
frequency divid~r 1615. The twice subcarrier fr~quency
~2xSC) from ~ivide~ 1615 is applied as a sampling
25 signal to ~DCs 1609 and 1611. The 8-bit output signals
from the ADCs compri~e digital samples of the analog
input signals. The po~ition of the Y signal samples
on a scanning raster is shown in FIGURE (a). The
exact value of the frequency of the clock signal from
30 generator 1613 is chosen to have an odd number of
samples in each scanning line~ This choice causes
the 2xSC sample~ of both the I and Q signals to be
alternate-line ofset with respect to signals of the
~ame type, as shown in FIGURE (b). Other ways of
35 achieving sample offset are known. For example, if
an even number of samples in each scanning line is
used, then the divided 2xSC clock signal can be "paled",
which is a shifting of the phase of the clock signal
by 180 degrees from line to line~
~10
~6~
-3- RCA 77,254 DIV A
1 In FI~URE 1 all of the LPFs have a cut-off
fxequency slightly less than 2xSCr Since the Nyquist
limit for the I and Q channels is about lxSC, aliasing
will occur in these channels which will be apparent upon
decoding. That is, the channel bandwidth allow~
p~ssage of signals sampled at rate~ at which alias
occurs. Howe~er, due to the phase offset depicted
in FIGVRE (b), the aliasing will usually occur in
a raster dixection other than the direction of the
10 high frequency (highest resolution) information. Thus,
it iæ usually possi~le to remove the aliasing by
filtering in the direction of the alia~.
Figure 3 shows a decod~r circuit for accomplishing
this. The 8-bit 4xSC rate Y signal from Figure 1 is applied
15 ~ia an equalizing delay line 641,to DAC (~igital to analog)
coverter) 1802 that provides the Y output signal, and also
both directly and via delay line 641 t~ a circuit
comprising filters 634, 636 and 640, comparators 642, 644,
646 and 648,and minimum
error loglc 650 which serves to detect in which
direction the Y signal has the least resolution
(least amount of change) and to provide a 2-bit outpu~
signal from logic 650 that conveys this information.
This information will be accurate since the sampling
rate for the Y signal satisfies the Nyquist criterion,
and therefore there is no aliasing in the Y channel.
-4- RCA 77,254 DIV A
1 Mbre part.icNlarly, in FIGURE 3 the 8-~it Y signal,havi~g samples
occurring, in a particular enbodiment, at 14.32 kHz~
are applied to a delay line 641 and to filters 634,636,63B
and 640. Ihes filters are used to provide the average of surrounding
samples in directions in which I and Q signal averages can be derived from
the transmitted I and Q signals for interpolation therewith~as will
be described. By "average" is meant adding together the signal values
represented by each of two 8-bit samples and then dividing the
resulting sum by two. Filter 634 suppli2s the average (a first " dia-
10 gonal" aver~ge~ of sa~ple points 12B and 130. ~hese points are spacedin time by two horizontal lines and four signal sampling intervals, which
corresponds to approximately 127 micr~econds, in the NTSC system, plus
280 nanoseconds. FIGURE 4 illustrates ~le details of filter 634, which
comprises a digital delay line 900 having~ a delay of
15 127 microseconds plus 280 nanoseconds coupled between input
terminals 632 and an input terlminal of a digital adder 902.
Undelayed signals from terminal 632 also are coupled to a
s~cond input terminal of adder 902. The digital sum of
these signals, corresponding to the video signals at
20 sample points 128 and 130, is obtained at the output
terminal of adder 902 and coupied to an input terminal of
a digital divider 904. Divider 904 divides this summed
signal by two to provide at its output terminal an ~-bi~
parallel signal representing the average signal of sample
25 points 128 ~nd 130. Tkis averayed signal is coupled to an
input terminal of a comparator 642 in FIGURE3 . Delay line
641 also comprises an 8-bit digital delay line and has a
delay of about 63.5 microseconds plus 140 nanoseconds.
This time is equal o one-half of the total delay of delay
30 line 900 of filter 634, and delays the video at sample
point 114 20 that it
I
1 - 5 ~ RCA 77,254
DiV A
will be in time coincidence with the aver~ged signal f~orn
filte~ 634, permittln~ the two signals to be compared by comparator
642. Filter 636 supplies the average of points 120 and 122
(a "horizontal" average)~ It comprises an 8 bit wide
diyital delay line 1002 in FIGURE 5 having a delay of
about 140 nanoseconds. The input (undelayed~ and output
(delayed) signals of this delay line are averaged by adder
~o 1004 and divider 1006. An ~additîonal equalizing delay of
one line plus 70 nanoseconds to oompensate for the delay
line 641 is provided by delay line 1000 within filter 636.
The output signal of filter 636 from divider 1006 is
supplied to a comparator 644 in FIGURE3 . Filter 638
supplies the average of diagonal points 124 and 126 (a
"second diagonal" average). It comprises an 8-bit digital
delay line 1102 in FIGURE 6 having a delay of two
horizontal lines minus 280 nanosecondsO The delayed and
undelayed signals are averaged by adder 1104 and divider
1106, while the digital signal from input 632 is first
delay equalized by a 280 nanosecond delay line 1100. The
output signal from divider 1106 is applied to a comparator
646 in FIGURE 3. Lastly~ filter 640 supplies the average
of points 116 and 118 (a "vertical" average). It comprises
an 8-bi~ digital delay line 1202 in FIGURE 7 having a
delay of two horizontal lines. The delayed and undelayed
signals are averaged by adder 1204 and divider 1206, while
the digital signal from input 632 is first delay eaualized
by a 140 nanosecond delay line 1200. The output signal
from divider 1206 is applied to a comparator 648 in
~IGURE 3.
FIG~RE 9 shows an 8-bit wide delay line for use
in the filters 634, 636, 638 and 640 and delay 641. It
comprises eight shift registers 1302, 1304, 1306, 1308,
1310, 1312J 1314 and 1316, each oE which receives one bit
of the 8-bits simultaneously present at input 1300. The
bits are shifted within the registers under the control of
a clock signal from clock 1338 coupled to shift inputs
1318, 1320, 1322, 1324, 1326, 1328, 1330, and 1334. The
3~
-- 6 ~ Ci~ 7 7, 2 5
DIV A
number of stages of the shift registers are chosen to
achieve the desired delay. The outputs of the shift
6 regis~ers are coupled ~o B-bit parallel output 1336.
Comparators 642, ~44, 646 and 648 e~ch comprise an B-bit
subtractor that also receivles the original 8-bit samples
through delay line 641 in addition ~o the OtltpU~s of
ilters 634, 636, 638 and $40 respectively. The respective
1~ two signals in each comparator are subtracted and then the
absolute value is taken of the resulting difference. The
comparatoxs apply absolute value signals to a minimum
~ error logic circuit 650~
As shown in FIGURE 8, minimum error logic
circuit 650 comprises Ç magnitude comparators B82, 884, 886,
888, 890 and 892, each of which receives two 8-bit numbers
from diffexent pairs of the output signals of comparators
642, 644, 646 and 648 and supplies at its respective
output a one-bit logic level indication to indicate which
of the two respective input num~ers is smaller~ It should
be noted that there are only six possible combinationc of
four numbers taken in pairs, thus giving rise to the six
magnitude comparators. It is only necessary to look at
three of the magnitude comparator outputs to determine if
a specific magnitude comparator input is the lowest. Thus
NOR gates 894, 896, and 898 are used to detect if the
output signal from comparators 642, 644, and 646
respectively are the lowestO If none are the lowest, the
output signal from 648 is assumed to be the lowest which
will be true, or none will be lowest, i.e., they are 811
equal, in which latter case the output signal from any
comparator ~ill do. The output signals from gates 894,
896, and 89B are coded by OR gates 800 and 802 into the
2-bit control signal on bus 604 in accordance with the
following truth table:
L~
-7-- RCA 77,254 DIV A
irl~ ~{). , __ _~_
_ 642
604a 1 0 1 0
604b 0 1 1 0
The output of logic circuit 650 comprises two bits in
accordance with the above table which i~dicate which of
the pairs of samples of adjacent points is the closest
match to sample point 114, i.e. represents ~hich direction
has the least change of the video signal around the sample
point 114.
Ihe 8-bit 2xSC rate I and Q signals from FIGURE 1 are
applied to respective circuits in FIGURE 3,ea~ comprising filters
762t 764, 766 and 768, to provide I and Q signa~ each averaged in
four directions. ~bre specifically the 8 bits representing an I or Q
sample of a picture point are applied to filters 762, 764, 766, and
768, the internal construc.ion of which is the same as filters 634,
636 368 and 640 respectively. Ihe same 8 bits are also applied to a
contact of an 8-bit swi-tch 770 through a delay line 706 that has the
same delay as delay line 641 and which compensates for the delay
through filters 762, 764, 766 and 768. A control decoder 772
respvllsive to the output from logic circuit 650 sets switches 1804
and 1806 to providR an output signal averaged
in the directon of least resDlution as determined
from the Y signal. The signal ~amples from switc~es 1804
~nd 1806 are interpolated between the signal sample~
from dPlay lines 706D This filtering removes aliasing
in that direction~ For example, if the scene is of
picket fence having vertically aligned picketsl
there is horizontal information and the aliases in
the I and Q signals are in the vertical direction. The
alias free Y signal indicates that ~he direction of
least resolution is vertical, and this is the direction
.in which lthe iEiltering is done, i.e. selected as output
signals by switches 1804 and lR06. Switches 770 are
~8 - RCA 77, 254 [~IV A
~wi~ched ~t 2xSC ~nd altern~te:ly proYide the delay equalized
2xSC ~ignal~ ~rom delay line~ 706, ~nd the 2xSC now
~s-iEres~ ~igllals from ~witches 1804 and 18D6~ Thus
high definition 4xSC rate 8ignalE; are applied to DAC~
1808 and 1810 in channels havin~ a barldwidth equal to
the ~ampling rate 9 ~ithout the ~dver~e eiE:ec~ of alias .
Therefore analog Y, I and Q signal~ are ~vailable at
the output~ of DACs 18û2 y l~lD8 and 1810 r2spectively O
ïnstead of I and Q ~ignals~ other color diff2renoe
10 ~3ignals, ~u~h a~ B~Y and R~Y, could have Ibeen u~ed.
