Note: Descriptions are shown in the official language in which they were submitted.
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HIG~-POWER DUAL-GATE FIELD-EFFECT TRANSISTOR
This invention is concerned with dual-gate
field-effect transistors (FET) and more particularly with
dual-gate FETs which produce high power ou-tput.
Known dual-gate FETs have the desirable property
of high gain at high frequencies, such as at Ku-band.
Furthermore, the gain can be varied by varying the bias
voltage on the second gate. Known dual-gate FETs have the
undesirable property of producing low output power of
approxlmately -ten milliwatts.
Known single~gate FETs, particularly of the type
described in U. S. Patent No. 3,993,515 which are "flip
chip" mounted, desirably can produce hundreds of
milliwatts of output power but cannot produce controlled
high gain at high frequency.
In accordance with a preferred embodimen-t of the
invention; an FET pellet has at least a drain pad and a
source pad and multiple electrodes connected to each of
said pads, has at least two gate pads and multiple gate
electrodes connected to each gate pad, and has multiple
other electrodes, and a transistor carrier comprises an
electrically insulative thermally conductive substrate
and, mounted thereon, a source terminal, a drain terminal,
a first gate terminal, a second gate terminal, and an
additional terminal. The carriex and pellet are arranged
such that: the drain pad of -the pellet is elec-tr~cally
connected to the drain -terminal of the carrier, the source
pad of the pellet is electrically connected to the source
terminal of the carrier, one of said ga-te pads of the
pellet is electrically connected to the firs-t gate
terminal of the carrier, another one of the gate pads of
the pellet is electrically connected to -the second gate
terminal of the carrier, and the o-ther electrodes of the
pellet are electrically connected to the additional
terminal of the carrier.
FIGURE 1 is a plan view of an FET pellet
conventionally used to crea-te a single gate power FET;
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FIGURE 2 is a cross section elevatlon view along
lines 2 2 of the FIGURE 1 FET pellet;
FIGURE 3 is a plan view of a single-gate power
FET carrier above which is positioned the FET pellet of
FIGURE 1, illustrated in phantom, in accordance with the
prior art;
FIGURE 4 is a cross section elevation view along
lines 4-4 of the FIGURE 3 carrier and the FIGURE 1 pelle-t
in accordance with the prior ar-t;
FIGURE 5 is an electrical schematic of a single
gate power FET constructed as in FIGURES 3 and 4 in
accordance with the prior art;
FIGURE 6 is a plan view of a dual-gate power FET
carrier above which is positioned the FET pellet of FIGURE
1, illustrated in phantom, in accordance with a preferred
embodiment of the present invention;
FIGURE 7 is a cross section elevation view along
lines 7-7 of khe FIGURE 6 carrier and the FIGURE 1 pellet
in accordance with a preferxed embodiment of the present
invention; and
FIGURE 8 is an electrical schematic of a
dual-gate power FET constructed as in FIGURES 6 and 7 in
accordance wi-th a preferred embodiment of the pr~sent
i.nven-tion.
Referring now to FIGIJRES 1 and 2 there is
illustrated, in plan view and cross sectional elevation
view respectively, an FET pelle-t intended for use in
fabricating a single~gate power F~T. The pellet 10
comprises a semiconductor substrate 12 of gallium arsenide
(GaAs) material upon which i5 deposited n-doped layer 14
approximately 0.3 micrometers thick of GaAs ma-terial. On
the layer 14 is a pattern of electrodes and pads -to be
described hereinafter. Although the physical layout of
the pads and electrodes is the same in the prior art
single-gate application and the inventive dual-gate
application, the use made of the electrod~s and pads is
different~
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Thus in FI~URES 1 and 2 the let-ters S (source),
D (drain) and G ~gate) which are not in parentheses, (),
refer to the invention use of the pads and electrodes;
while the same letters enclosed in parentheses refer to
the prior art use for those electrodes and pads. A11
electrodes, S, D and G extend between lines 16~16 and
18-18 in FIGURE 1. There are our pads, 20, 22, 24, and
26 illustrated in FIGURE 1. ~ll electrodes and pads are
typically made of gold and deposited on substrate 14.
In the prior art there are two drain pads 20, 22
by way of example. The (D~ pad 20 is connec-ted to two (D)
electrodes 20a and 20b. Likewise, in the prior art there
are two ga-te pads 24 and 26. By way of example, (G) pad
26 is connected to four (Ç) electrodes 26a, 26b, 26c, and
26d. Referring to FIGURE 2, it will be noted that the
upper surface of all five prior art (S3 elec-trodes 30, 32,
34, 36 and 38 are elevated above layer 14 relative -to all
four (D) electrodes 20a, 20b, 22a and 22b. The eight (G)
electrodes (no-t nun~ered in FlGURE 2 because of their
small size) and depressed into voids in the layer 14 for
purposes of easy manufacture. The five (S) electrodes are
not connected to any source pads but rather in accordance
with the prior ar-t, are elec-trically connected together by
a carrier to be hereinafter described. Although not
indicated in FIGURE 2, the upper surface of pads 20, 22,
24 and 26 are at the same elevations as the upper surface
of the (S) electrodes.
In a typical prior art pellet, the elec-trode and
pad pattern illustrated in FIGURES 1 and 2 less one end
(S) electrode (for example, 38) may be repeated. That is,
a set of pads and electrodes extending between and
including elec-trodes 30 and 26d are positioned to the left
of electrode 30. Since the repeated set electrodes are
not necessary to the present invention, they are not
illustrated.
In accordance with the invention, the use of the
various pads and electrodes is much differen-t tha-t the
prior art use. For example, with reference to FIGURE 1,
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electrodes 22a and 22b are treated as source electrodes,
no-t drain electrodes as in the prior art. Likewise pad 22
connected to electrodes 22a and 22b is treated as a source
pad, not a drain pad. Electrodes 30, 32 and part of 34
are treated as drain elec-trodes, not source electrodes.
Finally the gate electrodes connec-ted to gate pad 24 are
treated as gate 1 electrodes and the gate electrodes
connected to gate pad 26 are treated as gate 2 electrodes
of the dual-gate FET, no-t simply gate electrodes of the
single-gate FET.
In the prior art, FET pellet 10 is flip chip
(turned over and) mounted to a carrier 50 as illustrated
in plan view iIl FIGURE 3 and in cross section view in
FIGURE 4, to which attention is now direc-ted. Thus
FIGURES 3 and 4 illustrate mechanically and FIGURE 5
illustrates electrically a single-gate power FET. With
regard to FIGURE 3, the pellet 10 is only shown in phantom
so the shape of the carrier can more easily be seen.
Further, since the scale of FIGURES 3 and 4 are smaller
than that of FIGURES 1 and 2, only the gate and drain
pads~ not electrodes are illustrated and source electrodes
are simply illustrated as one long block ra-ther -than
individual electrodes. Parentheses are used on the
designations G, D and S to be consistent with FIGURES 1
and 2.
Carrier 50 includes an inverted T-shape (as
viewed in FIGURE 4) membex 52 made of copper for heat
conduction and for an electrical connection to all of the
source electrodes (S). For good heat dissipation
characteristics the vertical portion 52a of the T is
typically trapezoidal in cross section as illus-trated in
FIGURE 4. Carrier 50 also contains two ceramic risers 54
and 56 parallel to and flanking portion 52a. On each
ceramic riser is a copper layer 58 and 60 respectively.
Short lengths of bond wire 62 and 64 are connected between
pellet gate pads 24 and 26 respectively and copper layer
58. Similarly, short lengths of bond wire 66 and 68 are
coImected between pellet drain pads 20 and 22 respectively
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and a copper layer 60. Thus, gate pads 24 and 26 are
elec-trically connected together by copper layer 58, drain
pads 20 and 22 are electrically connected together by
layer 60, and the source electrodes are electrically
connected together by the T-shaped area 52a which also
dissipates heat produced in -the source electrodes and
other parts of pellet 10. Layer 58 is the transistor gate
connec-tion designated by -the lower case letter g in FIGURE
3. Layer 56 is the transistor drain connection designated
by the lower case let-ter d in FIGURE 3, and T-shaped
member 52 is the transistor source connection as
designated by the lower case let-ter s in FIGURE 3.
FIGURE 5 illustrates in elec-trical schematic
form the transistor which is mechanically illustrated in
FIGURES 3 and ~. The letters in parentheses () are prior
art D, G and S designations corresponding wi-th th~ pelle-t
designations in FIGURES 1 and 2 while the lower case d, g
and s terminal designations are for consis-tency with the
equivalent designations in FIGURE 3.
FIGURES 6, 7 and 8 to which attention is
directed, illustrate how the pellet of FIGURES 1 and 2,
originally designated for use as a single-gate power FET,
is used to make a dual-gate FET with power handling
capacity ~reater than that of a conventional dual-ga-te
FET. FIGURE 6 is a plan view of a dual-gate FET in
accordance wi-th the invention. The FET comprises a
carrier 70 and, illustrated in phantom as was -true in
FIGURE 3, the FET pellet 10 of FIGURES 1 and 2. As with
FIGURE 3, only the gate and drain (one used as a source)
pads and in the general source (drain) area are
illustrated. FIGURE 7 is a cross section elevation view
along lines 7 7 of FIGURE 6 but with FET pellet 10 in
place.
Carrier 70 comprises a substra-te 72 preferably
made of beryllium oxide (BeO) on which is deposited a
conductive pattern typically of copper and gold. The BeO
material is known to be a good electrical insulator and a
good thermal conductor. The conductive pattern includes a
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drain pad 74 in line with and electrically connected to
drain pad 20 of pelle~ 10, a source pad 76 in line with
and electrically connected to source pad 22 (a drain pad
in the prio~ art), a first gate pad 78 in line with and
elec~rically connec-ted to the G1 gate pad 24 of pelle-t 10
and a second gate pad 80 in line with and electrically
connected to -the G2 gate pad 26 of pellet 10. The
conductive pattern also includes a pad 82 in line with and
electrically connected to all of electrodes 30, 32, 34, 36
and 38. The various pads and elec-trodes on pellet 10 are
soldered to their associated pads on carrier 70. The heat
generated in pellet 10 when it is conducting power also
passes by means of the various pads to BeO substrate 72
and then to other parts of the circuit (no-t shown) for
ultimate dissipation into the atmosphere.
The pads 74, 76, 78 and 80 are the dual-gate
transistor terminals and are so indicated by lower case
letters which correspond to the same letters in the
dual-gate FET transistor electrical schematic of FIGURE 8.
That is, pad 74 is the transistor drain pad d, pad 76 is
the transistor source pad s, which is typically grounded
as illustrated in FIGURE 8, pad 78 is the transistor gate
gl terminal and pad 80 is the transistor g2 gate pad
terminal.
Although as illustrated in FIGURES 6, 7 and 8
there is no connection to the outside world f.rom -the
source S2/D1 pad 82, in some applications a connec-tion
from this pad to other circuit elements (not shown) may be
desirable and is easily accomplished by simply adding the
desired circuitxy on BeO substrate 7~ in-terconnected as
appropriate with pad 82.
By reviewing FIGURES 1 and 2 and FIGURES 6, 7
and 8 it will be understood that in accordance wi-th the
invention, electrodes which are conventionally used as
sources are in accordance with the invention used as
drains, electrodes 30, 32 and 34 (FIGURE 1) being examples
thereof, electrodes which are conventionally used as
drains are in accordance with the invention used as
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sources, ~lectrodes 22a and 22b being examples thereof and
the various gate electrodes which normally are
electrically connected -together (see FIGURE 3) are
electrically split into two gates, G1 and G2.
It will be understood that by using an FET pellet 10,
FIGURE 1, conventionally used in making a single-gate
power FET in combination with a novel carrier which
interconnects the pellet electrodes differen-tly -than with
the prior art carrier and provides different external
connections, as illustrated in FIGURES 6 and 7, a
dual-gate FET capable of handling power many times that of
a conventional dual-gate FET is realized. Fu.rthermore,
other circui-ts and circuit elements (not shown) may also
be placed on the BeO substrate 72 and coupled to pads 74,
76, 78 and 80, as appropria-te.
