Note: Descriptions are shown in the official language in which they were submitted.
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This invention relates to a semiconductor
structure comprisinq a semiconductor body having a bulk
portion which is of a first conductivity type and having
a major surface which is adapted to have electronic devices
fabricated thereon.
Many of today's high density MOS random access
memories (RAMS) are suhject to alpha par-ticle induced
"soft" errors. U.S. Patent No. 4,112,575 describes a MOS
switched-capacitor memory cell which uses a capacitor
structure that has relatively high capacitance per unit
area and is resistant to alpha particle caused loss of
charge (stored memory information). Other parts oE the
memory cell, such as the n-~ type drain/source bit line,
are essentially unprotected from alpha particle hits and
thereEore such hits may cause information errors.
Some have proposed the use of an alpha particle
absorbinc~ coating on top of a finished integrated circuit
chip as a way of protecting against "soft" errors. These
coatings may crack or may cause the integrated circuit chip
to crack or to have a bonding wire pulled off. This could
result in "soft" errors or a complete failure of the chip.
In accordance with the invention these problems
are overcome in a semiconductor structure characterized by
means for collecting radiation-generated current carriers
2r~ in the semiconductor body comprising a grid layer located
within the semiconductor body at a location which is
rem~ved ~rom the major surface; the semiconductor body
portions on opposite sides of the grid layer beincJ in
mutual electrical contact, and the distance between the
3() ~rid lflyer and the major surface is suE~icient such that
the qrid layer has no significant electrical effect on any
electronic devices located on the major surface.
In the drawing~
The FIGURE illustrates an embodiment of the
present invention.
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The present invention is directed to a
semiconductor structure comprising a semiconductor body
having a bulk portion of a first conductivity type and a
major surface which is adapted to have circuits and/or
devices fabricated thereon. A grid layer of the opposite
conductivity type is located within the semiconductor body
at such distance below the major surface such that it
causes essentially no significant adverse affects on the
operations of circuits and/or devices formed on the major
surface. The openings in the grid layer are designed to
have sufficient dimensions such that the portions oE the
semiconductor body on each side of the grid layer are
essentially always in electrical contact with each other.
The grid layer, which may have a contact region connecting
same to the major surface, serves to absorb alpha particle
induced charge and other s~ray charge in the semiconductor
body. This serves to help protect against losses of
information that may be stored or transferred between
circuits and/or devices fabricated on the major surface.
rhe semiconductor body may comprise just a
semiconductor substrate or it may comprise an epitaxial
layer on top of a semiconductor substrate. In the latter
case, the grid layer is typically positioned between the
epitaxial layer and the substrate~ I-t can, however, be
positioned wholly w;thin the epitaxial layer.
Referring now to the FI~URE, there is illustrated
a prospective partly cutaway view of a portion o a
semiconductor str~lcture 10 in accordance with the present
inventioll. Structure 10 comprises a semiconductor
~) s~lbstrate 12 of a first conductivity type, an epitaxial
layer 1~ o the first conductivity type but of lower
impurity concentration, and a grid layer 16 which is of a
second conductivity type that is opposite the first and
which is sandwiched between substrate 12 and epitaxial
layer 14. Portions of substrate 12 extend through openings
in grid layer 16 and contact bottom portions of epitaxial
layer 14.
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Epitaxial layer 14 has a major surface 18 into
which circuits and/or devices can be fabricated. For
example, a 64,000 bit MOS RAM using dynamic
switched-capacitor memory cells could be fabricated in
epitaxial layer 14 with major surface 18 serving as the
major surface of the memory. This type of memory is
potentially sensitive to alpha particles which can strike
the memory and cause an error in information stored in a
memory cell or information being transferred within the
mernory. Grid layer 16 is designed and located within
structure 10 so as to collect (absorb) stray charge,
including alpha particle induced charge, without
significantly adversely affecting the operation of circuits
and/or devices fabricated on (into) major surface 18 of
epitaxial layer 14.
For illustrative purposes substrate 12, epitaxial
layer 14, and grid layer 16 are assumed to be of p~, _, and
n+ type conductivity, respectively. Typically, p+ type
substrate 12 is biased at the most negative potential used
with structure 10 so as to reverse bias p-n junctions and
to help stabilize the threshold voltages of MOS transistors
~abricated on major surface 18. Substrate 12 could be
biased through a _~ type region (not illustrated) which
extencls Çrom substrate 12 through epitaxial layer 1~ and
~5 intersects major surface 18 where the most negative
po~enticll source used with structure ln is connected. The
use of a dlscrete negative potential generator circuit (not
illustrated), or one (not illustrated) fabricated on
surface lR, allows the substrate 12 to be at a negative
potential independent of the most negative potential usecl
with structure 10.
The dimensions of the openings in grid layer 16
are selected such that depletion regions spreading out from
grid layer 16 into epitaxial layer 14 and/or substrate 12
do not pinch off electrical contact between epitaxial
layer 14 and substrate 12. The distance between -the
bottoms of circuits and/or devices that are fabricated into
4 --
surface 18 of layer 14 and grid layer 16 is selected such
that grid layer 15 has essentially no significant adverse
electrical affect on the operation of the circuits and/or
devices.
Grid layer 16 can be allowed to electrically
float in potential. Alternatively, a deep n~ type region
can be formed through epitaxial layer 14 to make contact to
grid layer 16 to allow grid layer 16 to be reve~se biased
with respect to epitaxial layer 14 and semiconductor
substrate 12 by the application of an appropriate potential
to the n+ type region.
If grid layer 16 is allowed to electrically float
in potential it tends to be close to a potential which
forward biases the p-n junctions which comprise p type
epitaxial layer 14 and _+ type substrate 12 and n+ type
grid layer 16 because of the collection (absorption) of
electrons fro~ leakage sources in substrate 12 and
epitaxial layer 14. If an alpha particle hits epitaxial
layer 14 then the generated electrons in layer 14 diffuse
through layer 14, are attracted into the depletion region
formed near the junction of layer 14 and grid layer 16, and
are then swept into grid layer 16~ This tends to further
forward bias the p-n junction comprising layers 14 ancl 16
and thus causes injection of electrons back into layer 14.
7.5 This re-injection has a drift field in grid layer 16 to aicl
in spreading out laterally and therefore spreads out the
excess electrons faster than is the case if grid layer 16
does no~ exist anc] the alpha particle c3enerated electrons
just diffuse normally through epitaxial layer 14. An
electrically Eloating grid region 16 thus has the net
affect of spreading out the electrons created by an alpha
particle hit over a wider area of epitaxial layer 14 such
that the detrimental affects on any one circuit and/or
device is reduced over what is the case if grid layer 16 is
not used.
If grid layer 16 is positively biased with
respect to substrate 12, then alpha particle generated
-- 5 -
electrons and other stray charge in epitaxial layer 14 or
substrate 12 are collected into grid layer 16 and there is
essentially no re-injection back into epitaxial layer 14 or
substrate 12.
If grid layer 16 is held at essentially the same
potential of substrate 12, it will still collect (absorb) a
relatively large number of alpha particle induced electrons
or stray charge because of the relatively large capacitance
between grid layer 16 and substrate 12. This capacitance
can absorb substantial charge without building up enough
potential to re-inject many electrons back into epitaxial
layer 14 or substrate 12.
In a typical embodiment the conductivity of _+
type substrate 12, p type epitaxial layer 14, and n+ type
grid layer 16 are 1018-102 impurities/cm3, 1014-1016
impurities/cm3, and 1013-102 impurities/cm3, respectively.
For a 16,000 bit MOS dynamic RAM the epitaxial layer 14
might typically have a thickness of approximately
10 microns and the grid layer might have a thickness of
approximately .5 to 1 micron~ The circuits and/or devices
on surface 18 might typically be fahricated to a depth of
approximately 1~5 microns below surface 18 of epitaxial
layer 14. The size of grid layer 16 openings would
typically be 5 microns on a side and the width of the grid
layer 16 lines would typically be approximately 5 microns
with grid layer 16 being no more positive in potential than
sllbstrate 12 than approximately 3 volts.
As devices become fabricated with shorter channel
len~ths and are more shallowly fa~ricated into epitaxial
layer 1~, th~ impurity concentration of layer 1~ increases
and the thickness thereof decreases. This allows grid
layer 1~ to be closer to surface 18.
The embodiments described herein are intended to
be illustrative of the general principles of the present
invention. ~larious modifications are possible consistent
with the spirit of the invention. For example,
substrate 12, epitaxial layer 1~, and grid layer 16 could
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be of n+, n, and _+ type conductivity, respectively. Still
further, in the case that an epitaxial layer is not used
and circuits and/or devices are fabricated directly into a
major surface of the substrate, then grid layer 16 would be
located below the major surface of the substrate. Still
further, the grid layer need not extend to the outer edges
of the semiconductor substrate and/or epltaxial layer.
Still further, grid layer 16 can be formed wholly within
epitaxial layer 1~ and not be located just at the interface
of substrate 12 and epitaxial layer 14. Still further,
grid layer 16 can be formed wholly within substrate 12 and
not be located just at the interface of substrate 12 and
epitaxial layer 14.
