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Patent 1200920 Summary

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Claims and Abstract availability

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(12) Patent: (11) CA 1200920
(21) Application Number: 1200920
(54) English Title: PRINTED CIRCUIT BOARD LAYOUT FOR A PERSONAL COMPUTER
(54) French Title: SCHEMA DE CARTE DE CIRCUITS IMPRIMES POUR ORDINATEUR PERSONNEL
Status: Term Expired - Post Grant
Bibliographic Data
(51) International Patent Classification (IPC):
  • H05K 1/02 (2006.01)
(72) Inventors :
  • BREWER, JAMES A. (United States of America)
  • LANGGOOD, JOHN K. (United States of America)
  • MARKHAM, HARVEY R. (United States of America)
(73) Owners :
  • INTERNATIONAL BUSINESS MACHINES CORPORATION
(71) Applicants :
  • INTERNATIONAL BUSINESS MACHINES CORPORATION (United States of America)
(74) Agent: ALEXANDER KERRKERR, ALEXANDER
(74) Associate agent:
(45) Issued: 1986-02-18
(22) Filed Date: 1984-07-17
Availability of licence: N/A
Dedicated to the Public: N/A
(25) Language of filing: English

Patent Cooperation Treaty (PCT): No

(30) Application Priority Data: None

Abstracts

English Abstract


ABSTRACT
There is described a six-layer printed
circuit card in which the first, third and sixth
layers are signal carrying layers for intercon-
necting various components forming a personal
computer. The second and fifth layers are both
ground plane layers and the addition of a second
ground plane layer to a printed circuit card
reduces the electromagnetic interference emitted
from the closely packed components and lines. The
final layer of the card is a voltage plane. The
components on the printed circuit board include
eight input/output (I/O) connectors to which eight
other cards controlling various I/O devices can be
connected. Seven of the eight I/O connectors are
interconnected to a conventional I/O bus. The
eight connector is interconnected to some lines of
the I/O bus and to some lines of the internal bus
throughout the card.


Claims

Note: Claims are shown in the official language in which they were submitted.


The embodiments of the invention in which an exclusive
property or privilege is claimed are defined as follows:
1. In a multilayer printed circuit board
having printed wires and plated holes for intercon-
necting components of a computer, said printed
circuit board having at least two signal planes, a
voltage plane and a ground plane all interconnected
in circuit with said components, the improvement
comprising a second ground plane primarily for
electrically connecting electrical ground through
said holes to be in circuit with said components,
said two ground planes being positioned immediately
adjacent to the outermost signal planes of said
multilayer printed circuit board.
2. The invention according to claim 1
wherein one of said ground planes further includes
signal paths formed by etched away copper for
electrically coupling voltages from one plated hole
to another plated hole.
3. The invention according to claim 1
wherein said multilayer board further includes a
third signal plane positioned between said two
ground planes.
4. The invention according to claim 3
wherein said voltage plane is positioned between
said two ground planes.
-17-

5. The invention according to claim 4
wherein one of said ground planes further includes
signal paths formed by etched away copper for
electrically coupling voltages from one plated hole
to another plated hole.
-18-

Description

Note: Descriptions are shown in the official language in which they were submitted.


BC9~83-005 1 ~ 2~ 2 ~
PRI~TED CIRCUIT BOARD LAYOUT
FOR A PE~SONAL CO~IPUTER
This invention relates to a printed
circuit board construction and layout and, more
particularly, to a six-layer printed circuit board
in which two ground plane layers are provided to
provide extra shieldiny against emitted electro-
magnetic interference.
Printed circuit cards and multi-layer'
printed circuit boards are well known in the prior
art. These boards are used to affix and inter-
connect electronic components to form electronic
circuits. Examples of such circuits are personal
computers such as the IBM Personal Computer. In
the IBM Personal Computer, for instance, the base
planar board includes a plurality of electronic
components including a microprocessor, random
access memory, special logic circuits such as
timers and direct memory access (DMA) circuits,
associated with the microprocessor and other logic
components forming circuits. These circuits are
all soldered to a printed circuit board and wire
lines etched into the board are positioned to
interconnect all of the components to an operating
computer system.
In the IBM Personal Computer, for instance,
a four-layer printed circuit board is utilized in
which the top and bottom layers are used as signal
path planes to interconne`ct the various components.
~etween the two signal path layers is a ground
plane and a voltage plane. Coupled through the
board are plated holes which may be electrically

BC9 83-005 2
coupled -to any of the layers to allow intercon-
nections from one layer to -the other~
In building a more comple~ circuit card
containing more larger, more powerful circuits,
shielding against electromagnetic interference
becomes necessary. This interference is caused by
high frequency signals traveling over long printed
leads (e.g. four inches at 5 Mhz) causing the lead
to act as an antenna. In the prior art, this
problem was solved by providing additional com-
ponents, such as resistors, capacitors and inductors
as well as special shielding to damping the oscilla-
tions. This solution resulted in extra cost and
extra space required on a finite area printed
circuit board. By providing two ground planes each
immediately adjacent to one of the front and back
signal planes, an improvement in the electromagnetic
interference characteristics is obtained.
In accordance with one preferred embodi-
ment of this invention, there is provided in a
computer system, including a a multilayer printed
circuit board having printed wires and plated holes
for interconnecting components of a computer, said
printed circuit board having at least two signal
planes, a voltage plane and a ground plane all
interconnected in circuit with said components, the
improvement comprising a second ground plane
primarily for electrically connecting electrical
ground through said holes to be in circuit with
sald components, said two ground planes being
positioned immediately adjacent to the outermost
signal carrying pLanes of said multilayer printed
circuit board.

~ 2~
BC9-83-005 3
One preferred embodiment of this inven-
tion is described hereinafter with respect to the
following Figures, in which:
Figure 1 shows the front, or component,
side of a six layer printed circuit board;
Figure 2 shows one ground plane layer of
the printed circuit board;
Figure 3 shows the third signal layer of
the printed circuit board;
Figure 4 shows the voltage plane layer of
the printed circuit board;
Figure 5 shows the second ground plane
layer of the printed circuit board;
Figure 6 shows the back, or pin, side of
the printed circuit board; and
Figure 7 shows the same front side of the
printed circuit board as shown in Figure 1 wi-th
blocks drawn over the board to indicate where
vaxious components fit;
Referring now to Figures 1 through 6, the
six layers of the multi-layer printed circuit board
used with an enhanced personal computer are shown.
Figure 1 is the top layer onto which the components
are inserted and Figure 6 is the bottom layer to
which the various pins from the components are
soldered. In Figures 1, 3 and 6 which are the
signal path planes, the dark areas represent copper
:

~ ,53
BC9-83-005 4
which is left af-ter having etched away the light or
white areas. Figures 2 and 5 which are ground
planes and Figure 4 which is a voltage plane are
just the opposite in that the dark areas indlcate
etched away copper and the light area is solid
copper.
Referring again to Figure 1 where the
dark areas indicate the copper which is remaining
a~ter etching, holes through the board are indicated
by either dots 20,26 or squares 22,28, and the
lines used for interconnecting components are
indicated by the thin lines. The dots such as 20
or 26 are shown in different sizes which is deter-
mined by the size of the pins on the components tobe inserted. No other significance is associated
with the different size dots. Generally, the
squares 22 and 28 are used to designat~ which way
the components is to be inserted, such that pin 1
of the component is fit into a square space. It
should be noted, however, that it is only the
plating around a round hole which is square, and
not the hole i,tself. The same is true with respect
to the larger holes, such as 26 and 28. The wires
interconnecting the various components, such as
lines 30 or 32, can be of two sizes depending upon
the amount of current which is to be conducted.
For instance, line 30 is a narrow line indicating a
small amount of current is to be flowing there-
through. On the other hand, line 32 is larger inwidth to indicate that a large amount of current,
such as a voltage path, will be utilizing that
connection. In addition in Figure 1, a pair of
ground pads 34 and 36, which have holes (not shown)
therethrough are provided. The pads 34 and 36 are

BC9-83-005 5 ~ ~63~1~ 2 ~
for the purpose of providing goocl connection
be-tween the scxew securing the board to the machine
frame and the ground plane shown in ~igures 2 and
5. There additionally are provided holes 38
through the entire printed circuit board which are
not plated through and not interconnected in
circuit with the remainder of the board. These are
for the purpose of securing the card into the
package of the computer. These holes are indicated
generally in Figure 1 by a hollow diamond shape.
Referring now to Figure 2, one of the two
ground plane layers is shown. As previously
indicated, in the ground plane layer the dark areas
represent copper which has been etched away and the
light areas represents solid copper. Thus, in
Figure 2, the ground plane layer is to a large
e~tent a copper layer. Again, the holés are
indicated by either dots or squares and it should
be noted that the etching away of the plated
through hole is gxeater than the hole itself to
avoid electrical contact between the plated through
hole and the ground plane layer. Where contact is
desired, such as indicated by area 40, lines
~5 surrounding the plated through hole may be etched
out so long as the etching is not solid. It is
necessary for the hole to electrically contact the
remainder of the ground plane and the amount of
etching shown in Figure 2 is for identification
purposes only. Electrically, the hole through the
printed circuit board must be conductively coupled
to the remainder of the board. It should be no-ted
that the large etched areas such as 42 have a large
etched away area so that the holes 38 (shown in
Figure 1) for securing the board to the package are
.j .

2~
sC9-83-005 6
not in electrical contact with the rernainder of -the
ground plane. However, in the case of pads 34 and
36 (shown in Figure 1) this is not the case as
indicated by areas 44 which are the actual connec-
tion of the ground plane to the frame. In additionto pads 34 and 36, area 46 electrically couples the
ground plane to the power supply, area 48 electrically
couples the ~round plane to the keyboard cable and
area 50 electrically couples the ground plane to
the keyboard.
Figure 3 is similar to Figure 1 in that
it is another signal path plane wh~re the dark
areas indicate the copper remaining and the light
areas indicate where the copper has been etched
away. Again, whether a hole has a round or a
square area of copper remaining is for identifica-
tion purposes and the physical size ~f'the hole or
the lead is the same as explained above with
respect to Figure 1.
Referring now to Figure ~, the voltage
plane is sh~wn. As was the case with the ground
plane shown in Figure 2, the white areas indicate
the remaining copper and the dark areas indicate
the copper areas etched away. Generally, the
majority of the white areas shown in Figure 4 is
maintained at a voltage of +5 volts which is
connected to the power supply through area 52.
However, because the processor requires both ~5 an~
-5 volts as well as +12 and -12 volts, it is
necessary to provide the +12 volts, -12 volts and
-5 volts to certain areas. This is indicated by
the lines such as~5~ which define paths cut away
from the main part of the voltage plane and can be

~ 26~
BC9-83-005 7
used to carry one of the other needed voltages.
The voltages may also be carried, for instance in
line 32 shown in Figure l, where such is required.
For instance, the area defined by lines 54 would be
a +12 volt signal which is applied to the various
pins as indicated. Note that where such a +12 volt
signal path is applied to a pin of a connector such
as at 56, the hole is not etched away at this
point, thereby providing the +12 volts to the
plated hole and any pin inserted at area 56. Where
it is desired to have the +5 volt voltage applied
to a particular pin such as at area 58, lines which
are not connected are etched away for identification
purposes of a hole only. Ayain, it is necessary
that the plated through hole be electrically
connected to the voltage plane, so that etching
should not be continuous aro~nd the hole.
Referring now to Figure 5, the second
ground plane is shown which is identical to the
first ground plane shown in Figure 2, except for
the areas defined by lines 60 and 62. These lines
define a voltage path of -5 volts. It was necessary
to place this voltage path defined by lines 60 and
62 on this ground plane ~ecause of the lack of room
on the voltage plane shown in Figure 4. It would
be preferable to have placed these lines on Figure
~ for system performance but spacing requirements
dictated o-therwise.
Referring now to ~igure 6, the back side
of the printed circuit board is shown. This back
side is another signal path plane and, again, the
round dots a~d square dots and the lines whe-ther
thick or thin, indicate the remaining copper.

sC9 83-005 8
Other than the specific interconnections of the
lines, Figure 6 is similar to Figure 1.
By utilizing Figures 1 through 6, it is
possible to trace out the entire circuit in-tercon-
nections. For instance, the lines defining the
voltage paths 60 and 62 shown in Figure 5 are
interconnected by holes 63 and 64 and line 65 shown
in Figure 6 so that electrically the lines 60 and
62 are at the same voltage. Line 62 further goes
through the plated hole indicated at area 66 in
Figures 1, 3 and 5. I~ Figure 3 specifically, it
is seen that a copper connection 68 connects hole
66 to another hole 70 to which the voltage is
applied to the entire circuit card from the power
supply through a pin of connector P2 (to be described
hereafter with respect to Figure 7) which is
inserted through hole 70.
Referring now to Figure 7, the populated
circuit board looking over the signal path plane of
Figure 1 is shown. Each of the blocks indicate a
circuit com~onent or a space for a circuit component
which is used on the populated board. The various
blocks have been la~eled with a letter and a number
to indicate what the component is. Referring to
the table set forth below, the various components
are indicated.
3~

BC9-83-005 9 1 2q~ 9 2 0
TABLE
Cl 5-50 PF TRIM CAPACITOR 50V
C2 47PY 15VDC
C3 lOUF 16VDC
C4 47PF 15VDC
C5-6 .047UF 15VDC
C7 47PF lSVDC
C8 .047UF 15VDC
C9 47PF 15VDC
C10-16 10UF 16VDC
C17-18 .047VF 15VDC
Cl9 .10UF 16VDC
C20-27 .047UF 15VDC
C28 10UF 16VDC
C29-36 .047UF 15VDC
C37 10UF 16VDC
C38-45 .047UF 15VDC
C46 10UF 16VDC
C47-52 .047UF 15VDC
C53 .0lUF 7VDC
C54 10UF 16VDC
C55 .047UF 15VDC
C56 10UF 16VDC
C57 .047UF 15VDC
C58 10UF 16VDC
C59 10UF 16VDC
C60 .047UF 15VDC
C61 10UF 16VDC
C62 .047UF 15VDC
C63 10UF 16VDC
C64-67 .047UF 15VDC
C68 10UF 16VDC
Jl J8 62 PIN EDGEBOARD CONNECTOR

~0~
BC9-83-005 1`0
J9 5 PIN 90 DEGREE CONNECTOR
Pl 6 PIN POWER CONNECTOR (KEY=4)
P2 6 PIN POWER CONNECTOR (KEY=l)
S P3 4Xl BERG CONNECTOR (KEY=l)
Rl 510 OHM
R2 510 OHM
R4 220 OHM
R5 180 OHM
R6 33 OHM
RNl 4.7 KOHM 15RESISTOR/PACK+10~
RN2 8O2 KOHM 15RESISTOR/PACK+10%
RN3-RN~ 30 OHM 8RESISTOR/PACK+10%
RN5 4.7 KOHM 15RESISTOR/PACK+10
SWl 8 POS DIP SWITCH
TDl DIGITAL TIME DELAY (5 TAPS 100
NSEC MAX)
TD2 DIGITAL TIME DELAY (7NSEC)
El NO COMPONENT
E2 NO COMPONENT
E3 NO COMPONENT
E4 NO COMPONENT
E5 NO COMPONENT
Ul 8284A CLOCK DRIVER
U2 74LS245
U3 8088 MICROPROCESSOR
U4 NO COMPONENT
U5 74LS373
U6 74LS244

?~2~D
BC9-83-005 ll
U7 74LS373
U8 8288 BUS CONTROLLER
U9 74LS245
Ul0 74LS670
Ull 74LS373
Ul2 74LS244
U13 74LS243
U14 74LS244
U15 74LS245
U16 74LS244
U17 74LS244
U18 32KX8 ROM
Ul9 8KX8 ROM
U20 74S280
U21 74LS175
U22 74LS04
U23 74LS27
U24 74LS00
U25 8259A INTERRUPT REQUEST CONTROLLER
U26 8253-5 TIMER/CONTROLLER
U27 74LS322
U28 8237A-5 D~R CONTROLLER
U-29 8255A-5 PARALLEL PERIPHEI~L INTERFACE
u3b-38 64KXl RAM 200NSEC
U39 74LS158
U40 74LS158
U41 74LS244
U42 74LS138
U43 74LS138
U44 24Sl0 PROM
U45 74LS138
U46-54 64KXl RAM 200NSEC
U55 74S08
U56 74S138
U57 74LS20
.

~2~
BC9-83-005 12
U58 74Ls32
U59-67 64~CXl BIT RAM 200NSEC (OPTIONAL)
U68 7407
U69 74S00
U70 74S74
U71 74LS04
U72 74LSl0
U73 74LS74
U74 74LS00
U75-83 64KXl BIT RAM 200 NSEC (OPTIONAL)
U84 NO COMPONENT
U85 75477
U86 74LS74
U87 74S08
U88 74LS175
U89 74LS04
XU3 40 PIN DIP SOCKET '
XU4 40 PIN DIP SOCKET
XU18 28 PIN DIP SOCKET
XUl9 28 PIN DIP SOCKET
-X.U30-XU38 16 PIN DIP SOCKET
XU44 16 PIN DIP SOCKET
XU46-54 16 PIN DIP SOCKET
XU59-67 16 PIN DIP SOCKET
XU75-84 16 PIN DIP SOCKET
Yl CRYSTAL 14.31818 MHZ
Wl SOLID AWG 24 WIRE
All of the components listed in the tabie are
commercially avaiLable components from semi-
conductor manufacturers such as Intel Corp. of

.~2~
BC9-83-005 13
Santa ~lara, California or Texas Instruments Corp.
of Dallas, Texas.
As noted frorn the above table, all of the
component areas shown in Figure 7 are not necessarily
populated. Some, such as U75-U83 are for optional
components such as additional memory, while others
such as E1 E5 are for future expansion. Further,
some of the components have a socket between -the
actual electronic component and the board. ~or
instance, from the chart, it is seen that U3 is an
8088 microprocessor sold by the Intel Corporation.
However, noting from the chart, there is also an
~U3 component which indicates that a connec-tor is
placed between the printed circuit card and the
8088 microprocessor. Such a connector may be any
40 pin dual in-line socket commercially available.
In another indication, the component ua is an extra
space as indicated by the lack of a designation for
U4. However, the designation XU4 indicates that a
43 pin socket is provided for the insertion of any
40 pin componentO For example, an 8087 math
processor manufactured by Intel Corporation may be
inserted in the space indicated as U4. Further,
there are some areas such as El through E5 which do
not contain any component or socket. These are
provided for the purpose of al]owing the user to
reconfigure the board. For instance, if one
desired to provide 256K X 1 bit RAM memories in
components U30 through ~38 or U46 through U54,
instead of the 64K as is indicated, it will be
necessary to change the component (74LS158) wiring
layout in the area indicated by E2 and to add to
location ~84. Such a chance could be simply
shorting a wire and adding a jumper, or soldering
.

f2~
BC9~83-005 1~
in a serg co~nector and makin~ an appropriate
connection.
In the configuration shown in Figure 7,
there are provided eight 62 pin edgeboard connec-
tors, into each of which another printed circuit
board may be inserted. Such inserted boards may be
an attachment card to control a display, a disk or
any other I/O or memory attachment card useful with
the processor. Attaching such I/O connectors is
well known in the prior art such as, for instance,
the IBM Personal Computer. However, in the prior
art computer, only five such connectors were
provided. By rearranging and reconfiguring the
circuit board as is shown in Figures 1 through 6
and populated by the components shown in Figure 7,
one is able to add three additional I/O connectors
for a total of eig.ht. These additional connectors,
and hence the ability to add three additional I/O
attachment cards to the computer, greatly increases
the usefulness of.the computer to its user. sy
increasing the number of connectors, additional
space and lines were required which were not
required on the prior art device. To accommodate
for the lost space and the additional lines, the
signal plane shown in Figure 3 was added, thereby
allowing the additional interconnections. This
further allowed the components to be physically
placed closer together to accommodate the area
required for the additional connectors.
Because of long printed wires and hi.gh
signal frequencies, a problem of electro-magnetic
interference may be encountered. To prevent this,
a second ground plane is added - as indicated in

sC9-83-005 15
Figure 2. Thus, the t~o ground planes shown in
Figures 2 and 5 act as a shield between the three
signal path planes, in addition to the normal
purpose of providing ground connectlons khrough the
circuit. The second ground plane also provides a
better current return to the power supply for loyic
circults, thus damping oscillations which could
cause electromagnetic radiation.
Referring again to the attachment card
connectors Jl~J8, it is desirable to connect each
pin of each connector identically to the same line
of an I/O bus. The I/O bus consists of signal
lines generated by the circuits shown in Figure 7
and includes the address bus lines, data bus lines,
and the control signals, as well as proper voltage
and ground linesO The signals generated by the
circuits may be referred to as an internal bus.
The required signals are applied through conven-
tional driver circuits to be provided as the I/O
bus signals. However, another problem which mustbe encountered when adding additional connectors is
the number of connectors which a driver circuit can
drive. This number is based on many things, such
as the load of the card placed in each connector.
Furthermore, within each card each signal line must
be considered. For the layout shown for the printed
circuit card shown in Figures 1 through 6, for
certain heavily used signals, such as the address
and data bus lines, seven is the maximum number of
I/O attachment cards which can be driven by the
driver circuits. However, because space was made
available for the eighth slot, and it was desirable
to provide as many I/O connectors as possible,
alternate methods of driving the eighth connector

~O~
sC9-83-005 1~
are required. This was accomplished by disassociatlng
certain pins o~ -the eigh-th connector Erom -the I/O
bus which interconnected connectors Jl -through J7.
For certain pins as can be traced by using Figures
1 through 8, J8 is interconnected to the internal
planar I/O bus rather than the I/O bus. For other
pins, such as a DMA request or acknowledge signal
where very little load is encountered, it is
possible and desirable to use the I/O lines them-
selves. Hence, the interconnection of connector J8is a hybrid between some lines o~ the I/O bus and
some lines of the planar bus.
For example, it can be seen that at pin
72 in Figure 1, an interrupt signal is provided to
connector J8 from the standard I/O bus which
interconnects Jl through J7. However, at pin 74
shown in Figure 1 a data line of the I/O9 bus
stops. In Figure 6, pin 76 which corresponds to
connector J7, pin 74 in connector J8 is connecte~
to lines on the internal bus by line 78. This
would be the same signal as is applied to pin 74 in
Figure 1 bu.t provided from a different driver
circuit.

Representative Drawing

Sorry, the representative drawing for patent document number 1200920 was not found.

Administrative Status

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Event History

Description Date
Grant by Issuance 1986-02-18
Inactive: Expired (old Act Patent) latest possible expiry date 1984-07-17

Abandonment History

There is no abandonment history.

Owners on Record

Note: Records showing the ownership history in alphabetical order.

Current Owners on Record
INTERNATIONAL BUSINESS MACHINES CORPORATION
Past Owners on Record
HARVEY R. MARKHAM
JAMES A. BREWER
JOHN K. LANGGOOD
Past Owners that do not appear in the "Owners on Record" listing will appear in other documentation within the application.
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Document
Description 
Date
(yyyy-mm-dd) 
Number of pages   Size of Image (KB) 
Drawings 1993-06-23 8 616
Cover Page 1993-06-23 1 15
Abstract 1993-06-23 1 19
Claims 1993-06-23 2 34
Descriptions 1993-06-23 16 454