Note: Descriptions are shown in the official language in which they were submitted.
SEMICONDUCTOR DEVICE ~IAVING TURN-ON
AND TURN-OFF CAPABILITIES
The invention realtes to -thyristors, and,
more particularly, to thyristors having both turn-on
and turn-off capabilities.
The prior art and the invention are described
herein with reference to the accompanying drawings,
in which
FIGURE l is a schematic, cross-secticnal,
view of a prior art thyristor illustrating MOS turn-on
structure on its upper surface;
FIGURE 2 is a schematic, cross-sectional,
view of a semiconduc-tor structure incorpora-ting
the invention; and
E'IGURE 3 is a graph oE device current
versus time illustrating aspects of turn-on and
turn-off of a semiconductor device in a controlled
manner in accordance with an embodiment of the
invention.
Thyristors are well known semiconductor
devices which are typically used as curren-t swi-tches
for enabling and interrupting eurrent flow in a
circuit. A thyristor is "turned-on" when it
provides a high conductance path between two of
its terminals that is, its anode and cathode), and
is "turned-off" when it provides a high resistance
path between such two terminals. A typieal prior art
thyristor 10 is shown in Figure l. The thyristor
10 ineludes four regions, 12, 14, 16 and 18, of
al-ternating conductivity type' an anode 20
and a cathode 22, and a metal-oxide-semiconduc-tor
("MOS") turn-on structure 2~; or, more broadly
~r~q
~2q~
stated, a conductor-insula-tor-semiconductor turn-on
structure 24.
The MOS turn-on s-tructure 24 includes
a gate 26 and an insulating layer 28 separating
the gate 26 from the semiconductor body of the
thyristor 10. The biasing of the gate 26 with
a positive voltage (with respect to the cathode
22) exceeding a threshold value "inverts" the
portions of the P-type region 16 adjacent to -the
insulating layer 28, thereby creating inversion
channels 30, which can conduct electrons. Accordingly,
electrons from -the cathode 22 can :Elow in the
electron current paths 32 through -the N-type region 18
to the N-type region 14, via the inversion channels
30.
As is known in the art, the thyristor 10
can be molded as two transistor structures,
comprising an N-P-N transistor structure, formed by
N-type region 14, P-type region 16, and N-type
region 18, and a P-N-P transistor structure, formed
by P-type region 12, N-type region 14, and P-type
region 16. The N-P-N transistor structures are
regeneratively "coupled" to each other; that is the
collector of the N-P-N transis-tor structure (region
14) is coupled to the base of the P-N-P transistor
structure (region 14) and so can drive -this base,
and the collector of the P-N-P transistor structure
(region 16) is coupled to -the base of the N-P-N
-transistor structure (region 16) and so can
drive this base. Accordingly, the supply of
electrons to the N-type region 14 (the base of
the P-N-P transistor structure) causes both
the N-P-N and P-N-P transistor structures to
regeneratively turn on, whereby the thyristor 10
becomes turned on.
It would be desirable to provide a
semiconductor device which can operate as a
thyristor and which has MOS turn-on structure
at its upper surface and MOS turn-off structure at
its lower surface. Such a device would have turn-
off capabilities and yet be simple to manufacture
because each surface of -the device would have only
two electrodes; that is, a yate for MOS turn-on or
turn-off structure and the anode or cathode.
Accordingly, it is an object of the invention
to provide a semiconductor device having MOS turn-on
structure on one of its surfaces and MOS turn-off
structure at another of its surfaces.
A further object of the invention is to
provide a semiconductor device which can operate
ei-ther as a thyristor or as a field-effect--transistor
(hereinafter, "FET"), whereby significant
advantages as set forth below result.
In carrying out the objects of the
invention, there is provided a semiconductor
device comprising a body of semiconductor material;
firs-t and second electrodes; and first and second
pluralities of cells.
The semiconductor body includes
first, second, third and fourth regions successively
_ 3
l ad I I
joined together. The first and third regions are of
one conductivity -type, and the second and fourth
regions are of the opposite conductivity type.
The second region is doped to a predetermined
concentration a-t leas-t in its portion which is
adjacent to the third region. The third region
is doped substantially higher in concentration
than the predetermined doping concentration. The
first and fourth regions each include a respective
portion doped subs-tantially higher in concen-tra-tion
than the third region doping concentration.
The firs-t and second elec-trodes are electrically
connected, respectively, -to the first and fourth
regions.
Each of the first plurality of cells
comprises conductor-insulator-semiconductor-
type means for transporting majority carriers
between the second region and the first electrode.
Each of the second plurality of cells comprises
conductor insulator-semieonductor-type means
for transporting majority earriers between the four-th
region and the second region.
In a partieular embodiment of the
invention, the cell repeat distances of the first
and second pluralities of cells are less than
about the minimum thickness of the second region of
the semiconductor body.
3etailed Description of Specific Embodiments of the Invention
FIGURE 2 schematically illustrates a semlconductor
device 40 incorporating the present invention. The device 40-
includes turn-on cells 42 and 44, which are suitably alike, and
further includes turn-off cells 46 and 48, which are
suitably alike. Accordingly, only the left-hand cells 42 and
46 are discussed in detail below.
The semiconductor device 40 includes a first
region 50, a second region 52, a third region 54, and a fourth
region 56, which are successively joined together. The first
region 50 is separated from the third and fourth regions 54 and
56 by the second region 52, and the fourth region 56 is
separated from the first and second regions 50 and 52 by the
third region 54. The device 40 includes further
5~
first regions, such as first region of the turn-off cell 48,
further third regions, such as the third region 5~ of the
turn-on cell 44, and further fourth regions, such as the
fourth region 57 of the turn-on cell 44. It is permissible
that the first regions, such as 50 and 53, be interconnected;
it is likewise permissible that the third regions, such as
54 and 55, be interconnected.
An N-P-N transistor structure is formed by the
N-type second region 52, the P-type third region 54, and
the N-type fourth region 56. A P-N-P transistor structure
is formed by the P-type first region 50, the N-type second
region 52, and the P-type third region S4.
Typical doping concentrations (that is, the number
of dopant atoms per cubic centimeter) for the various regions
2~
of the semiconductor device 40 are in the order of the
following numbers:
First region 50 (Pl+ portion): 1018 or above
. Second region 52: 1016 or below
Third region 54: lO 7 or below
Fourth region 54: 1018 or above.
It can thus be said, for example, that the third region 54
has a doping concentration substantially higher than the
doping concentration of the second region 52. By "substantially
higher" or "substantially lower" is meant herein: higher or
lower by at least about an order ox magnitude.
A cathode 58,which is suitably interdigitated on the
upper surface of the device 40,adjoins the fourth region 56.
An anode 60,which is suitably interdigitated on the lower
15 surface of the device 40,adjoins the first region 50.
The turn-on cell 42 includes a gate 60 and an
insulating layer 61 separating the gate 60 from the semicon-
ductor body of the device 40. The gate 60 overlies the
third region 54 from proximate location 62 where a junction 63
(between the second and third regions 52 and 54) terminates
adjacent the insulating layer 61 to proximate a location 64
where a junction 65 (between the third and fourth regions
54 and 56) terminates adjacent the insulating layer 61.
Similar to the operation of the prior art turn-on structure 24
of FIGURE 1, the biasing of the gate 60 with a positive
voltage (with respect to the cathode 58) exceeding a threshold
value inverts the P-type third region 54 immediately beneath
the insulating layer 61, thereby creating an inversion channel
66, whlch can conduct electrons. The inversion channel 66
thus provides an electron current path 67 between the fourth
region 56 and the second region 52. Electrons from the
cathode 58 can thus flow in the path 67 to the N type selond
region 52, which constitutes the base of the P-N-P transistor
structure, and cause both the P-N-P and N-P-N transistor
structures to regeneratively turn on, whereby the devlce 40
turns on.
lhe gate 60, the insulating layer 6a and the
portion of the third region 54 containing the inversion
channel 66 constitute what one skilled in the art would
recognize as an MOS-type means for transporting majority
carriers between the fourth region 56 and the second region
52, which means is of the normally-off type.
The turn-on cell 42 may be fabricated in a variety of
shapes as viewed from above, such as elongated, square, or
round.
The turn-off cell 46 comprises a gate 68,an insulating
layer 70 and preferably, an N-type region 72. The region 72
adjoins the first region 50 and the anode 60. The gate ~8
is separated from the semiconductor body of the device 40 by
the insulating layer 70. The gate 68 overlies the first
region 50 from a location 73 where a junction 74 (between the
first and second regions 50 and 52) terminates adjacent
the insulating layer 70 and a location 75 where a junction 76
between the first region 50 and the further region 72)
terminates adjacent the insulating layer 70,
Upon biasing of the gate 68 with a positive voltage
(with respect to the cathode 58) exceeding a threshold value,
2~1~
a portion of the first region 50 immediately adjacent the
insulating layer 70 becomes inverted, thereby creating an
inversion channel 78, which can conduct electrons. Accordingly,
electrons from the second region 52 can :Elow in a distributed,
electron current path 80 through the inversion channel 78 and
further region 72, to the anode 60.
In order for the turn-off cell 46 to properly function,
the electrical resistance of the electron current path 80
must be below a value that limits forward biasing of the
junction 63 due to electron flow in the current path 80, to no
more than about one-half of the energy bandgap voltage of the
semiconductor material forming the j~mction 63. This enables
the device 40 to turn off, inasmuch as it removes the base
drive from the P-N-P transistor structure,-which in turn causes
the N-P-N transistor structure to turn off. In general, the
lower the resistance of the current path 80, the more current
that the turn-off cell 46 can turn off. Thus, an appropriate
value of resistance of the current path 80 depends in part
on how much current the turn-off cell 46 is required to
turn off,
The value of resistance of the electron current
path 80 depends in part on the resistance of the inversion
channel 78. The channel 78 resistance can be reduced by doping
the P2 portion of the first region 50, which contains the
inversion channel, to a concentration below about 1017 dopant
atoms per cubic centimeter. Additionally, the following
dcsign considerations contribute towards reducing the value
of resistance of the current path 80:
(1) The overall length of the current path 80 can
be reduced by reducing the hori7.0ntal dimension
of the first region 50, as viewed in FIGURE 2;
(2) The overall length of the current path 80 can also
be reduced by reducing the horizontal dimension
of the inversion channel 78, as viewed in FIGURE 2;
(3) The resistance of the inversion channel 78 can be
reduced by increasing the dimension of the channel
78 normal to the view of FIGURE 2 in relation to
the area of the cell 46, such as by reducing the
size of the cell 46 by reducing dimension 82, and,
additionally,by configuring the cell 46 round
or square, as opposed to elongated, as viewed from
: below in FIGURE 2; and
(4) The resistance of the first region 50 and further
region 72 can be reduced by doping these reglons
to high concentrations; however, the doping
concentration of the region 50 should not be too
high lest the forward drop of the device 40
becomes excessive.
In view of the present description,-those skilled in the art willbe
able to implement semiconductor devices 40 having appropriate
values of resistance of the electron current path 80 for
enabling proper functioning of the turn-off cell 46.
It will be recognized by those skilled in the art that
the gate 68, the insulating layer 70, and the portion of the
first region 50 containing the inversion channel 78, constitute
an MOS-type struFture for transporting electrons between
the second region 52 and the anode 60 (via the further
region 72), and is of the normally-off type.
The semiconductor device 40 can have two modes of
operation, one as a thyristor, and the other as an FET, providing
that the cell repeat distances or cell w:idths) 82 and 84 of
the turn-off cell 46 and the turn-on cell 42, respectively,
are each about equal to or less than the minimum thickness 86
of the N-type region 52. Accordingly, an electron current path
in the device 40 (not illustrated) between the cathode 58 and
the anode 60, via the inversion channels 66 and 78 and the
N-type second region 52 (hereinafter, "FET current path"), has
a sufficiently high conductivity to enable signîficant electron
current flow between the cathode 58 and the anode 60. Further,
it is desirable that the turn-on cell 42 be aligned with the
turn-off cell 46, with respect to the second region 52, as
illustrated, to maximize the conductivity of the FET current
path in the second region 52, for example, between the
inversion channels 66 and 78. Additionally, it is desirable
that the insulating layer 61 be overlain by the gate 60 and
adjoin the second region 52, as in region 88, between locations
62 and 90, for a distance which is between about 10 and 50
percent of the cell repeat distance 84 of the cell 42, with
20 percent being the most preferred value. This minimizes
the spreading resistance of the FET current path through
the second region 52. It is not necessary that the foregoing
distance between locations 62 and 90 be along a straight path.
Prior art MOS-type turn-on thyristor structures have been
fabricated with distances falling withln the foregoing
range, per se.
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As will be understood by those in the art, with the gates
- 60 and 68 biased with positive voltages above their respective
threshold values (thus creating the invexsion channels 66 and 78),
varying the magnitude of either or both of the voltages on the
gates 60 and 68 will vary the conductivity of the FET current
path from a minimum value, which is predominantly determined by
the resistance of the second region 52 (except in a low voltage
devioP 40), up to essentially-infinity. While operat:ing in the
FET mode, the semiconductor device 40 can conduct current
between the cathode 58 and anode 60 in either direction, as
opposed to only one direction(i.e.~ with the anode 60 biased
positive with respect to the cathode 58) as is the case when the
device 40 operates as a thyristor.
Referring to FIGURE 3, there is shown a graph of device
current versus time, illustrating various possible features
of turning-on and turning-off the semiconductor device 40
of FIGURE 2 in a bimodal fashion involving both thyristor and
FET modes of operation. To simplify discussion of FIGURE 3,
the following definitions will be used:
(1) "FET mode" means both gates 60 and 68 are biased
above their respective threshold voltages (that is,
both inversion channels 66 and 78 are present);
(2) "Thyrist~r turn-on mode" means that only the gaze
60 is biased above its threshold voltage
(inversion channel 66 present); and
(3) "Thyri~tor turn-off mode" means only the gate 68
is biased above its threshold voltage
(inversion channel 78 present).
Turn-on of the semiconductor device 40 may proceed
it three stages. In the first stage during time pleriod tl,
with the device 40 in the FET mode, the device 40 current rises
to a maximum FET current value determined by the resistance of
the FET current path 9 which can be varied, as discussed above,
by varying the magnitude of either or both of the voltages on
the gates 60 and 68. The time period tl, may be very short
inasmuch as the device 40 acts as a majority carrier device in
the FET mode. In the second stage during time period t2, the
device 40 is maintained ln the FET mode; however, this stage
may be deleted if desired. In the thlrd stage during time
period t3, the device 40 is in the thyristor turn-on mode. In
this mode the device 40 current is initially low during a delay
time and then rises rapidly during a rise time. The device 40
current attains a maximum device current value in its thyristor
turned-on condition which depends largely upon the conditions
of the external clrcuit (not shown,) in which the device 40
is connected.
Turn-off of the device 40 may proceed in three stages.
The first stage occurs during time periods t4 and t5. The
length of the time period t4 can be adjusted by varying the
magnitude of the voltage on the gate 68. At the beginning of
time period t5, the N-P-N and P-N-P transistor structures of
the device 40 no longer operate in a regenerative fashion, and
the device 40 current falls quickly during a fall time and then
tapers off while the holes in the device 40 are being sub-
~5 stantially eliminated, such as by recombining with electronsin the second region 52. In the second stage of turn-off
during time period ~6,the device 40 i5 maintained in the FET
mode; however, this stage may be deleted if desired. In the third
stage during time period t7, the device 40 is operated in the
thyristor turn-off mode and the device 40 current falls rapidly
to zero because it acts as a majority carrier device when in
thelFET mode.
One very important advantage ox turning-off the
device 40 in a bimodal fashion (both FET and thyristor
operation) is that it relaxes a design constraint on turn-off
cells, such as 50. This design constraint requires that each
of the turn-off cells be nearly identical to the other so that
each one turns off the same amount of current at the same
time during the thyristor turn-off mode. If one turn--off cell
were to operate later than the other turn-off cells, it would
carry more current at a higher voltage and could overheat and
be destroyed.
With the device 40 operating in the FET mode during
turn-off, all of its FET current paths (not illustrated
assuredly carry electron current and the oregoing problem
is not present. With the device 40 next operating in the
thyristor mode, its turn off cells would need to turn off a
significantly reduced current, thereby greatly amelioratlng
the foregoing problem. If the device 40 initially operates in
the FET mode (during turn-off) for a period of time sufficient
to allow the holes in the device 40 to be substantially
eliminated, its turn-off cells would assuredly turn off the
electron current in the device 40 at essentially the same time,
and the foregoing problem is not present.
Additionally, turning on and turning off the device 40
in the birl~odal fashion(just described)is espedally useful /certain
current switching applications. This is because the device 40
13
can be turned on or -turned off in a more gradual or
controlled manner, as opposed to prior art thyristor
turn-on and turn-off which is accompanied by abrupt
changes in device current whenever the N-P-N and
P-N-P transistor structures of the thyristor
commence regenerative operation (during turn-on)
or terminate regenerative action (during turnoff
Accordingly, the voltage transients generated
across the device 40 during turn-on or turn-off
in the bimodal fashion are significantly reduced.
This reduces the need for expensive noise fil-ters
or snubbers.
In fabricating the semiconductor device
40, the first through third regions, for example,
regions 50, 52 and 54, are suitably produced using
conventional techniques for making thyristors where
the junctions 63 and 74 comprise the main voltage
blocking junctions of the device 40. The gates
60 and 68 and their associated insulating layers,
as well as the further region 72, are suitably
fabricated using conventional techniques for making
FET's. The fourth region, for example, region 56,
is suitably fabricated using ei-ther thyristor or
FET techniques.
In the best mode contemplated for
practising the invention, the semiconductor device
40 includes an electrical short (not shown) between
5~
the cathode Rand the third region 54~ which
constitutes the base of the N-P-N transistor
structure. Such a short reduces the sensitivity
of -the device 40 to turn-on due to noise or
thermal currents in its semiconductor body, and also
increases the turn-off speed of the device 40. This
is because the short diverts part of the hole current
base drive of the N-P-N transistor structure and
directs it to the cathode 58 where it recombines
with elec-trons from the cathode 58. This type of
electrical short per se, is known in the art.
Additionally, in the best mode, the semiconductor
body of the device 40 comprises a silicon wafer.
While the invention has been described
with respect to specific embodiments by way
of illustration, many modifications and changes
will occur to those skilled in the art. For
example, complementary semiconductor devices
could be made wherein the foregoing description
of the invention would be applicable if P-type
material were substituted for N-type material, and
vice-versa, and holes substituted for electrons,
and vice-versa. Additionally, while the device 40
may be fabricated by a planar diffusion process,
as illustrated, other processes, involving the
etching of a groove into a device semiconductor
body, can equally well be used. Such a groove can
have various shapes depending upon whether a
preferential etch or isotropic etch is used, and
upon the crystallographic orientation of the
semiconductor body. Those skilled in the art will
appreciate the range of possible groove shapes.
By way of example, a suitable groove shape is that
of a flat-bottomed "V", as further described, for
example, in V.A.K. Temple and P.V. Gray, "Theoretical
Comparisons of DMOS and VMOS Structures for Voltage
and On-Resistance", Reprint from International
Electron Devices Mee-ting, December 1979, pages
88-92. Further, the second region 52 can be
modified to have its portion which is in contact
with the first region 50 doped to a concentration
substantially higher than the concentration of the
remainder of -the second region 52 (as described
above), whereby the device would become what is
known in the art as an asymmetrical device. It is,
therefore, to be understood that the appended
claims are intended to cover the foregoing and all
such modifications and changes as fall within the
true spirit and scope of the invention.
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