Note: Descriptions are shown in the official language in which they were submitted.
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BA~KCPOlJND OF THE INVENTInN
This invention relates to an integrated semiconductor circuit
with a bipolar transistor structure in which the emitter region as
well as the base region on the silicon semiconductox substrate are
produced by out-diffusion of a doped layer structure deposited
directly on the substrate and which serves as an additional wiring
plane. The invention also relates to a method for the fabrication of
the semiconductor device.
The smallest possible dimensions of bipola- transistors are
determined by the relatively large metallization raster, s nce from
the metal conductor track plane contacts must be produced to the
emit-ter and collector zones as well as to the base zone.
lany attempts have been made to alleviate the wiring problem
or example by a polysilicon wiring, as described in If Trans.
Electron. Devices, Vol. Ed-27, No. 8, August 198n, at pages 137~ to
1384 in an article by ~.D. Tang et al, or by a polyzide wiring as
described in IEEE Trans. Electron. devices, Vol. ED-27, No. 8, August
1~80, at pages 13~5 to 138~ in an article by Y. Sasaki et al.
Polysilicon wirings, however, have relatively high resistance and
result in high series resistances. Since, as a rule, with this
procedure the emiter is diffused out of the polysilicon, and the n+
and p+ dopings diffuse one into the other, there results moreover a
high emitter-base capacitance, whereby the frequency response is
adversely affected. The application published in Sasaki's article of
a wiring consisting of molybdenum silicide does indeed reduce the
wiring resistance relative to the polysilicon wiring considerahly.
But the method for produciny this type of ~/iring is very costly
because of the required tasks.
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SUMMARY OF THE INVENTION
It is, therefore, an object of the invention to disclose
an integrated circuit with bipolar transistor structures in which
the contacting and joininy of the base, emitter and collector
zones is independent of the metallization pitch and therefore makes
possible a higher packing density. Moreover, the series resis-
tance to the base zone is to be reduced.
It is also an object of the invention to provide a sim-
pler methcd for the production of the circuit through mask-saving
process steps.
The solution of this problem according to the invention
is characterized in -that the layer structure serving as wiring
plane consists of a cloped silicide of a metal of high melting
point. Included under the scope of the invention is the idea that
the metal silicide compound has an excess of silicon in comparison
to the stoichiometry of the compound, to permit reoxidation without
consumption of silicon from the substrate. Preferably the com-
pound consists of a silicide of the metals tantalum, tungsten,
molybdenum or titanium. The layer thickness of the metal silicide
structure ranges from 150 to 300 nm, preferably abouk 200 nm.
The invention also provides a method :Eor producing npn
bipolar transistor structure, in which an emitter region as well
as a base region in a semiconductor substrate are produced by out-
diffusion of a doped layer structure deposited directly on said
substrate and serving as an additional wiring plane said method
comprising the steps of:
a) defining the active areas of the structure by produc-
ing n+-doped zones in a p doped silicon substrate by
masked ion implantation;
b) applying an epixtaxial n-doped layer on the n+-doped
zones;
c) masked etching of an insulation trench in the region
between the n+-doped zones;
d) producing the insulation oxide in the region of the
insulation trench;
e) n~-dep-th diffusing of a collector zone aEter a layer
which masks the other regions has been applied;
f) detaching the masking layer for the collector depth
diffusion and over-etching the substrate surface;
g) whole-area depositing of a first metal silicide layer
admixed with p-doping substances, silicon being
present in excessi
h) structuring of the p-doped silicide layer in the base
zone of the transistor;
i) forming the base with p-doping ions after producing
the mask for the base implantation;
-3a-
j) out-diffusing the p-doping substances from the sift
cide base contact region;
k) executing an oxidation process;
1) performing an anisotropic dry etching process to re-
move the oxide layer in the emitter and collector
terminal zones;
m) whole-area depositing of a second metal silicide
layer provided with n-doping substances;
n) structuring of the second n-doped silicide layer in
-the emi-tter region and collector contact region (12),
the struc-tures overlapping the structures of the first
metal silicide layer;
o) out-diffusing of the n-doping substances from the
second silicide layer to form the emitter zone;
p) whole-area depositing of an insulation layer acting as
intermediate oxide;
I) opening of the contacts to the p-doped regions of the
first metal silicide layer and to the n-doped regions
of the second metal silicide layer; and
r) metallizing and structuring the outer metal conductor
-3b-
track plane.
Other features and advantages of the invention will be
apparent from the following description of the preferred embodi-
ments and from the claims.
For a full understandlng of the present invention,
reference should now be made to the following detailed description
of the preferred embodiments of the invention.
3c-
BRIEF DESCRIPTION OF THE DRA~IIN~S
Figs. 1 to 3 are sectional viols of the integr3te~
semiconductor incorporating bipolar structure in various stages of
completion.
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DETAILED D~S~IPTTON
The process sequence for the production of a circuit with a
bipolar transistor according to the invention will be described more
specifically with reference to Figs. 1 to I. In the rigs. only the
process steps essential to the invention are illustrated in sectional
views. Like pa-ts are parked with the same reference synbols.
Fig. 1: On a monocrystalline, p-doped (100)-oriented silicon
substrate wafer 1 having a specific resistance of 10 Ohm cm, the
active areas of the circuit are defined by producing n~-doped zones
2 by masked ion implantation. Then, by an epitaxial deposition
method, an n -doped silicon layer 3 having a specific resistance of
2 Oh cm is applied on the n+-doped zones 2 and the insulation
trench is etched by jeans of a mask covering the active areas (not
shown in the Fig.). Thereafter the insulation oxide 4 is produced in
the area of the insulation trench. Then, after applying a layer
which masks the other regions, thQ n+ depth diffusion 5 is carried
out in the collector zone of the bipolar transistnr. After removal
of the mask for the collector depth diffusion 5 the substrate su-face
is etched over the whole area. Then follows the whole-area deposition
of a tantalum silicide layer 7 admixed with boron (first silicide
layer) in a layer thickness of 2no no, silicon being present in excess
(Ta:Si C 1:2). To define the base contact region (6), this TaSi2
layer 7 is provided with an oxide layer 8 to reduce the overlap
capacitances and to prevent the out-diffusion of boron, and it is
structured with the oxide layer 8 as illustrated in Fig. 1. after the
production of an inplantation nask for the base implantation (6), the
base 6 is implanted with boron ions, whereupon the boron is diffused
out of the tantalum silicide layer 7 at 80n to 1~00~. In sn
doing, the base implantation is also activated. There is formed the
device shown in Fig. 1 with the p+-diffused base contact zone
~arkod with the reference symbol and the base marked 6.
. 5 _
a8
Fig. I: After execution of an oxidation process ~reoxidation
of the TaSi~, excess silicon SiO2 being formed), the oxide layer
is removed in the emitter zone (11) an,i in the collector contact area
(12) by an anisotropic dry etching process, SiO2 being left at the
silicide edges. On the exposed emittel and collector contact
terminal areas, arsenic-doped tantalum silicide(lO)(second s~licide
layer) is deposited by sputtering of an arsenic-doped tantalum
silicide target and is structured as can be seen from Fig. 2. The
first silicide layer 7 is overlapped by the second silicide layer
ln. For emitter formation (zone 11) arsenic is then diffused out of
the tantalum silicide layer lO at 800-l~OOr. Simultaneously the
diffused n~-collector contact terminal 12 is formed.
Fig. 3: Shows the finished bipolar transistor structure after
an insulation layer 13 acting as intermediate oxide has been producerl.
The finished structure is shown with the contacts tn the boron-~oped
areas of the first tantalum silicide layer 7 (p+ base 9) and to the
arsenic-doped areas of the second tantalum silicide layer lO (n+
collector zone 12 or emitter 11) opened. The completed metallization
with aluminum contact 14 and 15 are also shown.
The advantage of the invention over known bipolar transistor
structures and their methods of fabrication resides in that with only
one additional mask (contact between the first and second metal
silicide) one obtains two low-resistance almost independent wiring
planes (7 and lO) which, in particular, as cross couplings in statlc
memory cells permit a higher packing density.
In addition, the arrangment according to the invention results
in the following advantages:
1. The contact metal/silicide (14 and 7, 15 and ln) has a
resistance lower by rne order of magnitude than the known contact
metal/polysilicon.
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2. The lead from the contact metal~silicide (lll, 7) to the
hase (9) has a resistance lower by one order of magnitude than
polysilicon.
3. In the critical etching of silicirJe (7, 10) on silicon it
is easier, because of the different materials, to achieve an etch ng
stop or respectively to carry out an endpoint control than when using
polysilicon.
There has thus been shown and described a novel bipolar
transistor structure and method therefor which fulfills all the
objects and advantages sought therefor. ~lany changes, modlfications,
variations and other uses anri applications of the subject invention
will, however, become apparent to those skilled in the art after
considering the specification and the accompanying drawings which
disclose preferred emborliments thereof. All such changes,
modifications, variations anri other uses and applications which do
not depart from the spirit and scope of the invention are deemed to
be covered by the invention which is limited only by the claims which
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