Note: Descriptions are shown in the official language in which they were submitted.
3:~
INPUT ~UFFER CIRC~IT FOR RECEIVING MULTIPLE
LEVEL INPUT VOLTAGES
Technical Field
This invention relates generally to buffer circuits,
and more particularlyl to buffer circuits which are
operable with variable ranges of input voltages.
Background Art
For many applications buffer circuits must be
operable for various ranges of input voltages. For
example, applications commonly exist when a buffer circuit
must accept both TTL voltage levels and MOS voltage
levels. Previously, multiple voltage level buffer
circuits requiring circuitry dedicated for each voltage
level have been used. Such circuits require multiple
inputs and utilize circuitry which detects an input
voltage level. Others have used a trinary input buffer
which is also known as a tri~state device. Trinary input
buffers however typically consume power when in a static
state. Other buffer circuits which accept multiple level
input voltages require a separate pin in an integrated
circuit package which is used to indicate what level to
detect.
Summary of the Invention
An object of the present invention is to provide an
improved input buffer circuit for receiving multiple level
input voltagesO
Another object of the present invention is to provide
an improved input buffer circuit having a single input.
In carrying out the above and other objects of the
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present invention, there is provided, in one form, an
input buffer circuit having a single input for receiving
input voltages having varying voltage swings. First and
second inverter circuits having differing trip points are
coupled to level shifting means. The level shifting means
vary the level of swing of the input voltage and buffer
the input voltage. In one form, voltage coupling
circuitry is interposed between the level shifting means
and latching means. The latching means provide the input
voltage as an output signal at a predetermined voltage
level. In a preferred form, the voltage coupling
circuitry comprises capacitors which store the level
shifted input voltage. In another form, digital logic is
used to selectively couple the input voltage to an output
terminal from level shifting means.
The above, and other objects, features and
advantages of the present invention will be best
understood from the following detailed description taken
in conjunction with the ~ollowing drawings~
Brief ~escription of the Drawings
FIG. 1 illustrates in partial schematic form a first
embodiment of the present invention;
FIG. 2(a) illustrates in partial schematic form a
partial equivalent circuit of the circuit of FIG. 1 for a
predetermined mode of operation;
FIG. 2(b) illustrates in partial schematic form a
partial equivalent circuit of the circuit of FIG. 1 for a
second predetermined mode of operation; and
FIG. 3 illustrates in partial schematic form another
embodiment of the present invention.
Detailed Description of the Invention
Shown in FIG. 1 is an input buffer circuit 10 which
~2~ 3:~
is capable of receiving an input voltage VIN having a
variable range of voltages. In a preferred form, input
voltage VIN may vary between a minimum and a maximum
voltage level within each range. A bipolar transistor 11
has a collector electrode connected to both a base
electrode thereof and to a positive supply voltage
VDD. An emitter electrode of transistor 11 is
connected to a source electrode of a P channel transistor
12. A drain electrode of transistor 12 is connected to
both an input of a level shift circuit 13 and a drain
electrode of an N channel transistor 15. Both a gate
electrode of transistor 15 and a gate electrode of
transistor 12 are connected to input voltage VIN, and
a source electrode of transistor 15 is connected to the
substrate thereof. The source electrode of transistor 15
is connected to a digital ground supply voltage VDG
and to a source electrode of a P channel transistor 16. A
gate electrode of transistor 16 is connected to input
voltage VIN, and a drain electrode of transistor 16 is
connected to both an input of a level shift circuit 17 and
a drain electrode of transistor 18. A gate electrode of
transistor 18 is connected to input voltage VIN and a
source electrode of transistor 18 is connected to the
substrate thereof. The source electrode of transistor 18
ls also connected to negative supply voltage Vss.
While a specific bipolar device and P channel and N
channel MOS devices are shownl it should be clear that
buffer circuit 10 may be implemented by completely
reversing the processing techniques (e.g. P channel to N
channel) or by using other types of transistors. Level
shift circuits 13 and 17 are conventional level shifting
circuits which utilize supply voltages VDD and Vss
and digital ground VDG as illustrated in FIG. 1. An
output of level shift circuit 13 is connected to an input
of an inverter circuit 20 which utilizes supply voltaqes
VDD and Vss. An output of inverter circuit 20 is
connected to a ~irst electrode of a capacitor 22. An
output of level shift circuit 17 is connected to an input
of an inverter circuit 21 which also utilizes supply
voltages VDD and Vss. An output of output
inverter 21 is connected to a first electrode of a
capacitor 23. A second electrode of capacitor 22 is
connected to a second electrode nf capacitor 23 at a node
24. An input of an inverter circuit 25 is connected to
node 24, and an output of inverter circuit 25, which
provides an output voltage, is connected to an input of an
output inverter circuit 26 via an outpu~ node 27. An
output of inverter 26 is connected to node 24. Output
inverter circuits 25 and 26 utilize supply voltages
VDD and VDG as illustrated. An intrinsic
parasitic diffusion diode 28 exists between node 24 and
positive supply voltage VDD. An intrinsic parasitic
diffusion diode 29 exists between node 24 and negative
supply voltage VSS
In operation, transistors 11, 12 and 15 function as a
first inverter circuit and transistors 16 and 18 function
as a second inverter circuit. The digital ground voltage
is arbitrarily chosen as a mid supply voltage. Buffer
circuit 10 can detect input signals having three different
voltage levels. The first voltage level range is from
VDG to VDD, and the second voltage level range is
from VDG to Vss. The third voltage level range is
from VDD to Vss. The first inverter circuit of
transistors 11, 12 and 15 detects input voltage level
swings between VDG and VDD. The second inverter
circuit of transistors 16 and 18 detects input voltage
level swings between VDG and Vss. Both inverter
circuits are utilized to detect input voltage level swings
between Vss and VDD. The physical dimensions of
the gate electrode of transistor 15 is made large in
--5--
comparison to the dimensions of the gate electrode of
transistor 12 so that a TTL switchpoint of approximately
1~4 volts is established for the first inverter comprising
transistors 11, 12 and 15 assuming VDD i5 five volts
and VDG is zero volts. In the second inverter circuit `
of transistors 16 and 18, the physical dimensions of the
gate electrode of transistor 16 are preferably made larger
than the gate electrode dimensions of transistor 18 to
compensate for conventional back gate bias effects and to
establish a typical MOS switchpoint halfway between
VDG and Vss. Level shift circuit 13 translates
the voltage swing from VDG to VDD at the input
thereof to Vss to VDD. Similarly, level shift
circuit 17 translates the voltage swing from VDG to
Vss at the input thereof to Vss to V~D. The
purpose of having a full voltage level swing at the
outputs of inverters 20 and 21 is to insure that a
sufficient voltage swing exists to switch output inverter
25.
Initially, assume that the input voltage swing is
from VDG to VDD. The input of level shift circuit
17 will remain constant at Vss because the input
voltage is always sufficient to make transistor 18
conductive and transistor 16 nonconductive regardless of
the input voltage swing in this ~ange. Therefore, the
input of inverter 21 will remain at a logic low value and
~he first electrode of capacitor 23 will be clamped at
approximately VDD. However, the input of level shift
circuit 13 will receive the inverted input voltage
VIN. Assuming for the purpose of illustration only
that VDD is positive five volts, VDG is zero volts
and Vss is negative five volts, if the input of level
shift circuit 13 is five volts, the output of level shift
circuit 13 is also five volts. Also, if the input of
level shift circuit 13 is zero volts, the output of level
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shift circuit 13 transitions to negative five volts. A
partial equivalent circuit of buffer circuit 10 is shown
in FIG. 2(a~ when the input voltag~ varies in the mid to
upper supply voltage range, i.e., where VIN varies
from zero to five volts. It can thus be readily shown
that the A.C. voltage level at node 24, V24, ignoring
the effects of output inverter circuit 26 is
approximately:
V24 = Vl[c22/(c22 + C23 + Cp)]
where V1 = the voltage at the output of inverter 20
C22 = the capacitive value of capacitor 22
C23 = the capacitive value of capacitor 23; and
Cp = the capacitive value of the parasitic
capacitance associated with intrinsic diodes
28 and 29.
Before the voltage at node 24 varies, the voltage will be
held by inverter 26 at either VDD or VDG. Voltage
V24 varies in accordance with the given equation to
establish a switchpoint voltage for output inverter 25.
Therefore, if capacitors 22 and 23 are substantially equal
in value, the voltage swing at node 24 will be slightly
less than five volts depending upon the amount o
parasitic capacitance. Assume for the purpose of
illustration only that input buffer circuit 10 has been
operable for several transitions of VIN between
VDG and VDD. Output inverter 26 functions as a
feedback device. When VIN is VDG volts, the
output voltage is at VDD volts and inverter 26 tries
to keep node 24 at VDG volts. Since the current
flowing through capacitor 22 must be lar~e enough to
overcome the effects of output inverter 26, output
inverter 26 is made weak enough to be easily overridden.
Assume now that VIN increases toward VDD volts so
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--7--
that the voltage potential at node 24 increases toward
VDD When the voltage at node 24 is made to equal
approximately the trippoint voltage of output inverter 25,
output inverter 25 trips so that the output changes to a
low logic value of VDG volts. Once output inverter 25
changes logic state or trips, output inverter 26 helps
drive node 24 ~o VDD volts. When the input voltage
VIN swings back to VDG, node 24 transitions back
to VDG volts, and the output becomes VDD v4lts
again. Level shift circuit 13 and inverter 20 function
jointly to guarantee that the transition voltage at the
input of output inverter 25 will be sufficient to trip or
switch inverter 25.
By the nature of the capacitive coupling of the input
voltage of output inverter 25 by capacitors 22 and 23,
output inverter 25 will trip logic states when VIN
switches levels within its voltage swing range. Thus
input buffer circuit 10 is edge triggered. Therefore, if
VI~ is initially equal to VDG, an ambiguity in the
output may exist until a voltage transition is coupled by
capacitor 22 or capacitor 23 to node 24. However, once an
initial edge or transition occurs, the output will not
experience another indeterminate state.
In a second mode of operation, assume that the input
voltage swing is from VDG to Vss volts. The input
of level shift circuit 13 will remain constant at VDD
because the input voltage is always sufficient to make
transistor 12 conductive and transistor 15 nonconductive
regardless of the input voltage level within this range.
Therefore, the input of inverter 20 will remain at a logic
high value and the first electrode of capacitor 22 will
remain clamped at Vss. However, the output of the
inverter comprising trànsistors 16 and 18 will logically
invert the input voltage as the input voltage varies in
the range between VDG and Vss. Assuming again
that VDD is positive five volts, that VDG is zero
volts and that Vss is negative five volts, if VIN
is initially at VDG volts, the input of level shift
circuit 17 is negative five volts and the output of level
shift circuit 17 is also negative five volts. Similarly,
if VIN is at Vss volts, the input of level shift
circuit 17 is at VDG volts and the output of level
shift ci~cuit 17 is at positive five volts. A partial
equivalent circuit of buffer circuit 10 is shown in FIG.
2(b) when the input voltage, VIN, varies in the mid to
lower supply voltage range (VDG to Vss) causing
the equivalent input voltage to vary from positive five to
negative five volts. It can readily be shown that the
A.C. voltage now at node 24 and again ignoring the effects
1S of output inverter 26 is substantially:
V24 = V2 [C23/(C22 + C23 ~ Cp) ]
where V~ = the voltage at the output of inverter 21.
Again, if capacitors 22 and 23 are substantially e~ual in
value, the voltage swing at node 2~ will be slightly less
than five volts depending upon the amount of parasitic
capacitance. When the equivalent input voltage swings to
Vss volts, the output voltage is at a low logic value.
When the equivalent input voltage transitions up to
VDD volts, the output voltage is at a high logic value
level. Level shift circuit 17 and inverter 21 function
jointly to guarantee that the transition voltage at the
input of output inverter 25 will be sufficient to trip or
switch inverter 25.
In a third mode of operation, assume that the input
voltage swing is from Vss to VDD volts~ The
inputs of level shift circuits 13 and 17 will swing in the
same direction for a transistion in the input voltage
causing corresponding inversions at the outputs of
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inverters 20 and 21. As a result of the level shifting,
voltages V1 and V2 will each change ten volts A.C..
As a result of the capacitive ratios and capacitors 22 and
23 having substantially equal values, both voltage V1
and V2 will be reduced to approximately five volts and
summed at node 24. Therefore, approximately ten volts of
A.C. voltage swing is present at node 24. Parasitic
diodes 2B and 29 which result from the drain to substrate
interface of the two small transistors used to form
inverter 26 will clamp node 24 at either VDG - 0.6
volts or VDD ~ 0.6 volts. The clamping action
provided by intrinsic parasitic diffusion diodes 28 and 29
is desirable because the clamping allows node 24 to
recover faster and accept a higher frequency input
signal.
By now it should be apparent that an input buffer
which is voltage edge sensitive and ~-hich has a single
input which may accept three ranges of input voltages has
been provided. The edge detection is accomplished by
lengthening the edges of the input signal via level
shifting circuitry and by utilizing capacitors 22 and 23
to trigger a latch implemented in the form of inverters 25
and 26. Capacitors 22 and 23 are substantially
insensitive to voltage spikes and edges created by noise
and transients due to the presence of level shift circuits
13 and 17 and inverters 20 and 21 which function as
buffers. No additional controls indicating which range of
input voltages is being utilized is required. It should
also be noted that an input buffer which may accept more
levels of an input voltage may be provided by utilizing
additional level detecting circuitry. Such circuitry for
each additional level would include additional inverters
such as transistors 16 and 18 coupled in series with an
additional level shifting circuit and an additional
capacitor. Such additional circuitry would be coupled to
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the input of output inverter 25.
Shown in FIG. 3 is another embodiment of the present
invention which func~ions as a multiple level input buffer
circuit 40 which detects the upper or lower rail voltage.
Due to the absence of capacitors, this embodiment is not
edge sensitive but rather rail sensitive. An inverter 41
has an input connected to an input voltage VIN and to
an input of an inverter 42. An output of inverter 41 is
connected to an input of a level shift circuit 43, and an
output of inverter 42 is connected to an input of a level
shift circuit 44. Inverter 41 operates in a voltage range
between a positive supply voltage VDD and a digital
ground voltage, VDG, as illustrated. Inverter 42
operates in a voltage range between digital ground,
VDG, and a negative supply voltage Vss. Level
shift circuits 43 and 44 are each cor.nected to Vss,
VDD and VDG and shift an input voltage between
VD~ and VDD. An output of level shift circuit 43
is connected to an input of an inverter 46 which operates
between voltages VDD and VDG. An output of level
shift circuit 44 is connected to an input of an inverter
47 which also operates between voltages VDD and
VDG. An output of inverter ~6 is connected to a first
terminal of a switch 48, to a first input of a dual input
NAND gate 49 and to a first input of a dual input NOR gate
50 at a node 51. An output of inverter 47 is connected to
a first terminal of a switch 53, to a second input of NAND
gate 49, and to a second input of NOR gate 50 at a node
52. In a preferred form, switches 48 and 53 are
implemented by CMOS transmission gates which are clocked
in a conventional manner. An N channel control terminal
of switch 48 is connected to an input of an inverter
circuit 55, and an output of inverter circuit 55 is
connected to an N channel control terminal of switch 53.
Inverter circuit 55 operates between voltages VDG and
9~
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VDD as illustrated. An output of NAND gate 49 is
connected to a complementary set terminal, S, of a
conventional SR flip flop circuit 57. An output of NOR
gate 50 is connected to a reset terminal, R, of SR flip
flop circuit 57. A Q output of flip flop circuit 57 is
connected to the input of inverter circuit 55. A second
terminal of both switches 48 and 53 are connected together
at a node 58 to an input of an inverter circuit 59. An
output of inverter circuit 59 provides an output signal.
Inverter circuit 59 operates between voltages VDG and
VDD.
In a first mode of operation, assume that the input
voltage varies from VDG to VDD. The input of
level shift circuit 44 is always a low logic level.
Therefore, the output of inverter circuit 47 is fixed as a
logic high level. When VIN transitions from VDG
to VDD, level shift circuit 43 maintains a low logic
level of VDG. Although level shift circuit 43 does
not function to level shift in this situation, level shift
circuit 43 equalizes the voltage delay of the input
voltage VIN to node 24 with the voltage delay
associated with level shift circuit 17. Inverter 46
provides a high logic level of VDD volts. The high
logic levels present at both nodes 51 and 52 function via
flip flop circuit 57 and associated logic to make switch
48 conductive and switch 53 nonconductive. Therefore, the
output of inverter circuit 59 is a logic low level. As
the input voltage changes, the output voltage will vary in
an inverse manner. In a preferred form of SR flip flop
57, the reset function is dominant. Therefore, when the
voltage potential at node 51 returns to VDG, although
the complementary set terminal changes lo~ic level, the
reset terminal of SR flip flop 57 remains at a logic low
level. As a result, the Q output of SR flip flop circuit
57 remains at a logic high level maintaining switch 48
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conductive. The only possible indeterminate state the
ou~put can have is if initially VIN is at VDG.
However, once VIN transitions to a rail voltage, no
indeterminate states will occur at the output.
In a second mode of operation, assume that the input
voltage varies from VDG to Vss. The input of
level shift circuit 43 is always at a high logic level.
Therefore, the output of inverter circuit 46 remains as a
logic low level. When the input voltage transitions to
Vss, a logic low occurs at the output of inverter 47.
Therefore, switch 53 is made conductive and switch 48
nonconductive by flip flop circuit 57 and associated
logic. Again, an indeterminate state may initially occur
only i~ VIN is at VDG-
In a third mode of operation, assume that the input
voltage varies from VDD to Vss. When the input
voltage is at VDD, switch 48 is conductive and switch
53 nonconductive, and the output is at a logic low level.
When the input voltage is at Vss, switch 53 is
conductive and switch 48 nonconductive, and the output isat a logic high level. Thus, buffer circuit 40 detects
which rail voltage is reached and provides a corresponding
output voltage. During at least one of the multiple
levels of input voltages, level shift circuit 43 is not
needed for voltage level translation due to the fact that
the level of the input voltage is already adequately
translated for inverter circuit 46. However, in this mode
of operation level shift circuit 43 is used in conjunction
with level shift circuit 44 to equalize the delay time of
the input signal through the two paths leading from the
input terminal to nodes 51 and 52, respectively. A buffer
circuit which can receive via a single input terminal an
input voltage having a plurality of voltage level swings
has again been provided. Although an input voltage
transition to one of the rail voltages is initially
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necessary for the output voltage to be in a determined
state, the initial ind~terminate state may be elminated by
using a conventional power on reset circuit which provides
an initial rail voltage at the Q output of SR flip flop
circuit 57 immediately upon powering up of the circuit.
While the invention has been described in the context
of a preferred embodiment, it will be apparent to those
skilled in the art that the present invention may be
modified in numerous ways and may assume many embodiments
other than that specifically set out and described above.
Accordingly, it is intended by the appended claims to
cover all modifications of the invention which fall within
the true spirit and scope of the invention.
