DATA PROCESSING SYSTEM WITH MULTIFUNCTION NIBBLE SHIFTER

SYSTEME DE TRAITEMENT DE DONNEES AVEC DISPOSITIF MULTIFONCTION DE DECALAGE DE QUARTETS

English Abstract

ABSTRACT
A data processing system having separate kernel,
vertical and horizontal microcode, separate loading of
vertical microcode and a permanently resident kernel
microcode, and a soft console with dual levels of capability.
The system includes a processor having dual ALC and microcode
processors, and an instruction processor. Also included are
a processor incorporating a multifunction processor memory, a
malfunction nibble shifter, and a high speed look-aside
memory control.

Claims

What is claimed is:
1) In a data processing system including processor means
for processing said data memory means for storing and
providing said data, and memory bus means for conducting
said data between said processor means and said memory
means, said processor means, comprising:
first bus means,
second bus means,
input means connected from said memory bus means
to said first bus means,
output means connected from said second bus means
to said memory bus means,
CPU means having an input connected from said
second bus means and an output connected to said first bus
means, and
nibble shift means having an input connected from
said first bus means and an output connected to said second
bus means for
(a) conducting said data between said
first bus means and said second bus means,
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(b) performing nibble shift data
manipulation operation in conjunction with arithmetic and
logical operations performed by said CPU means, and
(c) performing data alignment operations,
upon data being read from said memory means to said CPU
means and upon data resulting from said CPU means
operations being written from said CPU means to said memory
means.
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Description

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DIGITAL DAT~ PROCE5SING SYSTEM/420
Cros~ Reference To Related Applica~ion,
The present application is related, in part, to
copending Canadian Patent Applications Serial ~u~ers 4i9,755
439,798, 439,799, 439,800~ 439,801, 439,802 and 439,803
all filed October 2 6, 1983 .
1. ~ield of the Invention
- The presen~ invention relates to a high speed,
compact d~ta pxocessing system and, more part~cula-lyr to
circuitry therein to enhance operating speed, efficiency
and capabilities of such a system.
2. Description of Prior Art
~ common practice in the computer in~us~ry is
for a manufacturer to orovide a family of relatea computer,
or d ta processing, systems. Various computers in such a
family will be distinguished by size, complexity, capability
and cost. Because of cost and, therefore, complexi~y
constraints, lower level systems in such a family are usually
not able to provide the capabilities and functions of the
higher level systems~ A lower level system may ~o~, for
example, provide as high a speed of operation or as large a
memory space as a higher level system. In addi~ion, a
lower level system often may not be able to execute a
program written for a
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higher level system because the lower level system does
not offer the full functions and capabilities of the
higher level system. Such a family of systems may
therefore have ~pward compatibility, that is, programs
written on lower level systems mzy be executed on hi5her
level systems, but will not provide corresponding
downward compatibility. For full compatibility within 2
computer system family, the lower level systems should
offer, in general, the functionality and capabilities of
the higher level s~stems.
The present invention provides computer system
improvements which bear upon the above noted computer
system capabilities, thus improving computer system
speed, efficiency and capability, and also providing a
solution for the aforementioned problems and limitations
of the prior art, as will be discussed in detail herein
bçlow.
SUMMARY OF T~E INVE~TII:)N
The present invention re'ates to computer system
ele~ents providing increased capabili'y and efficiency.
The present invention includes z system having separate
kernel, vertical znd horizontal microcode, separate

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loading of vertical microcode and z permanently resident
kernel microcode, and a soft console with dual levels o~
capability~ The present invention includes a processor
having dual ALC and microcode processors, and an
instruction processorO Also included is a processor
incorporating a multifunction processor memory, a
multifunction nibble shirter, and a high speed
look-aside memory ~ontrol.
It is thus advantageous to incorporate the present
invention into a computer system because capability and
efficiency is increased.
It is thus an object of the present invention to
provide an improved computer system.
It is another object of the present invention to
pL-ovide an improved computer system providiing increased
speed and efficiency of operation.
It is yet another object of the present invention
to provide an improved computer system providing
increased capability and functionality.
Other objects and advantages of the present
invention will be understood by those of ordinary skill
in the art, after referring to the following detailed
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description of a preferred embodiment and drawings
wherein:
BRIEF DESCRIPTION OF ~RAWINGS
Fig. 1 is a block diagr2m of a computer system
incorporating the present invention;
Fig. 2 is an illustration of certain, typical
instructions;
Fig. 3 is a diagrammic representation of a single
level address translation;
Fig. 4 is a diagrammic representation of a two
lQvel address translation;
Figs. 5 and 5A are a detailed block diagram of the
present system control unit;
Figs. 6 and 6A are a detailed block diagram of the
present system processor unit, and
Fig 7 is a detailed block diagram of a portion of a
memory control unit.
~ESC~IPTION OF T~E PREFERRED E~BODIMENT
The following descriptlon presents the struc~ure
and operatlon of a computer system incorporating a

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.
presently preferred embodiment of the present invention.
In the following description, the general structure and
operation of the present system will first be described
in an introductory overview. Next, certain basic
eatures of the present system will be further described
as a further introduction to followin~ detailed
~escriptions of the system. The system will then be
described in detail, followed by yet further detailed
descriptions of certain features of the present system
as necessary.
Certain conventions are used throughout the
following descriptions to enhance clarity of
presentation. First, each figure element referred to in
the rollowing descriptions will be referred to by a
t~lree OL four diglt referenc~ number. ~he most
significànt digit of a three digit reference number or
most significant two digits of a four digit reference
number identify the particular figure in which an
elemenL referred to by that reference numker first
appears. The two least significant digits of a
particular r~ference number identlfy the particular
element appearing in that figure. For example,

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reference number 319 refers to the ninteenth element
appearing in Figure 3 while reference number 1020 re~ers
to the twentieth element appearing in Figure lOo A
particular reference number assigned to a particular
figure element is therefore always used to refer to that
particular figure element. Therefore, element 319,
~hich first appears as element 19 in Figure 3, will
thereafter be referred to by reference number 319 in all
figures or descriptions.
Next, certain of the figures presented in
conjunction with the following descriptions may occupy
more than one drawing page. In such instances, a common
figure number will be assigned to the drawing pages
comprising that figure, and a letter designation will be
a~pended to identify a particular drawing page of the
figure. For example, figure 3 may occupy three drawing
pages. The first page will be identified as Fig. 3, the
second as Fig. 3A, and the third as Fig. 3B.
Finally, interconnections between related circuitry
or system elements may be represented in two ways.
First, inter~onnections between system elements may be
:epresented by common signal names or references rather
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than by drawn representations of wires or buses.
Second, common connections between circuit:ry or system
elements may be indicated by a bracket terminating a
lead and enclosing a designation of the form "A~b". "A"
indicates other figures having a connection to the same
common point while "b" designates a partiCular
connection point.
INTRODUCTORY OVE~V~EW
The following introductory overview will first
identify and briefly describe the major elements of the
present digital computer ~ystem. Certain features of
operation of the present system will then be described
in further detail as an introduction to following
detailed descriptions o~ the present system.
A. System Overview (Fig. 1)
Referring to fig. 1, a block diagram of Computer
System (CS) 101 is shown. Major elements of CS 101 are
Memory ~MEM) 102, Control Unit (CU) lC4, and Processor
Unit (~U~ 106. MEM 102 is used to store, for example,

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user programs comprising data and instructi~ns. ME~ 102
is descrIbed in detail in related copending Canadian
Patent Application Serial No~ 441,238, filed October 26, 1983,
MEM 102 will not be described in further detaiL herein except
as necessary for understanding of the structure and oper~tion
of the remaining elements of CS 101. CU 104 and PU 106,
which will be described in detail in the following descxîpti~ns,
respectively perform system control and program execution
functions.
Major buses of CS 101 include Memory Address ~AD)
Bus 108, whi.ch conducts memory read and write addresses
from PU 106 and CU ln4 to MEl~ 102~ ~Semory Data (MDA) Bus
110 conducts data and instructions fr3m ~M 10~ to CU 104
an2 PU lG6. Data (D) Bus 112 i~ cor~r.ected between CU ~04
and PU 106 as a ~rimary path of _n~onmation exchan~e between
CU 104 and PU 106.
Referring to CU 104, major elements of CU 104 are
Instruction Prefetch and Decoder ~IPD) 114, Microsequencer
~US) 116, Memory Control (MC3 118, and System Clock
Generator (SCG) 120. IPD 114 is connected from MDA Bus
110 to receive instructions from MEM 102.
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.
IPD llfl operates in conjunction with certain elements of
PU 106 to perform instruction prefetch operations, in
addition, IPD 114 performs certain initial instruction
decode operaticns, for example, with respect to
instruction and data type, to initially determine
certain subsequent operations to be performed by CU 104
and PU 106 with respect to execu~ion of received
instructionsO IPD 114 provides certain outputs to D Bus
112, for example~ information used by ~U lOÇ in
addressing and fetching data from MEM 102. IPD 114 also
provides instruction outputs to US 116 for use by US 116
in controlling operations of CS 101.
As will be described in detail in fo:Llowing
descriptions, US 116 includes memory and logic for
providing microinstruction cont_ol of CS 101. In
addition to certain outputs described below to D Bus
112, US 116 provides control outputs to other elements
of CS 101 and accepts control inputs from other elements
o~ CS 1 01 .
Finally, SCG 120 comprises a central clock
generator wr.ich prcvides clock ~utputs to all elements
of CS 101. For clarity of presentatîon, the clock

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outputs of SCG 120 are not shown individually, but will
be described in the following detailed descriptions as
appropriate.
Referring to PU 106, as described above PU 106
performs functions directly assoclated with execution of
userls programs. In this respect, Central ~rocessing
Unit ~rocessor (CPUP) 122 performs arithmetic and logic
functions and is connected between D Bus 112 and Y Bus
124. Y Bus 124 is an information transfer path within
PU 106. ~ibble Shifter (NIBS~ 126, also connected
between D Bus 112 and Y Bus 124~ operates in conjunction
with CPUP 122 and other elements of CS 101 to performt
for example, nibble shifting, memory address and data
alignment operations.
Scratch ~ad and Address Translation Un~t (SPAD) 128
is a multifunction element also connected between D Bus
11~ and Y Bus 124. SP~D 128 operates as a scratch pad
memory for PU 106 and also performs certai~ address
mapplng operations, as will be described in detail in
tne following descrlptions.
Memory ~ddress Unit (MAD) 130 is connected from
SPAD 128 and has ou~puts connected to MA~ Bus 108 MAD
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130 provides read and write adaresses to MEM 102. In
addition to other functions, MAD 130 operates in
conjunction with IPD 114 to perform instruction prefetch
operations.
Memory Data Bu~fer (MDBj 132 is connected between
MDA Bus 110 and D Bus 112 and Y Bus 124 and is a primary
path for data transfer between PU 106 and MEM 102.
Finally, Serial I/O (SIO) 134 and Data and Burst
Multiplexer Channel I/O (DBIO) 136 operate as principal
paths of information exchange between CS 101 and
external dev-ces, such ~s terminals and bulk memory
storage units. SIO 134 is used for communication of
serial information between CS101 and, for example, a
terminal. DBIO 136 provides, for example, three modes
of parallel information transfer, such as, Proyrammed
I/O, Data C~annel I/O, and a Burst Multiplexer C~lannel.
As indicated in Fig. 1, SIO 134 has a bi-directional
connection from D Bus 112 while DBIO has an input path
rrom D Bus 112 and an output path to Y Bus 124.
Having brie~ly described the overall structure and
functional elements of CS 101 with reference to Fig. 1,

2~
certain basic features of CS 101 will be descriked next
below.
B. Inst~ion Sets
The present implementation of CS 101 is as a 32 bit
computer system; that is, CS 101 generates and
manipulates 32 bit addresses and 32 bit data elements.
CS 101 is designed to be com~ati~le with t~o earlier
generations of data processing systems, that is, capable
of executing programs created for use on the earlier
data processing systems. One earlier family of data
processing systems is a 16 bit system, for example, the
Data General Corporation ECLIFSE~ computer systems. A
second earlier family of computer systems are 8 bit
systems, for example, Data General Corporation NOVA~
computer systems. As such, CS 101 is capable of
executing three different instruction sets, the NOVA
instruction set, the ECLIPSE instruction set, and a new
instruction set, that fo~ the Data General Corporation
LECLIPSE MV/8000~ systems. Each of these instruction
sets contain two classes of instructions: Arithmetic and
Losic Class (ALC) instructions, which define an
arithmetic or logic operation to be performed, and
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memory reference instructlons, which define operations
to be performed with data to be written into or read
from memory. ALC instructions in general include only
an operation code (opcode) field defining the operation
to be FerformedO In kmemory reference instructions, a
displacement field containing information relating to
the location, or address, of the data to be operated
upon is added to the opcode field. NOVA instructions
use 8 bit opcode fields while ECLIPSE and MV/8000
instructions use 16 bit opcode fields. NOVA and ECLIPSE
instructions use, respectively, 8 and 16 bit
displacement ields, while ~V/80Q0 instructions use 16
or 32 bit displacement fields. NOVA and ECLIPSE
instructions are referred to as "narrown instructions
ana MV/8003 instructions as "wide" instructions~
CS 101's instruction set allows CS 101 to
manipulate data elements having widths of 8, 16, or 32
bits. In addition, and as will ~e described further
below, CS 101 is capable of generating addresses .n two
ranges. The first range, using 32 bit addresses, allows
CS 101 to address a logical address space of 4.3 billion
bytes, or four gigabytes. The second, using 16 bit
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addresses, allows CS 101 to utilize a 64 kilabyte
addressing range.
During the following descriptions, a byte is
defined as 8 bits of info mation, a word is de~ined as
16 bits (2 bytes), and a double word is defined as 32
bits (2 words, or 4 bytes). In general, most operations
performed by CS 101, for example, generation of
addresses and manipulation of data, are performed in
double word 132 bit) elements.
C. ~
As described above, CS 101 may utilize 32 hit
addresses for byte addressing, or 31 bits in word
addressing,and thereby has a logical address space, that
is, a user visible address space, of our gigabytes.
This logical address space is partitioned Eor purposes
or memory management into eight 512 megabyte sections
called segments and referred to as segments O to 7.
Each logical address contains, in the three most
significant bits, information identifying a particular
segment in which a data item is locatedO The remaining
29 bits identify the location of the data item ih the
segment.
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The size of CS lOl's logical address space means
that not all logical address locations can be
represented in MEM 102 at the same time. For this
reason, CS lQlls logical address space is further
divided into pages. Each page is a two kilobyte block
of contiguous logical or physical addresses. A demand
paging system moves pages between MEM 102 and external
storage devices upon demand and tracks pages currently
in MEM 102. An address translation unit, described in
detail below, translates logical addresses into
corresponding physical addresses in MEM 102 for pages
represented in ME~ 102.
Logical a~dresses may use to reference two types of
information, data and instructions. To reference
instructions, PU 106 uses logical addresses generated by
a program counter (PC), located in PU 106, which is
incremented to read sequential instructions from memory.
As described above, bits l to 3 of the PC specify a
current segment from which instructions are being read,
while bits 4 to 31 specify an address within that
segment. It should be noted that logical addresses
senerated by the PC contain 31 bits cf address rather

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than 32 as CS 101 performs addressinng on the word
level. As will be described further below, CS 101
actually reads or writes only double words to and from
MEM 102, thus requiring 30 bits of address rather than
31 or 32 bits.
In contrast to instructions, which are addressed
directly, data is addressed in2irectly through
instructions. CS 101 utilizes infoxmaticn coded in the
reerencing instructions to construct the logical
addresses of the data so referenced. Among other
factors, data appears in different ~ypes and lengths and
the structure of the data effects the generation o
logicai addresses referencing data. The Data types may
include, for example~ fixed point numbers, floating
point numbers, decimal numbers, alphanumeric character
strings, and bit strings. Data lengths may,for example,
include bits, bytes (8 bits), words (16 bits), and
double words (32 bits~. In addition, the locations of
various data items may be specified as a displacement,
or offset, relative to various base addresses, as will
be described below.
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To reference an element of information in logical
memory, therefore, a referencing instruction will
provide information used by CS 101 to construct a
logical address of the referenced data item. Varîous
typical instruction formats used in CS 101 and
containing such information are illustrated in Pig. 2.
The instructlon illustrated on line A represents a
narrow instruction of 8 bits, while the instructions
illustrated on the remaining lines represent typical 1~ -
and 32 bit instructions, as previously described. As
shown in Fig. 2, each instruction includes an Operation,
(OP~ Code indicating an operation to be performed with
the referenced data, and an Accumulator ~AC) Field
designating a source or destination accumulator as
appropriate.
Each instruction includes a displacement field of
8, 15, 16, 31, or 32 bits, depending upon whether the
instruction is referencing a byte or a word o data~
Each instruction further includes an index bit field ~e)
identifying the source of the base address from which
the displacement (offset) specified in the displacement
field is taken to determine the logical address. The
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index bi's are capable of specifying four di~ferent
addressing modes, that is, four different sources for a
base address from which displacement is taken to locate
the data refer~ed to by the instruction displacement
field. A first mode lis Absolute mode and uses logical
address zero as base address. A second mode is Program
Count (PC) relative wherein the present PC address is
used as base address. The remaining two modes select as
base address the contents of either of two accumulator
registers residing in PU 106. Both the instructions
and the logical addresses resulting from the operation
described above contain a single bit field which
identifies whether the logical address is a final
logical address, or whether indirect addressing has been
specified. In indirect addressin~, a logical address
resulting from resolution of the instruction is treated
as a pointer to yet another address. The address
pointed to may, in turn, be a final logical address orr
as indicated by its indirect bit field, may be an
indirect pointer to yet another logical address~
Finallyr as previously described the losical
address space of CS lOl is larger than the physical
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address space of MEM 102. As such, two ~byte pages of
information storage containing instructions or data, or
both, are transferred between MEM 102 and external
storase devices as required. As a result, logical
addresses generated by CS 101 must therefore be
translated into equlvalent physical addresses in MEM 102
of pages residlng therein.
CS 101 performs logical to physical address
translation operations through the use of Page Tables
(PTs) and Segment Base Registers ~SBRs)~ A PT is a
table of entries containing information for translating
logical addresses to a physical addresses. Each entry
in a PT, referred to as a Page Table Entry (PTE),
contains the necessary information relevant to one page
or storage residing in MEM 102. In conjunction, there
exists a SBR for each se~ment of CS lOl's logical
address space. Each SBR contains the physical base
address of a PT containing entries for those pages of
the corresponding segment residing MEM 102. The
contents of each SBR indicates whether the corresponding
segment is c~rrently defined, tnat ls, usuable by CS
101, the nu~ber of PT levels necessary for logical

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address translation, as will be described further below,
and the address translation information.
Each PTE contains information indicating whether a
particular page is currently defined, that is,
accessible to CS 101, and whether the corresponding pase
is presently residing in MEM 102. Each PTE also
contains information regarding access rights to the
information stored in the corresponding page; that is,
whether a reference to the corresponding page may
perorm a read operation, a write operation, or execute
instructions contained therein. Each PTE also contains
physical page address information defining the physical
address or location in MEM 102 of the page corresponding
to a particular logical address. The physical address
contained in each PTE may reference either of two items,
depending upon whether a one level PT translation is to
be performed or a two level PT translation is to be
performed. If a one level translation is to be
perfcrmed, the PTE physical address contains the
physcial address of the page referenced by the
corresponding logical address. If a two level
translation is to be performed, the PTE address field
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contains the address of a second PT, which in turn
contains the final physical address of the page
referenced by the logical address. The utilization of
both one and two level PT translations allows CS lOl's
address space to be tailored to a particular user
program. For a smaller program, a one level mechanism
would be utilized, while for larger programs two level
translations would be performed.
Referring to Fig. 3, a diagramic representation of
a one level page table translation is shown.
Represented therein is a logical address to be
translated, one of CS lOl's SBRs, and a typical page
table containing a plurality of PTEs.
As indicated in Fig. 3, the logical address
includes an SBR Field identifying a particular one of CS
lOl's SBRs, in this case the SBR represented in Fig. 3,
a single level page table address field, and a page
offset field. CS 101 u~ilizes the SBR field of the
logical address to select a corresponding one of CS
iOl's eight SBRs. CS 101 reads from that SBR a physical
address field which identifies the start, or base
address, of a corresponding page table, that is, the
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page table represented in ~ig. 3. The single level page
table address field of the Logical address represents an
offset, from the start of the page table located by the
physical address fiela of the SBR, to the particular PTE
containing the physical address information
corresponding to the logical address to be translated.
Together, therefore, the physical address field of the
SBR identified by the SBR field of the logical address
and the single level page table field of the logical
address identify the physical address of a corresponding
PTE in the page table.
A PTE so identified includes, as indicated in Fig
3, a valid resident physical address field which
identifies the physical starting address of a particular
page residing in MEM 102. The page offset field of the
logical address specifies an offset, relative to the
start of the paae in MEM 102 identified by the valid
resident physical address field, of the PTE of the
particular word to be addressed. The physcial address
field of the PTE and the page offset ield of the
logical address thereby together comprise the physical
address in MEM 102 of the word referenced by the logical
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ad2ress represented in Fig. 3 and the logîcal to
physlcal address translation has been completed.
Referring to Fig. 4, a two level page table
translation is represented~ As indicated therein the
general procedure for 2 two level page table translation
is similar to that of a one level page table translation
except that an additional reference through a second
page table is performed. The logical address includes,
in addition to the single level page table address
field, a double level page table address field. The
dou~le level page table address field of the logical
address is utilized, together with the physical address
field of the SBR identified by the SBR field of the
losical address, to generate a physical address of a
particular PTE in a first page table. The valid
resident physical address field of the PTE of the first
page table is then combined with the single level page
table address field of the logical address to generate a
physical address of a second PTE in a second page table.
In this case, the valid resident physical address field
of the PTE o the first page able identiEies the
physiFal starting address of the second ~age table. The

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single level page table address fie]d of the logical
word address identifies an offset, relative to the start
o~ the second page table, of the second PTE. The
physical address field of the second PTE is then
combined with the page offset field of the logical
address to generate the final physical address referred
to by the logical address.
Finally, as described above, CS 101 transfers pages
between MEM 102 and extenal storase as necessary. This
operation is perfor~ed by CS lOl's memory management
system, of which CS lOl's address translation mechanism
is a part. CS lOl's address translation mechanism
performs, in particular, two functions with regard to CS
lOl's memory management mechanism. First, CS lOl's
address translation mechanism monitors which of the
pages resident in MEM 102 are referenced in read or
write operations, and which pages are most frequen.ly
referenced. When it is necessary to transfer a page out
of MEM 102 to external storage in order to transfer in
another pase, CS lOl's memory manasement system utilizes
this reference information to determine which pages have
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not been referenced or have been least frequently
referenced in determining which pages resident in MEM
102 can be replaced. Secondly, CS lOl's address
translation mechanism monitors which of the pages in MEM
102 have been referenced by write operations, that is,
which pages in MEM 102 have been modified and are no
longer identical to the copies o thos~ pages residing
in external storage. If a particular page has been
referenced in a write operation, it is necessary for CS
101 to copy that page back external storage when that
page is replaced by another page frcm external stora5e.
If that particular page has not, however, been
referenced in a write operation, CS 101 may simply
discard that page by writing a new page from external
sforage into the same address lo~ations in MEM 102~
thereby reducing the execution time required for a page
swap. CS lOl's address translation mechanism stores the
above described memory management information, in the
form of referenced/modified bits, in MC 118, which will
be described in greater detail below.
petailed System ~e~cription
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Having described the overall structure and
operation and certain basic features of CS 101 above, CS
101 will be described below in further detail. ~U 104
will be described first, followed by PU 10~.
Referring to Figs. 5, ~Æ, 6 and 6A, these figures
comprise a detailed block diagram of CU 104 and PU 106.
Figures S and 5A present CU 104 and Figures 6 and 6A
present PU 106~ Figures 5, SA, 6 and 6~ may be placed
side to side, in that order from left to right, to
comprise a complete detailed block diagram of CU 104 and
PU 106. For purposes of certain of the ollowing
discussions, it will be assumed that the reader has so
assembled Figures 5 and 6 into such a block diagra~.
A. ~U lO4 (Figs. 5 and 5A)
Re~erring to CU 104 in Figs. 5 and 5A, as
previously descri~ed the major elements of CU 104 are
Microsequencer (US) 116, Instruction Prefetch an~ Decode
(IPD3 114t Memory Control (MC) 118, and System Clock
Generator (SCG) 120. Th~se elements will be described
nex~ below in tha~
Referring to US 116, US 116 contains CS lOl's
microcode control logic, including microcode memories
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for storing microir.struction sequences for controlling
operation of CS 101, microcode sequencing control logic
for selecting and manipulating microinstruction
sequences, and condition logic for providing
microinstruction control of CS 101 in response to
certain conditions occurring therein and, for example,
branches in microinstruction sequencesO Microcode
control functions provided by US 116 also include
microcode state save and restore mechanisms for use in
executing microcode traps and interrupts. In addition
to the above functions directly concerned with execution
of users programs, US 116 also provides all console
control functions through the provision of microcode
therein directly responsive to commands entered through
a soft console~ that is, a user keyboard as opposed to
front panel switches.
As will be described further below, US 116
microcode resides in three microcode memories,
reflecting 'he microcode organization of CS 101. A
first microcode set~ referred to as kernel microcode,
resides permenently in US 116, as does horizontal
microcode. Vertical microcode is not permanently

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resident in US 116. That ls, vertical microcode is
stored in Random Access Memories (RAMs) comprising
writable control store and are loaded into CS 101 at
system startup. Briefly, kernel microcode resides
permenently in US 116, and in addition to providing !
console and other functions, is available at system
startup to perform system initialization, including
loading of vertical microcode. Typically, vertical
microcode will reside in external memory devices, such
as disk memories. At time systemls initialization,
vertical microcode is read from external memory and,
under control of kernel microcode, is transferred into
ME~ 102 a file to reside therein. Then, still under
control of kernel microcode, ver'ical microcode is read
from MEM 102 and loaded into vertical microcode memory
in US 116. At that time, the full functionality of CS
101 is available.
Th~ core of US 116's microsequencer is comprised of
Microsequence Control Logic ~USCL~ 500. USCL 500 is
comprised, for example, of d AMD AM2930 bit-slice
program control units connected in parallel. USCL 500
includes logic to implement Microprogram Count (UPC)
-28-

~ - - ~
lZ~4~2ZO
increment, a seventeen word deep last in first out
stack, a separate register as a source of
microinstruction addresses, an input port for jumping
out of sequential microprogram execution, and an output
port for providing microinstruction addresses to US
116's microcode memories. USCL 500 also includes an
nternal microprogrzm control unit for controlling
operation of USCL 500~
USCL 500's microinstruction address output is
provided from the output of Microinstruction Address
Multiplexer ~UAM) 502. UAM 502 is provided with a first
input frQm USCL 500's input, which is connected from
Microinstruction Input (UIN) Bus 504. A second input of
UAM 502 is connected from Microinstruction Address
Register (UAR) 506, whose input is connected from
Microinstruction Address Register Multiplexer (UARM)
508. UARM 508 is provided wi~h a first input connected
from VSCL 500's input, that is, from UIN Bus 504, and a
second input from output of UAM 502. UAM 502's third
input is connected from output of Microstack (USTACK)
510; as described above, US~ACK 510 is a seventeen word
deep last in first out stack. UST~CK 510 has a first
-29-

~Z~ Z2~
input connected from UIN Bus 50~ and a second input
connected USCL 500's microprogram counter, described
next below. UAM 5n2's fourth input is similarly
connected from the output of USCL 500's microprogram
counter.
USCL 500's microprogram counter includes
Micrcprogr~m Counter Register (UPCR) 51~ whose output is
connected to inputs of UAM 502 and USM 512. Input of
UPCR 514 is connected frcm output of Mi.croprogram Cour,t
Increment (UPCI) 516, which has an input connected from
Microprogram Count Multiplexer (UPCM) 518. Inputs of
UPCM 518 are connected from the output of UA~I 502 and
from the output of UPCR S14. UPCM 518 allows an initial
microcode starting address to be loaded from output of
UAM 502 and into UPCR 514 through UPCI 516. Thereafter,
Microprogram Count (UPC) may be sequentially incremented
by transferring current UPC from output of UPCR 514 and
through second input of UPCM 518 to UPCI 515; current
UPC may then be incremented by one by UPCI 516 and the
resulting next sequential U?C loaded into UPCR 514.
Other operations of USCL 500 in generating
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~Z~)4ZZO
microinstruction addresses for US 116's microcode
memories will be described further below.
Finally, USCL 500 includes internal microcode
control logic USCLC, which USCLC receives and decodes
control and instruction inputs from Microinstruction
Decode (UID) 522, which will be described below, to
control operation of USCL 500.
Referring to the outpu~ of USCI, 500, 16 bit
microcode address output of UAM 502 is connected to UY
Bus 524. UY Bus 524 in turn provides a single bit input
to Microprogram Counter Save Register (UPCSR3 526 and a .
sixteen bit input to UY Register (UYR) 528. UYR 528 in
turn provides a sixteen bit output to D Bus 108.
Sixteen bit UY Bus 524 is connected, through a
bufer, to sixteen bit Next Microprogram Counter (NX~PC)
Bus 530. NXUPC Bus 530 also receives, through a bufferr
a sixteen bit input from UIN Bus 504. NXUPC Bus 530
provides sixteen bit address inputs to Rernel Microcode
Memory (RUM) 532 and Vertical Microcode Memory (W M)
534. NXUPC Bus 530 also provides a fifteen bit input to
UPCSR 526.

12~4;~ ~
Referring to KUM 532 and WM S34, thirty--two bit
microinstruction outputs of kernel and vertical
microcode memories are provided to Microcode Output
(UCO) Bus 536. Thirty-two bit input of Microinstruction
Register (VIR) 538 is connected from UCO Bus 536, and
thirtv-two bit output of VIR 538 is connected to
Microinstruction Regis~er (UIR) Bus 540. As will be
described further below, kernel and vertical
microins~ructions are distributed to other portions of
CS 101 frorn UIR Bus 540.
Returning to UCO Bus 536, UCO Bus 536 provides
sixteen bit microinstruction inputs to Microirlstrllction
Save High Register (UI~SHI) 542 and to Microinstruction
Save Low Resister (UIRSLO) 544. Sixteen bit
microinstruction outputs of UIRSHI 542 and UIRSLO 544
are connected to D Bus 112. Certain bits of thirty-two
bit UCD Bus 546 are provided as data in~ut to VUM 534
through Bu~fer 535.
Returning to UUR Bus 540, UIR Bus 540 provides an
address inpu. 'co Horizontal Microcode Memory (HUM) 548.
As described above, and described in further detail
below, HUM 548 stores and provides horizontal extensions
--32--

to vertical microcode dealing with random control of ou
104, IPD 114, and D Bus 112~ among other functions. UIR
540 also provides cer~ain selected microinstruction bits
as inputs to UID 522. UID 522 in turn provides
instruction and control outputs to USCL 500 and to SCG
120.
UIR Bus 540 also provides control inputs to
Condition Multiplexer (CONM) 550. Dat~ inputs to CONM
550 are registered and unregistered conditions occurring
at various points throuahout CS 101. CONM 550's output
is provided as an input to UID 522 and as an input to
Condition Save Reqister (CONSR) 552. An output o~ UPCSR
526 is connected through a buffer to the output of CONM
550 so that UPCSR 526's output may be provided to the
same inputs of UID 522 and CONSR 552 as the output of
CONM 550~
Finally, certain of UIR Bus 540's thirty-two
microinstru tion bits are provided as one of five inputs
to Microinsturction Multiplexer (UIM) 554. UIR Bus .
540's input to UIM 554 is, as will be described further
below, provlaed to implement o~t of sequence jumps to
-33-

:aZCI 4~zo
new microinstruction addresses while executing
microinstruction sequences.
Referring to UUM 554, UIM 554's output is connected
to UIN Bus 504 and UIM 554's inputs are connected to
various sources used, as described below, to select
microinstruction sequences to be executed by US 116 and,
therefore, CS 101. As just described, one input of UIM
554 is connected from certain DitS of UIR }3US 54Q.
Another input of UIM 554 is connected from D Bus 112,
yet another input is connected from CONSR 552, and
another input connected from UPCSR 526. Finally, a last
input of UI21 554 is, as will be described in detail
below, connected from an outp~?t Il'D 114.
Referring finally to the upper portion of US 116,
therein are represented th~ee registers having outputs
connected to D Bus 112. These registers are provided to
store certain conditions and flags occurring in CS 101,
for su~sequent transfer on to D Bus 112. A first
register is Error Log Register (ERRLR~ 556, a second
register is Diagnostlc Register (DIA~R) 558J and a third
resister is Flag Register (FLAGR) 560.
--34--

12~ LZ20
Having described the overall structure of US 116
and certain features of the operation thereof, the
operation of US 116 will be described in further detail
next below.
b. U~_115_0p~in~
1. ~5~
As described above, USCL 500 provides functionality
for microprogram control and selection operations.
Input to USCL 500 is through UIM 554 and UIM Bus 504
while USCL 500's output is through NXUPC Bus 524.
Referring first to USCL 50~'s input through UIM
554 and UIN Bus 504, UIM 554 is provided with inputs
from five sources. A first input source for UIM 554 is
from D Bus 108 and provides, for example, instruction
from IPD 114. A second source is from UIR 8us 540 and
is utilized for jumping to nonsequential
microinstruction addresses in microcode memory4 A third
source is from IPD 114, described below, and is used for
certa~n inst~uction pre-execution operations and certain
preliminary operations regarding addressing from
instruction. A fourth source is a microcode conditional
-35-

~L20~Z2~
input comprised of selected portions of UIM 554's inputs
frcm UPCSR 526 and UIR Bus 540. Finally, the fifth
source is again a conditional input provided by the
output of ~PCS~ 526.
Referring to NXUPC Bus 530, either UY Bus 524,
which is USCL 500's direct output, or UIM Bus 504 may be
seiected to drive NXUPC Bus 530 and thereby directly
address ~UM 532 and W M 534.
For a microinstruction fetch, that is~ a
microinstruction read from microinstruction memory,
either RUM 532 or W M 534 is enabled, based upon the
state of a Rernel Flag ~RFLAG) stored in FLAGR 560 and
asserted during fetch operations. If ~FLAG is asserted,
fetch is from ~UM 532 and, i RFLAG is not asserted,
fetch is from W ~ 534. RFLAG may be set, or asserted,
for example, on system initialization or upon occurrence
of a microparity error, as described below. RFLAG may
be loaded into ~FLAG~ 560 as a bit output from VIR Bus
540 through operation of an NCU random control output
provided from HUM 548.
The 32-~it outputs of XUM 532 and W M 53~ are ORed
together on UCO Bus 536 and are loaded into UIR 538 at
-36-

~Z~2ZO
the er.d of each microinstruction read cycle to appear on
UIR Bus 54û. KUM 532 and WM 534 outputs may each be
selectively disabled for this ORing operation. All
microcode visible operations of CS 101 are controlled by
the 32 bit microinstruction appearing on UIR Bus 540
from ~IR 538.
In addition to beins loaded into UIR 538,
microinstruction outputs apprearing on UCO Bus 536 may
be loaded into and saved in UIPcS~I 542 and UIRSLO 544.
Outputs of UIRSHI 542 and UIRSLO 5~4 may then be
transferred onto D Bus 112 to allow reading of kernel
and vertical microcode memories~
As will be described further below, all
microinstructions appearing at UIR 538 output on VIR Bus
540 are checked for error by operation of Microparity
Checker (UPARC) 562, which is connected from UIR Bus
540.
As described above, each microinstruction outpu~
appearing on UIR Bus 540 from UIR 538 contains 32 bits
of microcode control information. Although there is
certain overlap of functions controlled by various
micrcinstruction fiel2s, certain portions of each

lZ~4Z2~
microinstruc~ion may be generally described as
controlling certain CS 101 functions. For example, in
general UIR Bus 540 bits 0 and 3 through 30 are provided
to PU 106 to control all PU 106 microcode visible
functions. UIR Bus 5~0 bits 7 through 13 may be used to
select a detected and registered condition occurring in
CS 101 to be tested during a current microinstruction
cycle. For this purpose, bits 7 through 13 from VIR Bus
540 are provided as control inputs to CONM 550, which in
turn selects conditions to be tested. Other microcode
controlled functions will be described further in the
following descriptions.
Having described the general operation of US 116,
certain features of US 116 operation will be described
in further detail next below.
2. Basic M;croinstruction Fetch
A microinstruction cycle is defined, for purposes
of the followin~ descriptions, as the time between
consecutive CS 101 clock cycles and is the period of
time during which single microinstruction functions are
executed. In qeneral, during each microinstruction
cycle the microinstruction is fetched from either KUM
-38~

z~
532 or W M 534 and a previously fetched microinstruction
stored in UIR 538 is executed.
The ollowing presents a typical sequence of steps
occurring in US 116 during consecutive microinstruction
cycles:
1) USCL 500 has placed on UY Bus 524 a
microinstruc~ion memory address specified by decode of
the certain bits (0~6) currently appearing on UIR Bus
540 and the output of CONM 550. Information appearing
on CONM 550's output from CONM 550 and UPCSR 526, may
include the contents of UPCSR 526, information
indicating the current top of USTAC 510, the contents of `
UAR 506, or on input appearing on UIN 8us 504.
2) The microcode address appearing on UY Bus
524 is incremented by UPCI 516 and the incremented
microprogram count loaded into UPCR 514. In all
microsequencer operations, except certain operations
described ~elow, the microcode address appearing on UY
Bus 524 is transferred onto NXUPC Bus 530 to address
either ~UM 532 or W M 534. Therefore, UPCSR 526 will
con~ain the address cf the curr~ently executing
microinstruction plus one.
-39-

l~;P'~42Z(i~
3) A new microinstruction addressed by the
address presently appearing on NXUPC 530 is loaded into
UIR 538.
4) The address presently appearing on NXU2C
530 is loaded into and saved in UPCS~ 526, so that UPCSR
526 always contains the address of the currently
executing microinstruction except on a TRA~ condition as
described below.
5) The output of CONM 550 from the microcycle
just ending is loaded into CONSR 552.
6) US 116's pointer to the top o~ the
microstack residing in USTACR 510 is changed if the
current US 116 operation specified in the cycle just
ending has affected US 116's microstac~.
7) The contents of U~R 526, whose operation
is described further in following descriptions, is
changed if the US 116 operations specified in the
microcycle just ending has affected UAR 506, or if other
operations, described below, occurred during the same
microcycle.
--~0--

~422~
Having described a typical microinstruction cycle
sequence, US 116 operation for TRAPS will be described
next below.
3. Tra~ Oper~tion
A TRAP condition occurs during execution of
microcode when an exceptional condition occurs and it is
desirable ~o stop the execution of a misroinstruction in
progress, service the exceptional condition, and then
res~me execution of microcode from the suspended
microinstruction. A TRAP process must save suficient
machine state so that the stopped microinstruct on may
be restarted. For those TRAPS that can be serviced
entirely by microcode, the two pieces of state
information that must be sa~ed in US ll~'s microstack
residing in USTACK 510 are,
(1) address of the stopped microinstruction;
and
~ 2) the output of CONM 5~0 from the stopped
microinstruction; that is, all conditions currently
present.
CONM 550 output must ~e saved because the inputs to
CONM 550 2re registered, or stored, state that may

~2~ 22~3
change- durin~ servicing of a TP~AP condition and the
microinstruction which was interrupted must recover the
correct conditions selected upon resuming.
A signal, TRAP is asserted by IPD 114 During
execution of zny microinstruction which is to be
suspendedJ This event causes the following to occur:
(1) Clock to all CS 101 registers under
explicit microcode control is stopped so that these
xegisters are not loaded with altered informa~ion during
servicing of the TRAP condition;
(2~ USCL 500's control input from UID 522 is
forced into a state to force USCL 500 to do a jump
operation to a TRAP handling microinstruction sequence;
and
(3) Control input to UIM 554 is forced to the
appropriate state to select UIM 554's input to be that
provided from IPD 114.
The address of a TRAP handling microlnstruction
sequence is provided to UIM 554's input from IPD 114 by
either CU 104 or PU 106, depending upon whether CU 104
or PU 106 is~the source of the ~RAP signal. If both CU
104 and PU 106 nave provided TRAP signals, then a
-~2-

~z~z~
priority mechanism will determine the TRAP handling
microinstruction sequence to be selected. A TRAP
handling address is the starting address of a TRAP
handling microinstruction sequence and is placed
directly upon NXUPC Bus 530 from UIN 504 through Buffer
505.
At the end of a microcycle in which a TRAP
condition occurs, the following occurs:
tl) UIR 538 is loaded with the
microinstruction beginning the TRAP handling
microinstruction sequence;
( 2) UPCSR 526 is nQ~ ioaded with the
microinstruction address appearing on NXUPC Bus 530;
UPCSR 526 will therefore contain the address of the
trapped, th~t is, interru~ted, microinstruction during
the first microinstruction of the TRAP handling
microinstruction sequence;
(3) The output of CONM 550 is loaded into
CONSR 552.
At conclusion of handling o the TRAP condition the
original sta~e or execution of the interrupted
microinstruction sequence is restored, using information
-43-

~Z~42~0
retained in UPCSR 526 and CONSR 552 and through the
state save/restore mechanism described next below.
4. Basic State Saye/Restore M~chznism
US 116's Basic State Save/Restore Mechanism is USCL
500's microstack residing in USTACK 510.
Durinq the first microinstruction cycle of a trap
handling microinstruction sequence, signal TRAP is not
asserted and any the information stored in UPSCR 526 may
change state. The first microinstruction cycle of a
~RAP handling microinstruction sequence must therefore
do a state save/restore operation to save current state
of US 116 and USTACR 510. During this operation, the
contents of CONSR 552, that is, previous conditional
states of execution, and the contents of U~SCR 526. that
is~ the address of interrupted microinstruction, a~e
transferred through UIM 554 and onto UIN Bus 504. This
state information is then transferred through USM 512
and onto the top of microstack residing in USTACK 510,
thereby saving the conditions and address cf the
interrupted microinstruction.
If a TRAP may be totally handled by a microcode, no
further microsequencer state save is required. Resuming
-44~

~2~Z2~
execution of the stopped microinstruction is
accomplished by leaving the saved condition state and
microinstruction address at the top of microstack
residing in USTACK 510 and performing a resume operation
which "pops" the top entry in USTACK 510. A "pop'l
operation fetches the stopped microinstruction while
reading the saved condition state inrormation r^rom top
of microstack and transferring this information from top
of microstack through ~AM 502 and into UPCSR 526. Saved
condition state is a single bit of information from
UPCSR 526 and which represents the saved output of CONM
550. After being.transferred into UPCSR 526, and during
re-execution of the interrupted microinstruction, the
sa~ed condition state information is transferred onto
CONM 550's output throuyh Buffer 527, thereby providing
saved condition state information to CONSR 552 and UID
S22. Saved address of the interrupted microinstruction
is concurrently transferred through UAM 502, UPCM 518
and UPCR 516 to UPCR 514. At this point execution of
the interrupted microinstruction may be resumed.
~ aving described US 116's basic state save/restore
mechanism, US 116's state save/restore mechanism for
-45-

42ZQ
conditions requiring assistance from macrocode, that is,
from instruction stored in MEM 102, ~ill be described
next below.
5. M2cxoinstruction L~s~L~ tate Save/s~
~h~
When a trap condition occurs requiring macrocode
assistance for handling, the trap handler must save all
microsequencer state and other PU 106 state in MEM 102
rather than in USTACK 510's microstack. State saved in
such conditions includes the curren~ contents of USTAC~
510's microstack including the address o the curren~ly -
executing microinstructions and current state condition
information pertaining to the interrupted
microinstruction, and the current contents of UAR 506
As in the case described above, current condition from
CONSR 552 and UPCSR 526 are first pushed onto USTACK
510. Full state save then saves the contents of USTAC~
510 and MAR 506 in MEM 102.
Current state conditions and current
microlnstruction address are read from CONSR 552 and
UPC5R 526, respectively, and through UIM 554 to UIN Buss
-46-

lZ~4~Z(~
S04. This information, together with inormation from
U~R 506 and the contents of USTACK 510's microstack, are
read through UAM 502 and UY Bus 524 into UYR 528. State
in~ormation so read from US 116 may then be transferred
through D Bus 112 to MEM 102, or to scratch pad memory
in PU 106/ described in a following description of PU
106.
State restore is accomplished by reading ~S 116's
saved state information from MEM 102, or scratch pad
memory in PU 106, to D Bus 112. This information is
then transferred into UIM 554's input from D Bus 112,
and onto UIN Bus 504. The saved contents of UAR 506 and
USTAC~ 510 may then be transferred through UARM 508 to
UAR 506 or through USM 512 to USTACR 510. Once
completed, the saved condition state and interrupted
microinstruction address will be the top entry in USTACX
510 and the interrupted microinstruc~ion may be resumed
as described in section 3 above.
6~ R~a~ing a~d Writing Microcode Memory .
As previously described, CS 101 implements vertical
microcode in a writable control store, that is, W M 534.
A meansr described next below, is provided to write
. -47-

4,~
vertical microcode from external memory to MEM 102 and
from MEM 102 to WM 534. This means also allows the
contents of WM 534 and and P~UM 532 read frorn VUM 534 or
~UM 532 to D Bus 112, for example, to verify microcode
residing in WM 534 or RUM 532 or to be read as a source
of literal data. This mechanism operates under
r.icrocode control and the functions described may be
performed under control of microcode provided from
either ~UM 532 or WM 534.
During a microcode wri~e to VUM 534, or a microcode
read from WM 534 or ~-M 532, USCL 500 is forced to
perform a conditional microinstruction jump to the
appropriate microinstruction sequence, by means of a
microcode input to UID 522 and a corresponding
instruction to USCLC 520. Microcode memory read and
write addresses are provided to NXUPC Bus 530 from UAR
506 through UAM 502 and UY Bus 524. UAR 506, in turn,
is provided with read and write addresses from D Bus 112
through UIM 554 and UIM Bus 504.
In microcode write oE~rations to WM 534,
microinstruction words are pro~rided on D Bus 112 and are
transferred ~hrough UCD Bus 546 to VUM 534's data input
.
--48~

~2~42Z~
through Buffer ~35. In mlcrocode read operations from
either RU~ 532 or W M 534, microinstruction words are
read from KUM 532 or W M 534 onto UCO Bus 536 and into
UIRSHI 542 and UIRSLO 544. Microinstruction words may
then be transferred from UIRS~I 542 and UIRSLO 544 to
UCD Bus 546 and to D Bus 112.
7. Microcode Pa~i~y Errors,
Each microinstruction provided by KUM 532 or by W
534 is a 32 bit word comprising 31 bits of microccde
information, plus 1 parity bit which is set to preserve
odd parity. Parity of each microinstruction appearing
in UIR 538 is checked by UPARC 562 after each fetch of a,.
microinstruction from KUM 532 or VULM 534~ If a parity
error occurs, UPARC 562 will initiate a microparity
error trap that prevents execution of the
microinstruction in error and transfers control to
Kernel microcode in KUM 532 for error handling.
8. ~
In the above desc;iptions, IPD 114 was described as
the source of instructions to be executed by means of
corresponding microinstruction'sequences provided by US
116. An instruction boundary is crossed when the
-49-

lZ()42ZO
microinstruction sequence corresponding to a first
instruction is ended, for example, by completing
execution of the sequence or because of a trap
condition, and execution of a second instruction is
iritiated. Microinstruction sequences provided by US
116 provide a mechanism for initiating the execution of
new instructions.
End of execution of a current instruction may be
indicated by the appear2nce in UIR 538 of a particular
microinstruction in the corresponding microinstruction
sequence. If such an end of execution microinstruction
occurs, UID 522 and USCLC 520 pro~ide an :instruction to
USCL 500 to jump to a state for receiving a next
instruction. At this time, UIN 554 is instructed to
accept as input to UIN Bus 504 UIM 554's input from IPD
114. IPD 114 will then provide, through UIM 554 and UIM
Bus 504, the starting address in microinstruction memory
of the next instruction to be executed.
I~ an interrupt is pending, or if the next
instruction has not yet been fetched, or if any one of
several other conditions occurs, a next instruction may
not appear or be avallable. IPD 114 will then provide
-50-

~z~gz~o
to UIM 554 the address in~ microinstruction memory of an
appropriate routine to handle the existing condition~
9~ SQf~, Console
As previously described, CU 101 incorporates a
"soft consolen. That is, operator console type commands
may be entered through a terminal rather than through
front panel switches. US 115 wili detect the initiation
of such a console command entry ~y means of a non
maskable interrupt initia~ed by an initial console
command. Upon such occurrenceJ an address will be
forced at UIM S541s input from IPD 114 which~ provided
to USCL 500 and thus to NXUPC Bus 530, is the initial
address in KUM S32 of console microcode sequences stored
therein.
As previously described, at system initiation US
116 microcode memory contains only kernel microcode. In
a present embodiment of the present invention, kernel
microcode includes at least a portion of the NOVA
instruction set microcode and is responsive to single
character commands provided from a terminal through SIO
120. Vertical microcode include microcode for the full
N5VA, ECLIPSE and MV/8000 instruction sets and is
--51--

~2~4220
responsive to multiple character ccmmands provided from
a terminal throush SIO 1~0. CS 101 thereby provides a
limited nraft" console, that is, from a terminal, at
system start-up, and full console functions after
vertical microcode has been loaded.
~ aving described the structure and operation of US
116, the structure and operation of IPD 114 will be
described r,ext below.
3. InstruçtiQn Prefetch and Deçode (IPD~ 114 (Fiqs. 5
5~ .
As indicated in Fig. 5 and 5A, and as previously
described, IPD 114 is connected be~ween memory data
(MDA) Bus 110 and D Bus 112 with an output to an input
of UIM 554 in US 116. IPD 114 opera~es as aan up to
four instruction deep instruction prefetch, and as an
initial instruction decoder. Some typical formats Of
instructions used in CS lOl have been previously
described with reference ~o Fig. 2.
a. StructuL.e o~ IP~ 114
Referring to IPD 114, 16 b~it Prefetch Register A
(PRA) 564 and 16 bit Prefetch P~egister B (PRB) 566 ha~e

~Z~ 22~
inputs connected from MD~ Bus 110i 1~ bit outputs of
PRA 564 and PRB 56~ are connected to 16 bit Prefet:ch
Register (PR) Bus 568.
PR Bus 568 is connected to 16 bit input of
Displacement High Latch (DISPHIL) 570 and to 16 bit
input of Displacement Low Latch (DISPLOL) 572. 16 bit
outputs of DISPHI~ 570 and DISPLOL 572 are connected to
first and second 16 bit inputs of IPD Ou~put Multiplexer
(IPrOM~ ~74.
Next Instruction Register (NIR) 574 has a 16 bit
input connected from PR Bus 568 and 16 bit output
connec~ed to 1~ bit input of Instruction Register (IR)
578. I~ 578 in turn has a 16 bit output connected to a
third input of IPDOM 574.
Finally, PR Bus 568 is connected to 16 bit input of
Single Level Instruction Cracker (SLIC) 580. 9 bit
output of SLIC 580 is connected to the input of 9 bit
Single Level Instruction Cracker Register (SLICR) 582,
and 9 bit output of SLICR 582 is connected to input of
Macroinstruction Decode Memory (MIDM) 584.
A firs~ output of MIDM 584 is connected to the
input of Decoded Instruction Register (D~R) 586. A

~Z~42ZO
first output of DIR 586 is connected to a fourth input
of IPDOM 574 and in part controls IPDOM 574 Second
outputs of DIR 586 are provided to other portions of CS
101, as will be described in following descriptions.
A second output of MIDM 584 is connected to a first
input of Microinstruction Address Multiple~er (UADRM)
588. ~ second input of UADRM 588 is connected from Trap
Addresses (TA) 590.
F}nally, IED 114's first output, from output of
IPDOM 574, is connected to D Bus 112 while IPD 114's
second output, from output of UADRM 588, is connected to
the previously described input of UIM 554 in US 116.
Having described the overall structure of IPD 114,
tne operation or IPD 114 will be described next below.
2. IP~ 114 Q~Lg$iQn
As has been previously described, a typical
instruction or CS 101 may contain 32 bits, including. 16
bits of instruction information (opcode ,ield) and 15 or
16 bits of address displacement information
(displacement rield). Certain instructions, however,
will have a total length of 16 bits or will have a
doublD word displacement field of 32 bits, for a total
-54-

12~4Z20
of 48 bits. As also previously descri~ed, and as will
be further described in fol:Lowing descriptions, all
writes to and reads from MEM 102 by CS 101 are of double
words, tha~ is, of two 16 bit words at a time. Upon
each read from MEM 102, therefore, PRA 564 and PRB 566
will receive a 32 bit double word from MDA Bus 110, with
one 16 bit word being received in PRA 564 and the other
16 bit word being received in PRB 556. A Prefetch
Register (PR) pointer generated by US 116 indicates, at
any time, which of PRA 564 or PRB 566 presently contains
or will contain a 16 bit instruction information of a
current instruction field or which contains or will
contain displacement field informa~ion.
Instruction displacement field information may be
transferred from either P~A 564 or PRB 566 PR Bus 56~
and toeither of DIS~IL 570 or ~ISPLOL 572. Diplacement
field information may then be transferred from DISP~IL
570 or DISPLOL 572 and through IPDOM 574 to D Bus 112
for use by PU 106 in addressing data referenced by an
instruction. Two displace fleld latches, that is,
DISPHIL 570 and DISPLOL 572, a.e provided to enable
displacement field information to be transferred to PU
,
-55-

2ZO
106 in a single cycle for 15, 16 or 32 bit displacement
~ields.
Instruction informaLion fields may be transferred
from either PRA 564 or PRB S66 to PR Bus 568 and NIR 576
and in turn .o IR 5780 From IR 578, instruction
information fields may be transferred, simultaneously
with the corresponding decoded output of SLIC 580 to
SLIC~ 582, through IPDOM 574 to D Bus 112 and thereby to
US 115 through UIM 554 to select corresponding
microinstruction sequences to be executed by CS 101.
N~R 576 and IR 578, together with PRA 564 and PRB 566,
provide an up to four instruction deep prefetch
mechanism, allowing CU 104 to fetch instructions in
advance of ~he instruction currently being executed.
Certain of CS lOl's instructions cannot ~e executed
immediately as received from MEM 102. For example,
instructions will frequently require additional
processing of the instructions addressing information
before the data referenced by the instruction can be-
fetchecl from M~M 102. Additionally, due to the variety
of instruction formats used by CS 101, CS 101 and US
116, in particular, mus~ perform certain preliminary
-56-

Z~ . ~
operations in order to properly interpret and respond to
instructions.
The instruction crack ng and decoding circuitry
provided by SLIC 580 and MIDM 584 and related logic
provides a mechanism for interpreting instructions.
First, SLIC 580 examines the 16 bit instruction
information field of each instruction and extracts
therefrom 9 bits, depending upon the instruction format,
defining the operation to be performed. A first output
is a 9 ~it predecode address which is provided as an
input to MIDM 584, described below. A second, 2 bit,
output defines the index made for the instructions being
decoded and other output may define the instruction
class. The information so extracted includes
information relating to data addressing, such as data
width, displacement type and instruction width.
MI~M 584 is a read-only-memor~ addressed by the 9
bit output of SLIC 580 and providing appropriate control
outputs. MIDM 584's first output to DIR 586 provides
information relating to data width~ displacement type
and data length. MIDM 584's second output, to UADRM 588
provides to US 116 the starting microaddress cf
-57-

~L2~ ;ZQ
microinstruction sequences to be executed~ as previously
described in the description of US 116.
UADRM 586's second input, from TA 590, provides
information to UIM 554, and thus to US 116, regarding
the starting microaddress of microinstruction sequences
to handle trap conditions occuring in CS 101, as
previously described.
~ aving descrihed the structure and operation of IPD
114, the structure and operation of MC 11~ will be
described next below.
3. Me~oIy Control (MICl 118 ~Fig. 5. 5A and 71
MC 118, as previously described, performs interface
functions between CU 101 and MEM 102. MC 118 is a "look
asiden interface device, that is, is connected in
parallel from ~AD Bus 108 and MDA Bus 110, rather than
being connected in series in these buses between CS 101
and MEM iO2. MC 118 operates, however, as if connected
in serles in MAD Bus 108 and MDA Bus 110 between CS 101
and MEM 102. MC 118 allows CS 101 and MEM 102 to share
the same address and data signals on ~AD Bus 108 and MDA
Bus 110 while, at the same time, allowing CS 101 and MEM
10~ to have different interface protocols.
-58-

~Z~42ZO
In addition to performing tran~lation between CS
lOl's memory bus protocol and ~M 102's ~emory bus protocol.
MC 118 provides MEM 102 refresh and "sni.fing"~ Sniffing,
as described in U5 Patent 4t380,812, iss~ed April 19, 1983,
is a mechanism and method for scanning ~ 102 locations
being refreshed, detectin~ errors therein, and correcting
such errors. In addition, MC 118 perfor~s memory error
logging. Finally, as previously descriked with reference
to CS lOl's addressing mechanis~s and in particular CS lOl's
demand paging mechanism, MC 101 monitors and logs, or
records, referenced and modified pages residing in ME~ 102.
a. Structure of MC 118
Referring to Fig. 5, MC 118 includes a Memory
Control Sequencer ~MCS) 592 r which provi~es timing and
control for all memory related operations, in particular
those of MC 118. MCS 592 has a clock in?ut from SCG 120,
a refresh timing input from Refresh Time- (REFT) 594,
and an error input from MC 118's ERCC losic, described
below. In addition to other control out?uts,
_ 59 _
cr/J~

~Z04Z~:O
MCS 592 provides outputs to Refresh Address Counter
Buffer (RACB) 596 and to Referenced/Modified Bits Logic
(REFMOD) 598.
In addition to a timing output to MCS 592, REFT 594
provides a timing output to Refresh Address Counter
(RAC) 501. RAC 501 in turn provides refresh address
outputs to RAC~ 5 96, and RACB 596 in turrl prcvides
refresh address outputs to ~D Bus 108 under control of
the previously described control input from MCS 592.
REFMOD 598, as previously described, monitors and
logs referenced and modified pages in MEM 102 as part of
CS 10i's demand paging system by storing information
bits pertaining to referenced and modified pases
residing in MEM lU2. In addition to a control 7 nput
from MCS 592, ~FMOD 5g~ includes an input from MAD Bus
108 and a bidirectional connection to MDA 3us 110.
Finally, MC 118 incorporates Error Checking and
Correction (ERCC) loaic which includes a first level
ERCCER (FLE) 503 and a second level ERCCER (SLE) 505.
FLE 503 and SL~ 305 are implemented with Advanced
Microdev~ces AM 2960s ccnnecte~ in a 32 bit
~configuration.
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12~4Z;~CI
MC 118's ERCC logic is provided with an internal
data bus, Check Data (CDATA) 507,which allows data to be
transferred from MDA Bus 110 to MC 118 ERCC logic,
manipulated, and transferred back onto MDA Bus 110.
Data is transferred from MDA BUS 110 to CDATA Bus 507
through ERCC Dzta.Inut Buffer (EDIB) 50~, and from
CDATA Bus 507 to MDA Bus 110 through ERCC Data Output
Buffer (EDOB~ 511.
FLE 503 and SLE 505 each have a 16 bit
bidirectional data input/output connection to CDATA Bus
507 for receiving data from and transferring data to
CDATA Bus 507. FLE 503 receives 7 bits of check bit
(ERCC) information, from ~DA Bus 110 through FLE 503's
check bit (CB) input connected from MDA Bus 110 and
provides a check bit output to check bit input o~ SLE
505's CB input. SLE 505 provides 7 check bits of ERCC
information to M~A Bus 110 through E~CC Check bit Output
Buffer ~ECBOB) 513. SLE 505 also provides error
outputs, as previously described, to MCS 59~ and to
ERRLR 556 in US 116.
--61--

~042;2~
Having described the structure and certain features
of the operation of MC 118, certain features of MC 118 will
be described further next below.
2. Operation of MC 118
The operation of MEM 102, and ~EM 102's interface
to MAD Bus 108 and MDA Bus 110 are described in Canadian
Patent Application No. 441,238, filed October 26, 1983. MEM
102 and MEM 102's interface to CS 101 will thereby no~ be
described further in detail herein. The following
description will pertain to CS 101 and CS 101's interfaces
to MAD Bus 108 and ~A B-~s 110 and CS 101's functionalitv
with respect to me~ory oper2t~0ns.
As described above, CS 101 anG ,~EM 102, will have
differing interface protocols but share the address and
data signals appearing on MAD Bus 108 and MDA Bus 110.
Translation between CS 101 and MEM 102 interface protocols
involves the control signals exchanged therebetween and
manipulation of check, or ERCC, bits appearing on MDA Bus
110. It should be noted that CS 101 may provide 30 bits
of address, since, as previously
cr/l~

1~42ZO
described, CS 101 performs reads from and writes to ME~I
102 double words only.
The least significant bit of CS lOl's addresses are
exchanged to be the least signlficant bit of the
addresses received by M~M 102. This implies that
consecutive double words written or read by CS 101 never
appear in consecutive locations in MEM 102, allowing
faster double word instruction fetches when ME~ 102
interleave operation is considered.
MC 118 operations may be divided into two broad
classes, read operations and write operations. ~ead and
write operations differ in that read operations may be
pipelined, whereas write operation may not, due to the
operation of the MEM 102. That is, address and control
signals for a next read operation may be sent to MEM 102
while reading and checking the data read from ME~ 102 in
a present read operation. Æll data control and add~ess
control functions for a present write operation must,
however, be fully completed before initiating a
subsequent wri.e operation.
MCS 592 may be regarded as performing two mutually
dependent operations with regard to memory read and

` ~Z~)4Z2,~
write operations, address control and data control~
Address control monitors operat on of MEM 102 through
control signals provided rom MEM 102r initia~es
addressing operations, determines acceptance of
addresses by MEM 102, and generates control si~nals to
initiate oFeration of MCS 5g2's data control logic on
information ~ransfers MCS ~92's address control also
monitors refresh operations, to allow sniffing
operations.
MCS 592's data control logic generates all data
control signals for MEM 102's CS lOl's inter~aces to MAD
Bus 108 and MDA llOo MCS 592's data control logic also
generates all control signals for MC 118 ERCC functions
and monltors the ERCC outputs of MC 118's ERCC logic.
As descri~ed above, MC 118 performs refresh
operations upon information stored in MEM 102. Refresh
is performed through ~cycle stealing" operations,
wherein MC 118's refresh control circuitry takes control
of MAD 108 and M~A Bus 110 at periodic intervals to
refresh successive portions of MEM 102's address space.
REFT 594 generates a refresh re`q-lest signal at periodic
ntervals and, at time of a refresh cycle, increments
. -64-

~Z~;)4ZZO
RAC 501 to generate successive refresh addresses. RAC
501 generates 21 bit addresses specifying double woras
to be read and checked for errors.
A sniff operation, that is examining information
stored in MEM 102 in storage locations currently being
refreshed for error checking and correction, be~ins by
requesting a refresh cycle. During refresh cycle, MC
118 takes control of M~D Bus 108 and MDA Bus 110 and
asserts a refresh address from RAC 501 through RACB 596
to ,~AD Bus 108. Informa~ion read from corresponding
locations in MEM 102 is checked for errors, while C~ 101
is allowed to continue making memory references. If a
correctible error is found, a refresh write back
operation is initiated. A refresh write back operation
is performed in the same manner as the original refresh
except that the information is corrected and written
~ack.
When R~C 501 generates an address greater than the
present address space of MEM 102, that address will
2ddress nonexistant memory. When this event occurs, MEM
10~ will not~generate a signal indicating that the
refresh address has been accepted. This event causes
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31 Z~9~220
RAC 501 to be reset to zero, allowing refresh to start
over at the beginning of MEM 102 address space. A
refresh and sniff in ~EM 102's address zero is performed
immediately upon this occurrence.
As described above~ ERCC and error logging is
accomplished through MC 118's ERCC logic, including FLE
503 and SLE ~05. Data inputs to FLE 503 and SLE 505
from MDA Bus 110, and data outputs from FLE 503 and SLE
505 to MDA Bus 110 are isolated from MDA Bus 110 through
the bidirec~ional buffer comprising EDIB 50~ and ~BOB
511. As descrlbed above, CDATA Bus 507 operates as the
data portion of ~DA Bus 110, but is isolated from MDA
Bus 110 by this bidirectional buffer. Check bits, that
is ERCC bits appearing on MDA Bus 110, are, however,
provided direc~ly to FLE 503's check bit (CB) input from
MDA Bus 110. Check bit output SC of MC 118's ERCC logic
is provided frcm check bit output SC of SLE.505 to MDA
Bus 110 through ECBOB 513. MCS 5~ provides individual
and separate controls of all data and check bit
transfers through EDIB 509, EDOB 511, FLE 503, SLE 505,
and ECBOB 513~

~ZC~42ZO
ERCC upon information read from MEM 102 on to MDA
Bus 110 is accomplished by reading data bits from MDA
Bus 110 and through EDIB 509 to CDATA Bus 507, and thus
into FLE 503 and SLE 505, while check bits are read
directly into FLE 503. It should be noted that FLE 503
receives the 16 least significant bits of data whlle SLE
505 recei~es the most significant 16 bits of data~ ~E
503 utili~es the check bit inputs from MDA Bus 110 and
the 16 least significant data bits received from CDATA
Bus 507 to generate an appropriate check bit output to
SLE 505 ~or ~hose check and information b1ts. SLE 505
in turn utilizes the most significant 16 bits of data
from CDATA 507 and the check bit input from FLE 503 to
senerate a final check bit output.
ERCC upon lnformation read from MEM 102 is
performed at the same time that the information is
passed on to the requestor, in most cases PU 106. That
is, ERCC is performed in parallel with the read
operation.
If an ERCC error is detected, a signal halting memory
operations is asserted and a correction cycle initiated.
During correction cycle, error syndrome bits indicatina
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~ZV'4ZZO
the error which has occurred are provided at output of
SLE 505 and are driven onto MDA Bus 110 through ECBO~
513. From MDA Bus 110, error syndrome bits are
transferred into FLE 503, which provides appropriate
outputs to the check bit input of SLE 505. FLE 503 and
SLE 505 then generate corrected data onto CDATA Bus 507.
The corrected data is then transferred through EDOB511
to MDA Bus 110 and thereby to the requester Because
comparitively few read operations will result in
correction cycles, the parallel operation of MC 118's
ERCC Logic, wherein information is passed on to the
requester while ERCC's performed, will result in faster
a~-erage read operations than will a series E~CC
operation.
MC 118's ERCC Logic also generates ERCC bits during
write operations to MEM 102. As previously described,
all write operations, as are all read opexations, are of
double words. Data appearing on MDA Bus 110 to be
written into ME~ 102 is accepted on to CDATA Bus 507
through EDI3 509. FLE 503 and SLE S05 accept this data
as inputs and generate corresponding check bits from the
output of SLF 505. These write check bits are then
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~Z~42~0
transferred onto the check bit porticn of MDA Bus 110
through ECBOB 513, and the data and corresponding check
bits written into MEM 102.
CS 101 may also perform partial write operations,
that is, writes of single words of single bytes.
As described above, all read and write operations
of CS 101 frcm and to MEM 102 are of double words, that
is, of two sixteen bit words at a time. As has also
~een previously described, CS 101 is also capa~le of
generating read and write addresses referencing single
words (16 bits) and single bytes (8 bits). The
operation of CS 101, and in particular MC 118, in
performing single wo d and byte read and write
operations will be described next below.
Referring .o Fig. 7, a block diaaram of certa~n
portions of CU 104 and PU 106 is shown, in particular CU
104's ERCC circuitry, including FLE 503 and SLE 505 and
CDATA Bus 507, and PU 106's MDS 132, in particular MDR
602. In Fi~. 7, FLE 503, SLE 505, EDIB 509, EDOB 511,
MDR 602, and MDRB 603 have been redrawn to illustrate
the operatio~ of these elements in yet greater detail.
In particular, MDR 602 and MDRB 603 of MDS 132 are
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~2~)4;2~
indicated as operating, respectively, as four
independently controllable 8 bit registers and buffers,
C, D, E, and F, rather than as a single 32 bit register
and buffer. In FLE 503 and SLE 505, input latches I
have been represented as each comprisinq two
independently controllable 8 bit latches Aand B, while
output latches O have been similarly represented âS e2ch
comprising two independently controllable 8 bit latches,
A and B. Similarly, EDIB 509 is represented as
comprising our independently controllable 8 bit input
buf:fers, while EDIB 511 is represented as comprising
four independently controlla~le 8 bit output buffers.
For clarity of presentation of the following
description, CDATA Bus 507 is shown as divided in two
parts, one part corresponding to FLE 503 while the
second part is associated with SLE 505. This division
is made ror illustrative purposes only and the two
halves of CDATA Bus 507 shown in Fig. 7 ar~ in fact a
single bus. ~IDA Bus 110 is represented as Deing
comprised of a 32 bit data bus and â 7 bit check bit ~us
for ERCC bits.
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~z~ zo
In as much as CS 101 performs only double word
reads from and writes to MEM 102, a write of a single
word or byte to MEM 102 is performed as a read, modify
and write of a double word. T.he double word containing
the address location of the single ~ord or byte to be
written into MEM 102 is read from MEM 102. The double
word read from MEM 102 is effectively modified by ha~ing
the single word or byte written into the appropriate
location in the double word, and the double word lS then
written back into MEM 102. The following will describe
the operation of CS 101 in writing a single byte (8
bits) into MEM 102. A single word write, that is, of 16
bits, or two bytes, is performed in the ~ame manner
except that t~o bytes rather than one are ~ritten into
the appropriate location in the double word.
Referring to Fig. 7, at start of a single byte
write operation a double word is read from MEM 102 on
MDA Bus 110. Thirty-two data bits appear upon the data
portions of MDA Bus 110, while seven check bits appear
on the check bit portion thereof. The four 8 bit bytes
comprising the 32 bit double word are transferred
through the corresponding portions of EDIB 509 to CDATA

~LZ042Z~
Bus 507 and into the corresponding A and B portions of
FLE 503's and SLE 505's input (I) latches. The check
bits are transferred directly into FLE 503's check bit
(CB) input. The 32 bit word received f rom MEM 102 and
to FLE 5û3's and SLE 505ls I latches are checked for
errors, corrected if necessary, and transferred into FLE
503's and SLE 505's ~our 8 bit output (O) latches A and
B.
At the same time, the byte to be written into MEM
102 is loaded into one of MDR 602's four single byte (8
bit) latches, C, D, E, and F, from D Bus 112. The byte
to be written into ME~ 102 will appear in the one of MDR
602's latches corresponding to tbe location that the
byte is to be written into in the double word initially
read .rom MEM 102. The byte to be written is then
transferred from the corresponding byte register of MRD
602 and through the corresponding portion of MDRB 603
to the data portion of MDA ~us 110 and thererrom into
the cor responding single byte input ].atch of FLE 503 or
SI.E 505. For ex~ample, a byte appearing in MDR 602 byte
register E GOUl d correspondingl~- be transferred into FL~

l'Z~4ZZO
503's I latch A, while a byte appearing in MDR 602's
latch D would appear in SL.E S05's I latch B.
At this time, three of FLE 503's and SLE 505's
input latches contain corresponding bytes from the
double word originally read frcm MEM 102 while one of
FL~ 503's or SLE 505ls input lztches contains the byte
to be written into ME~I 102. FhE 503's and SLE 505's
input latches thereby contain the modified double word
to be written back into MEM 102, that is, the double
word containing the byte to be written into MEM 102.
FLE 503 and SLE 505 will then generate the new seven
check bits for the modified double word. The check bits-
in modified double word are then transferred to FLE
503's and SLE 505's output latches and on to CDATA Bus
507 and ~DA ~us 110 to be written into MEM 102, thereby
completing the write of a single byte into MEM 10~. As
described above, a write of a single word, that is of
two bytes at a time, is performed in the same mannex as
a single byte write operation except that two bytes are
received frcm MDR 602 and used to generate the modified
double word.
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422~
Finally, as previously described, .~C 118's REF~OD
598 operates as part of CS 101's demand paging system by
monitoring and storing information relating to
referenced and modified pages residing in MEM 102.
REFMOD 59~ may store information pertaining to up to,
for example, 8 megabytes of information storage in MEM
102.
REFMO~ 598 stores two different types of
information pertaining to each page in MEM 102. First,
RSFMOD 598 stores, for each page residing in MEM 10~, a
bit indicating whether the page has been referenced by
CS 101, for example, in executing a user's program.
Secondly, REFMOD 598 stores, again for each pase in ME~
102, a bit indicating whether CS 101 has modified, tha~
is, performed a write operation to, that page in MEM
102. Referenced information bits are updated upon
occurrence of each read or write operation to ME~ 102,
while modified bit information is updated during each
write operation. Updating o referenced and modified
inormation in REFMOD 598 is performed under control of
CU 104 random control outputs from HUM 548 and US 116 as
preYiously described.
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lZ~ Z~
Having described the structure and operation of ~U
104, the structure and operation of PU 106 will be
corresponding described next below.
B. ~QÇ~ ~ UNIT ~PU) 15h_~B~C~URE AND
9PE~TIpN (Eigs. S and 6~
Referring to Fig. 6, a detailed block diagram of PU
106 is shown. æs previously described, ~U 106 opera~es
under microinstruction control of CU 104 to e:cecute
user's programs. That is, PU 106 performs all data
manipulation ~nd calculation operations, addressing
operations, and infor~ation transfers be.ween CS 101 and
external storage devices.
~S~9~0S
As previously described and as shown in Fig. 6, PU
106 includes CPU Processor (C~t7P) 122, Nibble Shifter
(NIBS) 126, Stratch Pad and Address Translation Unit
(SPAD) 128, Me~ory Addressing (MAD) 130, Memory Data
Store (MDS) 132, Serial Input/Output (SI0) 134, and
Data/3MC Input/Output (DBIO) 136.
Referring first to CPU~ 122, CPUP is a 32 bit
processor comprlsed of 8 four ~it Advanced Micro D~vices
(AMD) 2901C microprocesscrs connected in parallel.

~z~ o
CPUP 122 performs all CS 101 arithmetic operations under
microcode control of CU 104. CPUP 122 includes a random
access memory (RAM), a shift register/buffer, a
register file, an arithmetic and logi~ unit (~LU), and
other registers, shift registers, and multiplexers as
needed to perform general purpose data manipulation
operations/ including arithmetic operations. CPUP 122
further includes internal microcode control, which
receives instruction inputs from US 116. CPUP 122
receives two inputs, AR~G and BREG from US 115 microcode
control output which selects, for certain operations,
source and destination registers in CPUP 122's register
file. As indicated in Fig. 6, CPUP 122 has a 32 bit
data input connected from D Bus 112 and a 32 bit output
connected to Y Bus 124. The circuitry comprising CVUP
122 are commercially available components well known to
those of ordinary skill in the ar~, and will not be
described further except as required for a more thorough
unders~anding of CS 101 during the following detailed
descriptions of other portions of PU 106.
~ aving aescribed PU 106's~CPUP 122, the
transmission paths by which information, primarily data
~76-

~2~1~ZZO
and aadresses, are transferred between MEM 102 and ~U
106, and in particular CPUP 122, wi~l be described next
below. These transmission paths include M~D Bus 108~ by
which ~ead and write addresses are provided to MEM 102
by PU 106, and MDA Bus 110, by which instructions and
data are communicated between PU 106 and MEM 102.
Paths internal to PU 106 include D Bus 112 and Y
Bus 124. As indicated in Fig. 6, MDS 132 is connected
between D Bus 112 and MDA Bus 110 arld between MDA Bus
110 and Y bus 124. MDS 132 includes Memory Data
Register (MDR) 602, having a 32 bit input connected from
D 8us 112 and a 32 output connected through buffer
driver MDRB 602 to MDA Bus 110. .~BS 132 also includes
Memory Data Latch (MDL~ 604, which ~.as 32 bit input
connected from MDA Bus 110 and a 32 bit. output connected
to Y Bus 124. Finally, PU 106's internal data path
further includes NIBS 126, having a 32 bit input
connected from Y Bus 124 and a 32 bit output connected
to D Bus 112. MRD 130, comprising PU 106's address
output to MAD Bus 103, will be discussed separately
rurther below, in conjunction with the discussion of
SPAD 128.

lZCi~
Considering first data transfers from MEM 102 to PU
106, data read from MEM 102 appears on MDA Bus 110 and
may be received and stored in MDL 604. That data may be
then transferred from MDL 604 to Y Bus 124, and may then
be trznsferred from Y 3us 124 to NIBS 126.
NIBS 126 is a nibble shifter and is capable of
either passing data straight through or performing right
or left shifts of data on a nibble by nibble basis.
NIBS 126 is used, for example, to shift data within
words received from MEM 102 into difrering formats for
subsequent operations by CPUP 122. NIBS 126 may~ for
example, be further used to reorganize data resulting
from operations CP~P 122 into formats select:ed for
storing such data in MEM 102.
As previously descr~bed, NIBS 1?.6's output is
connected to D Bus 112, so that data appearing on Y Bus
124 may be transferred onto D Bus 112, either directly
as a straight through-put or after being operated upon
by ~IBS 126.
As previously described .he output of CPUP 122 is
connected to Y Bus 1~ d, SO that data generated as a
result of CPUP 122 operations may be transferred,
-78-

2Z~
through NIBS 126, to D Bus 112~ Again, data transferred
through NIBS 126 from output of CPUP 122 may be passed
directly through NIBS 126 or may be operated upon by
NIBS 126. For example, NIBS 126 may perform alisnment
operations upon data outputs of CPUP 122 in preparation
for subsequent write operation to ME~ lC2.
Data ap?earing on D Bus 112 may then be transferred
into MDR 602 and subse~uently transferred through .~DRB
6~3 to MDA Bus 110 and thus written into MEM 102.
Alternately, data appearing on D Bus 112 may be
transferred into CPUP 122's data input. Data appearing
on D Bus 112 may also be transferred through Buffer 606
to DBIO 136 for subsequent transfer to external storage
devices.
Before describing SPAD 128 and MAD 130, two further
features associated with operation of CPUP 122 will be
described next. The first is the use of CPUP 122 to
perform increment by two operations and the second is
the multiple uses of Temporary ~egister (TREG) 608,
which is bi-directionally connected from D Bus 112.
A common operation, for example, in manipulating
addresses and other arithmetic operations, is to
79-

~2~2Z~
increment a given number by two. The A~D 2901Cs
utilized in CPUP 122 are~ however, not directly capable
o~ performing an increment by two operation. Minus 2
Source (MINUS2) 610 having an output to ~ Bus 112, ~nd a
microinstruction sequence from US 116, allow CPUP 122 to
perform increment by two operations. MINUS2 610 is a
sc~rce for placing on D Bus 112 a 32 bit number having a
n~meric value of minus 2. CPUP 122 contains the number
to be incremented by 2 in its register file. It accepts
~he minus 2 operand provi~ed by MI~US2 610, and
compliments it (giving a +l) and per orms an add
operation with the number to be incremented to give a
number equal to the operand to be incremented plus 1~
At the same time, a plus 1 is forced lnto CPU 122's ~U
carry input to provide a further plus 1 increment. The
output of CPUP 122's ALU will there~y be the ¢riginal
operand incremented by 2O MINUS2 610 thereby allows
CPUP 122 to perform a commonly desired op~ration not
originally provided for by the ~MD 2901ccircuits
employed therein.
Referring now to TREG 608,` T~EG 608 is a 32 bit
shift register which may be used for temporary storage
~80-

lZq:~ZZ~
of data appearing on D Bus 112, from which TR~G 608 is
connected by a bi-directional 32 bit bus. TREG 608 is
further utilized to generate 32 bit long control word
sequences for controlling other operations of CS 101.
Under microcode control, a 32 bit pattern of ones and
zeros is loaded into TREG ~08. That 32 bit pattern is
then shifted rlght or left as necessary to ~enerate bit
sequences which are used, for example, to perfor~ system
resets, to perform timed input/output operations, and to
control buffers for programmed input and output
operations. TR~G 608 thereby provides an extended means.
for controlling certain operations of CS 101 ~hile
utilizing already existing circuitry normally intended
~or temporary data storage functions~
Referring now to SPAD 128 and MAD 130, SPAD 128,
having inputs connected from Y 3us 124, performs address
translation and mapping functions as previously
described. SPAD 128, for example, accepts logical
addresses from Y Bus 124 and provides corresponding
physical addresses to MAD 130. MAD 130 transfers
addresses from SPAD 128 to MAD Bus 108. In addition,
MAD 130 operates in conjunction with IPD 114 as a
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prefetch mechanism by generating and providing prefetch
read addresses to MEM 102 through MAD Bus 108.
Referring f irst to SPAD 128, ~he core of SPAD 128
is SPAD Memory tspADM) 129. SPADM 129 is a random
access memory used in part by PU 106 and CS 101 as a
scratch pad memoryi SPADM 129 is further utilized to
store address mapping information, and thus is a part o~
CS 101's addressing mechanism. For exâmple, SPADM 129
may be used to store address translation maps for CS
lOl's data channel, burst multiplexer channel,
programmed I/O, through DBIO 13~. SPADM 129 is also
used to store addressing maps for logical to physical
address translations~ In addition, SPADM 129 contains
cs lOl's Se~ment Base Registers (SBRs), previously
described, and a portion of SPADM 129 is utilized as
accumulators for floating point operations.
As indicated in Fig. 6, SP.~D 128 includes an
internal addressing bus, referred to as Logical Address
Register (LAR) Bus 132, and a data bus, referred to as
SPAD 3us 134. L~R ~us 132 is connected from Y Bus 124
through Log;cal Address Register tLARR) 136 and Logical
Address Register Multiplexer (LARM) 138~ LARR 136 has a
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32 bit output to LAR Bus 132 and has inputs from ~ Bus
124 and from LARM 138.
LARR 136 and LA~M 138 are utilized to provide
logical and physical addresses to SPAD 128 and MAD 130.
The general format of CS lOlls logical addresses has
been previously described. In those descriptions,
certain bits were indicated as representing p~ysical or
logical page numbers and page offsets, while other bits
comprise various control ields. As shown in Fi~. 6~
LARR 136 has a first 16 bit input connected from Y Bus
124 for receiving 16 bit physical and logical page
offset fields from Y Bus 124. LARR 136's second input
is connected from LARM 138 and comprises those 16 bits
of address used for logical and physical page number
fields " various control fields, and also for short
addresses. LARM 138 includes a first 16 bit input
connected from Y Bus 124 to receive, for example, a
corresponding 16 bits of page number field from Y Bus
124 when LARR 136's first input is receiving a page
offset field. LARM 138 further includes 2 inputs to
enable varyi~g formats to be selected for bits 0 to 16
of addresses to be provided to SPAD 128. For example,
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three bits (CRE) of each of these two inputs represents
which of CS lOl's 8 memory space se~ments CS 101 is to
be addressed by a particular address, while other bits
of these two inputs are taken from Y Bus 124.
As indicated in Fig. 6, LARR 136's 32 bit output is
connected to L~ Bus 13~, which in _ur~ is a source of
addresses to SPADM 129, to CS lOl's address translation
unit control, TG 146 and ATC 148, and to MAD 130.
A first output of LAR Bus 132 is direc~ly to MAD
130, and in particular to an input cf MAD Multiplexer
(MADM) 140. As will be described further below, MADM
1~0 is a source of physical address offset fields for
~D 130's output. LAR Bus 132's output directly to MADM
140 is used, for example, to provide physical page
of.sets to MADM 140 when PU 106 is directly phys-cally
addressing M~M 102. This path is also used, in further
example, to provide single and double level page table
offset fields when per~orming single and double level
page table translations of logical to physical
addresses, 2s previously described.
LAR Bus 132 is further provided with a direct path
through Buffer 142 to SPAD Bus 134. As will be
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12(;~4220
described further below, this path may be used to
provide physical page number fields directly to Memory
Address Latch tMAL) 150 in MAD 130 from LARR 136 in
conjunction with the corresponding offset field of a
physical address as described above. Finally, will be
described f urther DelOw~ S~ADM 129 is ~rovi2ed with a
bi-directional data input/output connection to SPAD Bus
134. The path comprising I.~ Bus 132, Buffer 142, and
SPAD Bus 134 may also be used, for example, to write
information, such as address maps, into SPADM 129 from
LARR 136.
LAR Bus 132 also provides an input into SPAD
Multiplexer (SPAM) 144, which has an address output
connected to SPADM 129's address input (~D)~ SPAM 144
is the means by which SPADM 129 is addressed foz read
and write operations~ The path comprising L~R Bus 132
and f irst input of SPAM 144 is used, in part, to address
SPAljM 129.
SPAM 144 is pLovided with three further inputs.
Two of these inputs, ACD and ACS, are provided from IR
578 in IPD 114, respectively, and identify destination
and source accumulators . ACO and AC5 may be used, f or
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12(~ z~
example, in addzessir.g SPADM 129's address locations
assigned, for example, as floating point accumulators.
SPAM 144's fourth input is connected from UIR Bus 540 in
US 116 is used to microinstruction control in addressing
SPADM~
The above combination of address sources for SP~M
144 allows, for example, ACS or ACD inputs to ~pecify a
base address in SPADM 129 and VIR microinstruction
inputs to specify an offset from such a base address to
a floating point source or destination accumulator.
This addressing mode also allows tne ACS field of IR 578
to be determlned without performing a mas~ and shift
operation to read ACS field from IR 578, the information
is instead determined from a read from SPADM 129, with
the results of such an ACS read indicating the contents
of IR 578's ACS field. Microinstruction and I~ 578
addressing of SP~DM 129 also allows constants to be
stored in and recovered from SPADM 129 as required.
Finally, LAR Bus 132 provides an output to SPAD
128's address translation control unit, comprising Tag
Compare (TC) 146 and Address Translation Control (ATC)
148. TC 146 receives certain portions of addresses
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appearing on LAR Bus 132 and SPAD Bus 134 and, utilizing
this information, generates control inputs to ATC 148.
ATC 148 has a bi-directional connection to Y Bus 124 to
receive address translation control information
therefxom and to provide such control information onto Y
Bus 124.
Referring to SPAD Bus 134, as previously described
SPAD BUS 134 has a direct 32 bit connection from LAR Bus
132 '~hrough Buffer 142 and has a bi-directional 32 bit
input/output to SPAD~ 129. Certain address fields, that
is, physical page number fields, appearing on SPAD Bus
134 from SPADM 129, or from Buffer 142, may be
transferred into Memory Address Latch (MAL) 150 in ~AD
13~.
Finally, SPAD Bus 134 has a 82 bit bi-directional
input/output connection to D Bus 112 th~ough SPAD Buffer
(SPADB) 152. SPADB 152 allows operations to be
performed on SPAD Bus 134, for example writing a page
number into MAL 150, while leaving D Bus 112 free for
other, concurrent operations. SPADB 152 allows
information to be transferred between D Bus 112 and
SPADM 129 or TC 146. For example~ address information
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may read from SPADM 129 to D 3us 112, or may be read
from D Bus 112 and written into SPADM 129 for example,
when loading address maps into SPADM 129. SPADB 152 is
particularly used, for example, ln floating point
operations ard for any operation wherein SP~DM 129 is
being used as PU 106's scratchpad memory, or general
registers.
~ aving described SPAD 128, MAD 130 will be
described next below.
3. MemoFy_Addressin (MAD) 130
As previously described, MAD 130 is connected from
outputs of SPAD 128 and in turn has an output connected
to MAD Bus 108. MAD 130 receives physical address~s
from SP~D 128 and transfers those physical addresses to
MAD Bus 108 to address MEM 102 ~or read and write
operations. MAD 130 also operates in conjunction with
IPD 114 as an instruction prefetch mechanism by
providing instruction prefetch physical addresses to MEM
102.
As also prev-iously described, physical addresses
for reading from or writing to MEM 102 are comprised of
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l~C~22(~
a physical page number field and a physical page ofrset
field. As described above, physical page number fields
are provided by SPAD 128 to MAL 150 through SPAD Bus
134, either from SPADM 129 or from BARR 136 throu~h
Buffer 142. Physical page offset fields are provided to
MADM 140 by LARR 136 through the bus connection directly
~rom LA~ Bus 132 to an input of ~DM 140.
Outputs of MAL 150 and MADM 140 are connected to
Memory Addressing Internal (MADI) Bus 154, which is
connected in turn through Memory Address Buffer (MADB)
156 to MAD Bus 108. `Physical addresses received by MAD
130 ~rom SPAD 128 may thereby be assembled from MAL 150
and MADM 140 onto MADI Bus 154 and tr2nsferred onto MAD
Bus 108 to address MEM 102.
That portion of MAD 130 which operates as part of
CS 101's prefetch mechanism includes Prefetch Page
Number Register (PPNR) 158, Prefetch Page ~ffset Counter
(PPOC) 160, and Write Compare (WCOMP) 162. PPNR 158 has
an input connected from and an output connected to MADI
Bus 154. PPOC 163 has an input connected from MADI Bus
154 and an output connected from PPNR 158 and MADI Bus
154 and provides outputs to IPD 114.
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~L2(~2Z(;I
An initial physical address, includiny page number
and page offset, from which instruction prefetch is to
begin is generated by SPAD 128 and is transferred onto
L~ADI Bus 154. Page num~er and page offset are then
transferred ~rom MADI Bus 154 into, respectively, PPNR
158 and PPOC 16C. 'lhereafter, pase cfEset in PPOC 16
is successively incremented and combined, through MAD~
14Q, with pase number read from PPNR 158 to provide
successive instruction prefetch read addresses on MADI
Bus 154 and thus onto MAD Bus 108 to fetch successive
double words containing instructions from MEM 102.
Sequential instructions are fetched frcm consecutive
15~i5~ pages, thus barring address j~mps. Consecutive
logical pages need not be cor.secutive ~hvsical pages.
PPNR 158 is imp1emented as a register, rather i_han a
counter, to prevent prefetch from crossing physical page
boundaries. When PPOC 160 over.lows, pre~etch is
stopped until PPNR 158 is loaded with a new physical
page number, corresponding to the next sequential
logical page of execution.
~ COMP 162 checks each physical address to MEM 10
for write operations and compares such addresses to
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4:~20
addresses of instructions prefetched by MAD 130 and IPD
114. If a write operation is executed to a physical
address within the same pase as a prefetched
instruction, WCOMP 162 provides an output indicating
that the contents of IPD 114 are no longer valid. CS
101 will respon~ by reinitlatins prefetch to obtain n2w
valid instructions from MEM 102.
~ escription of a preferred embo2iment of the
present invention is hereby ccncluded. The inver.tion
may be embodied in yet other s~ecific forms without
departing fro~ the spirit or essentlal characteristics
thereof. Thus, the present embodiments are to be
considered in all respects as illustrative and not
restric ive, tne scope of the invention being indicated
by the appended claims rather than by the foresoing
description, and all changes which come within the
meaning and range of equivalency of the claims are
therefore intended to be embraced therein.
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