Note: Descriptions are shown in the official language in which they were submitted.
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DETAILED DESCRIPTION OF THE INVENTION
Technical Field
This invention relates to a keyboard interface, and more
particularly to a serial keyboard interface system to
prevent the erroneous transmission of keyboard data due to
noise .
A cross reference is made to co-pending Canadian application
439,560 of the same Applicant in which is disclosed an
embodiment of the invention claimed in the subject patent
application.
Background Art
There has been proposed keyboard system in which a
keyboard and a data processing unit a~re connected through a
data line and a clock line so as to t;ransmit keyboard out
codes bit-serially through the data line and to transmit a
keyboard out clock signal through the clock line. The
keyboard out codes are transmitted in a 9-bit frame
consisting of a leading start bit and the following 8-bit
serial scan code identifying a key position. On the data
processing unit side, there is provided a 9-stage
serial-parallel shift register connected to the data line
and clock line. The bits of the frame received are loaded
successively from lowest ordered or least significant stage
of the serial-parallel shift register under the control of
the clock signal. The completion of the receipt of the
9 bit frame is indicated when the start bit appears at the
highest ordered or most significant stage.
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The start bit from the highest ordered stage causes an
interruption to request the read-in of the scan code
in the shift register into the data processirlg unit,
and also signals to the keyboard that the keyboard
data cannot be sent until the read-i.n process is completed.
This keyboard system is very simple because the keyboard
data can be sent by the use of a singl.e data line and
a single clock line, and further the keyboard has the
advantage of being operated at the pace of its own
clock independently of the clock of the data processing
unit.
It was found, howe-ver, that this keyboard causes false
operation due to noise when a low cost stretch cable
without shield is used as a cable for connecting the
keyboard with the data processing unit for economical
reason. Static discharge typical of external disturbance
causes noise pulse on the cable. ~he noise pulse may
be induced on both the data and clock lines. However,
the probability of a narrow noise pulse occurring
concurrently with the data sampling time is negligible,
presenting almost no problem in practice.
On the other hand, in case the noise pulse is induced
on the clock line, the same data bit is sampled twice
by the normal clock signal and the noise pulse. This
leads to false receipt OI 9 bits of a frame by the
serial-parallel shift register before the 9-bit
transmission from the keyboard is completed, resulting
in drop out of the 9th bit. Since the number of
binary l's is unchanged when the last bit dropped out
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is binary 0 and the data bit sampled twice is binary 0 and
when the last bit is binary 1 and the data bit sampled twice
is binary 1, this data error cannot be detected by parity
check.
Although such data error due to noise pulses may be
prevented by the use of a shielded cable, such a cable is
very expensive and it is desired to prevent such data error
with a low cost cable without shield.
Summary of the Inventi_n
Therefore, the object of the present invention is to provide
a serial keyboard interface system for a data processing
system of the type in which a keyboard and a data processing
unit are connected through a clock line and a data line for
transmitting keyboard data serially, which solves the
problem of erroneous transmission of keyboard data due to
noise pulses induced on the clock lineO
In accordance with one aspect of the disclosed invention
there is provided in a data processing system including a
data processing unit and a keyboard connected with each
other through a single data line and a single clock line;
said keyboard transmitting serially via said data line a key
code in a frame consisting of a predetermined number of bits
including data bits identifying a depressed key and concur-
rently transmitting via said clock line clock pulses~ one
for each of the bits of the frame, each clock pulse being
coincident in time with the significant data level of a
corresponding bit of the frame; said data processing unit
including means for counting the number of received bits in
response to received clock pulses and means for applying to
said data line a status signal indicative of the receipt of
a frame immediately when the value of said means for
counting reaches the number of bits of the frame. The
system includes an arrangement for keyboard data
transmission checking, which comprises status judging means
at said keyboard, responsive to said status signal, for
judging whether said status signal is received after the
completion of transmission of one frame and transmitting to
said clock line a response signal indicative of the result
of the judgement, and keyboard response judging means at
said data processing unit, responsive to said response
signal, for judging whether said response signal i5 positive
or negative.
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In accordance with another aspect of the disclosed invention
there is provided in a data processing system including a
data processing unit and a keyboard connected through a
single data line and a single clock line; said keyboard
transmitting serially via said data line a key code in a
frame consist.ing of a p.redetermined number of bits including
data bits identifying a depressed key and concurrently
transmitting via said clock line a clock signal having a
predetermined transition during the significant signal level
of each of the bits of the frame; said data processing unit
sampling the key code on said data line in response to said
predetermined transitions of said clock signal and applying
to said data line a status signal indicative of the receipt
of a frame immediately when the number of sampling reaches
said predetermined number of the bits of a frame. The
system includes a method for keyboard data transmission
checking, which comprises the steps of judging at said
keyboard whether said status signal .is received after the
whole frame has been transmitted from said keyboard, sending
a response signal indicative of the result o~ said judgement
from said keyboard to said data processing unit via said
cloc~ line, and sampling at said data processing unit said
clock line for judging whether said response signal i9
positive or negative to thereby determine whether the key
code has been correctly transmitted from said keyboard.
The foregoing and other objectsl features and advantages of
the invention will become apparent from the following more
paxticular description of the preferred embodiment of the
invention as illustrated in the accompanying drawings.
In the drawings which illustrate preferred embodiments of
the invention:
Figure 1 is a block diagram showing a configuration of the
invention,
Figure 2 is a diagram of another embodiment of the
invention;
Figures 3A and 3B illustrate waveforms for correct and
erroneous data transmission .respectively; and
Figure 4 is a Elowchart illustrating the operation of~the
embodiment in Figure 2.
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Figure 1 is a block diagram showing configuration of the
invention. A broken line block 6 shows a keyboard, a broken
line block 8 a data processing unit. The keyboard 6 is
connected to the data processing unit 8 by one data line 2
and one clock line 4. A key scan code transmitting means 10
transmits a scan out code to the data line 2 bit-serially in
the form of a fxame including a scan code representing a
depressed key. For example, a frame consists of a leading
start bit and the following scan code hits identifying a key
position. A clock means 12 transmits one clock pulse for
each bit to the clock line 4 in synchronism with the trans-
mission of serial frame bits. A counting means 14 counts
clock pulses transmitted to the clock line 4. Therefore,
the counting means 14 counts the number of serial hits
,
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transmitted. The counting means 14 ge~erates a trans-
mission count full (TCF) signal to a status judging means
16 when it counts the number equal to a predeter~ined
number of bits for one frame.
On the other hand, the serial bits and -the clock pulses
transmitted from the keyboard 6 are applied to a receivi~.g
part 20 of the data processing unit 8, the received
bit counting means 22 of which counts the nu~.~er of
received bits in response to each clock pulse on the
clock line 4, and generates a receive count ~ull (RCP)
signal to a status transmitting means 24 through a line 30
when it counts the number equal to the number or bits
for one frame. The status transmitting means 24 is
responsive to the si~nal RCF on the line 30 to apply
a status signal to the data line 2 through a line 32,
which is indicative of the completion of receiving of
serial bits in one frame.
The status judging means 16 of the keyboard 6 judges
whether or not the status signal is returned to the
keyboard after the completion of transmission of all
the bits for one frame, that is, af-ter the generation
of the transmission count full signal TCF from t~e
c~unting means 14. The sta-tus judging means 1~ gene-
rates a positive response signal to the clock line 4
through a line 17 when the status signal is returned
after the transmission of one frame is completed.
A keyboard response judging means 26 of the data
processing unit checks the clock line 4 through a
line 33 to judge whether the response from the ke~board
is a positive or negative response. ~hen the kevboard
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response judging means 26 detec-ts the positive response,
it activates a gate means 28 via a line 34 to cause
the received data bits to be transferred to other
processing part (not shown) of the data processing unit 8.
When a noise pulse occurrs on the clock line 4 during
the transmission of keyboard data, the received bit
counting means 22 counts twice in one clock cycle,
and generates the receive count full signal RCF before
the completion of receiving of all the bits of one
frame. At that time, the status judging means 16 does
not receive the transmission count rull signal TCF
when receiving the status signal. Therefore, it supplies
a negative response signal to the clock line 4 through
the line 17 and also supplies a control signal through
a line 18 to the key scan code transmitting means 10
and the elock means 12 so as to command retransmission
of the same scan code. When the keyboard response
;~ judging means 26 detects the negative response, it
generates a signal to the receiving part 20 through
a line 36 to discard the received data in preparation
~or retransmission.
Now~ referring to Figure 2-4, description is made on
the embodiment of the invention. Figure 2 shows the
embodiment which uses a microprocessor in each of the
keyboard 6 and the data processing unit 8. The keyboard
6 comprises a key matrix 40, a microprocessor ~M~U) 42,
and open eolleetor ga-tes 44 and 46, while the data
processing unit 8 comprises a open eollector gate 48,
a D-type edge trigger latch 50, a shift register 52,
and a microprocessor (MPU) 54. The data line 2 and
the clock line 4 are connected to +5V power supply
through reyistors respectively.
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MPU 42 is, for example, an Intel* gO48 microprocessor, and
constitutes a programmable self-scan serial keyboard in
combination with the key matrix 40. MPU 54 is, for example,
an Intel* 8Q86 microprocessor. The open collector gates 44,
46 and 48 act to provide high level output for high level
input, and low level output (typically ~round level) for low
level input. The open collector gate is shown, for example,
as 5N 7407 in "The TTL Data Book" second edition, 1976,
published by Texas Instruments Inc.
MPU 42 drives the data line 2 through the open collector gate
44, and the clock line 4 through the open collector gate 46.
The data line 2 is also connected to an input terminal of MPU
42 so as to sample this line.
The data line 2 and the clock line are connected to the shift
register 52. It samples the data signal at the falling edge
of each clock pulse, and takes in bits of one frame while
sequentially shifting from the lowest ordered stage. In this
embodiment, one frame consists of a leading start bit SB, and
the succeeding 8-bit scan code identifying a key position.
The highest ordered stage of the shift register 52 is connected
to the D input of the lakch 50. The clock C input of the
latch 50 is connected to the clock line 4.
~hen the start bit appears from the highest ordered stage of
the shift register 52, the latch 50 is set at the falling
edge oE the clock pulse so as to make Q output high level and
Q output low level. The Q output of low level drives the
output of the open collector gate 48 to the low level (ground
level),
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and thus makes the data line 2 low level. This low
level on the data line becomes the status signa~
indicating the completion of receiving of one fra~e.
Because the data line 2 is clampled at the ground
level while the latch is being SQt, the keyboard can
not transmit the data signal any longer.
The high level Q output of the latch 5~ issues an
interruption request to MPU 54, and invokes ~rogram
steps to perform the required processes such as judgement
of a keyboard response to the status sisnal. When Mr~U
42 returns the high level positive response signal via
the clock line 4 as a ke~board response, MPU 5~ takes
in the 8 scan code bits ~H of the shift register,
clears or resets the latch 50 and the shift register
52, and returns to the program process before the
interruption.
~hen the latch 50 is cleared, the Q output becomes high
` level, and the open collector gate 48 maintains the
data line 2 at high level (+5V). The high level state
of the data line is detected by MP~ 42, which lndicates
that new frame data can be transm:itted from the ke~boa-d.
When the low level negative response signal appears on
the clock line 4 from MPU 42, MPU 54 clears the latch 50
and the shift register 52 without taking in the data of
the register 52, and returns to the program process
before the interruption.
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Figures 3A and 3B illustrates operational waveforms for
correct and erroneous keyboard data transmission, respec-
tively. In Figures 3A and 3B, the waveform (a) shows
the clock pulses transmitted to the clock line 4, the
waveform (b) the data signal transmitted to the data
line 2, the waveform (c) the signal applied to the data
line from the Q output of the latch 50 through the open
collector`gate 48, the wave~orm (d) the sample timing
for MPU 42 to sample the data line 2, and the wa~efGrm
(e) the sample timing for ~5PU 54 to sample the clock
line 4 after the interruption.
In Figure 3A, when MPU 54 becomes possible to receive
the keyboard data~ MPU 54 clears or resets the latch 50
to make the data line 2 high level as indicated by 61
of the waveform (c). ~IPU 42 samples the data line 2 tG
check whether it is at high level (step 78 OL the program
flow chart in Figure 4). After confirming that the
data line 2 is at high level, the data transmitting
~ operation is initiated.
:. .
~0 MPU 42 transmits frame bits consisting o~ (a leading
start bit SB) plus (the succeeding 8-bit scan code),
to the data line 2 bit-serially. Alt~.ough preferred
values for the high level and the low level intervals
of the clock signal (a) are 50~s - lOO~s and 25~s - 50~s
respectivel~, each is set at 50~s in this embodiment.
However, these values are not important.
The data signal (b) is sampled and taken in at the
falling edge of each clock pulse (a) in the shift
register 52. Therefore, the data signal (b) needs to
have significan-t data level at least at the time of
the falling edge of each clock p~llse. 1^7hile, in this
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embodiment, each bit is arranged to have set-up and
hold time of 2.5~s with respect to the rising and falling
edges of each clock pulse i-t is important when samplin~
at the falling edge that the significant data level is
assured at the falling edge of each clock pulse.
In addition, MPU 42 is re~uired to make the data line
high level at least when sampling that line in order to
detect the status signal from the data processing unit.
If MPU 42 drives the data line 2 to low level (srouna
level) when sampling, the data line 2 is clamped,
making it unable to detect the Q output status of the
latch 50 correctly. Therefore, as indicated by 60 in
the waveform (b), MPU 42 makes the data line 2 high
level for a predetermined interval in the latter half
of each clock cycle regardless of the bit transmitted
being ~ or "0", MPU 42 sampling the data line 2 during
said high level intervalO In this embodiment, the daLa
line level is made high after 2.5~s elaspes from the
falling edge of each clock pulse. Although, in the
figure, the data signal (b) and the ~ output (c) of
the latch 50 are separately shown for convenience,
logical AND of the waveform (b) and t.ne wave~orm (c)
appears on the data line 2.
Therefore, when MPU 42 confirms the high level on the
data line in the step 78 of the program steps in ~igure
4, it applies one bit (first, the start bit SB) to the
data line 2 (step 80 in Figure 4), and makes the clock
line 4 high level after 2.5~s from the rising ed~e of
the start bit SB (step 82), the clock line 4 low level
(step 84), and the data line 2 high level after 2.5~s
from the falling edge of the clock pulse (step 8~).
MPU 42 samples the data line 2 for each clock c~cle
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(step 88) to check whether the status signal is sent
from the data processing unit (step 90). If the status
signal is not ~etected, it returns to the step 80,
an~ repeats the bit transmitting operation.
When 9 bits of one frame is taken in the shift~register
52 and thus the start bit SB appears at the highest
ordered s~age of the shift register 52,. the latch 50
is set at the falling edge of the clock pulse in the
clock cycle 9 so that the Q output goes to low level
to thereby transmit the low level status signal to
the data line 2 (62 of the wave~orm (c)). Because.the
received ~it counting operation and the status sisnal
transmitting operation are performed with hardware by
the shift register 52 and the latch 50 respectively,
these operations are shown in Figure 4 as broXen linQ
blocks 102 and 106 for distinguishing..
MPU 42 detects the status signal at the sampling o'
the clock cycle 9. In this case, since MPU 42 detects
the status signal in the condition of transmission
count=9, or after the completion of transmission OL
one frame, it indicates correct transmission, and
- MPU 42 makes the clock line 4 high level following
the clock cycle 9 as 64 of the waveform (a) (step 94
in Figure 4). This indicates the positive response.
When the latch 50 is se-t, the Q output recuests inter-
ruption to MPU 54 (step 104 in Figure 4). In response
to this, MPU 54 samples the clock line 4 in a predetermin?d
time after the interruption, as in the waveform (e),
to detect the keyboard response to the status signal
(step 108 in Figure 4), and checks whether it is high
level (step 110). In this case, the high level is
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detected, an~ MPU 54 takes in the scan code A~H of
the shift register 52 (step 112) and clears the latch
50 and the shift register 52 (step 114) to make the Q
output high level, signalling to keyboard that the
keyboard is allowed to transmit the next keyboard
data. Then, MPU 54 returns to the program prior to
the interruption by the return operation (step 116).
Figure 3B illustrates a case where a noise puise 66
appears in the clock pulse (a) during the clock cycle
5. Although the noise pulse due to static discharge
may occur in either positive or negative polarity,
the negative noise pulse 66 during the clock high is
illustrated in Fig. 3B.
In this case, the shift register 52 samples data twice
during one clock cycle at two falling edges. Therefore,
the start bit SB appears at the h:ighest ordered stage
of the shift register 52 in clock cycle 8, and returns
the low level status signal to the keyboard in clock
cycle 8 (70 of the wave form (c)). This status signal
is sampled by MPU 42 in clock cycle 8. In this case,
since the transmission is not completed because of
the transmission count~9, MPU 42 makes the clock line 2
low level following the clock cycle 8 as 68 of the
waveform (a) (step 98 in Figure 4). This indicates
the negative response. In a predetermined time after
the interruption, MPU 54 samples the clock line 4 to
detect this low level. M~U 54 clears the latch 50
and the shift register 52 without taking in the data
of the shift register 52 (step 118), returns to the
program before the interruption b~ the return step
(step 120), and continues other process until another
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interruption is caused by the retransmission. MP~ 42
prepares for the retransmission (step 100), and re-
transmits the same scan code after confirming the high
level on the data line by the step 78.
The noise pulse due to static discharge has a duration
of about 10 - lOOns, and occurs at time intervals of
at least ~Oms according to experience. The intervals
are considerably longer than the time required f~r
(the transmission for one frame) plus (the status
detection/response/retransmission), and there_ore tne
exroneous transmission is scarcely detected again in
the retransmission.
While the invention has been particularly shown and
described with reference to preferred embodiments
thereofl it will be understood by those skilled in
the art that the foregoing and other changes in form and
- details may be made therein without departiny from the
spirit and scope of the invention.
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