Note: Descriptions are shown in the official language in which they were submitted.
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COMMUNICATION S~ITC~ G S~`$TEM
Field of the ~nvention
.
The present invention relates to s~i-tc~ing
$ystem~ in general and to communication switching
systems suitable for voice frequency bands in particular.
More particularly still, it relates to a pulse amplitude
mo~ulati3n ~P~M~ and data switching system for interfacing
a plurality of trunk, radio, and/or telephone circuits
~ to a plurality of terminals~ Such a system is suitable
for air -traffic control (ATC) and similar applications
at a fraction of the cost of hitherto utilized systems.
Pulse amplitude modulation, although not representing
the state of the art, is a technique combining
advantages of both analog and digital technologies
- found particularly effective for such small switching
systems accommodating both voice frequencies and low
speed data.
Background of the Invention
~xi~sting systems, such as Westinghouse's
Terminal Communications Control Systems (TCCS) for
airport traffic control applications, utilize pulse code
modulation, time division multiplex CTDM~ and digital
s~gnal processing. The TCCS sys-tem ~nterfaces nine
hotlines, thirty-six radios, seven ringdown trunks,
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six dial trunks, two communication system networks, up to
thirty-five dial intercoms, and forty tape recorder channels.
In terms of capability, the system is excellent for intended
applications. However, the central switching and control
equipment of the system consists of six bays of more than
fifty cubic feet in volume. And while the size of equipment
is not always a determinant of cost, it should be expected
that a reduction in size would reduce the cost of manufacture,
apart from other costs associated with the space occupied
by the equipment.
In addition to disadvantages of size and cost,
prior art systems are not easily expandable and the initial
capitai investment is often too high for certain applications.
The primary reason for this is lack of modularity in the
deisgn of both hard and software. Modularity of hardware
and software would also have the advantage of efficient
maintainability and easy expandability. System design would
be simplified and reliability improved by means of multiple
redundant modules at the interfaces. Continuous self
checking should be used throughout. The core of a system
ought to be a simple (therefore highly reliable) control
module with dual redundancy.
Thus, an optimal system design would have the
following characteristics:
- combine analog/digital techniques;
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~ possess modularit~ of h~rd(~softwarei
- be continuously~sel~.di~agnosing~ and
- have multlple redundancy.
$uc~ a system is a flexible compromise. A~ will be
seen from the details of the ~nvention hereinafter
described, the features and associated advantages
of this system are:
- ci~rcuit oriented functions allow
incremental additions to the processing
poweri
~lexib~i~lity within subsystem elements
permits user interface modifications
while ensuring continuing system
integrity;
= system modularity based upon functional
bus structures allows system configuration
by selection of building blocks; and
- functional subsystems obey specific
setS of rules thereby reducing development
~isk.
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Summary of the InventIon
The basic system of the present inventi~n
consists of one or more remote term~nals and central
control equipment. The latter comprises terminal/trunk
inter~aces and a common control unit. The interfaces are
subsystems ~h,i~ch translate the external communication
equipment to a network function internal to the control
system., Each subsystem has a specific function designed
~ to service a remote terminal, a radio circuit termination,
a voice circuit termination, etc. In addition, the
following two important features characterize the
present sys-tem., Firstly, digital multiplex loops transfer
~oth voice and control messages between functional circuit
packs in the interfaces within the central control
equipment. And secondly, all circuit terminations are
fully available at the network bus, so that each inter-
face has d~rect access to vo~ce messages on all channels.
~urther features of the present system are the
partitionin~ o~ the hardware and software into building
blocks (modularization~, a selective redundancy for
critical modules to provide "hot standby" capability
,f,or immediate reconfiguration~ and periodic fault
~on~toring by means of sys-tem-~ntegral test equipment
to identify faulty circuit cards.
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Two significant advantages ~low from the
above features and othe.r as~ects o~ the i`nvention;
namely, an order of magnitude reduction both in size
and in cost,
~ h ~ts broadest aspect, the present invention
provides a communication swi-tching system comprising:
(a) a central mult~ple network bus~
(b) common control means;
(c) a plurality of interPace means for
interfacing at least one operator position
terminal and a plurality of auxiliary
circuIt terminations to one another and with
said common control means;
(d) said central multiple network bus inter-
connecting said plurality of interface
means according to periodically generated
address codes; and
(e) said plurality oX ;nterface means providing
t.ime div~s~on multiplexed representations
of the assoc~a-ted aux~liary circuit termination
on said central multiple network bus for
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d~rec-t access thereto by the o~her interface
means.
In a narro~er aspect of t~e invent~on, the
central multiple net~ork bus has t~e time di~sion
multiplexed representations mult;plexed thereon as pulse
amplitude modulation signals..
Brie~ Descrip-tion of the Draw;ngs
The preferred embodiment of the present invention
will now be described in conjunction with the annexed
drawing figures in which;
~gure 1 is a block~d~agram of the communication
s~itching system according to the present invention;
Figure 2 ~s a block-diagram of the common
control subsystem of the system of figure 1;
Figure 3 is a block-diagram of the terminal
interface subsystem of the system of figure 1,
~Igure 4 is a block-d~agram o~ the radio
inter~ace subsystem of the system of figure 1,
F~gure 5 is a block~diagram of the remote
term~nal of the system of Figure l;
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~ igure 6 is a flow chart showing an overview
of the operating system of the common control subsystem
of figure 2; and
Figure 7 illustrates the time-sharing
scheme of the operating cycle of the operating system
of figure 6.
Detailed Descrip-tion of the Preferred Embodiment
Referring to figure 1 of the drawings,
the switching system comprises a PAM 3 Data bus
system 10, a common control A 11 in continuous
bilateral communication with the bus system 10,
and a hot standby common control 11', which takes
over control in case of failure of the common
control 11. A trunk interface 12 is also in bilateral
communication with the bus system 10 and interfaces it
with a~plurality of voice trunks, while a radio
interface 13 similarly interfaces a radio transciever.
Two terminal interfaces 14 and 14' similarly interface
remote terminals 15 and 15', respectively, with
the bus system 10. The bus system 10 transfers
both control and voice messages between the devices
11 to 1~. As will be explained la-ter, the. trunk
and radIo interfaces 12 and 13 provide on the
bus system 10 time division multiplexed repre-
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on the bus system 10 time division multiplexed repre-
sentations of the circuit denominations (i.e. voice
trunks and so on) in the form o~ amplitude modulated
pulses (PAM~, so that all circuit terminations are
available during the designated time-slots for direct
access by system components. A Byte CPU 17 inter~aces
the bus system lO to a maintenance terminal 18, while a
line interface l9 inter~aces a plurality of local
~ telephones.
1 Figure 2 shows the common control 11 in some
detail. It is run under control of a 3.58 MHz clocking
oscillator 20 which generates a two-phase master clock
- of 397~8 KHz nominal. Divider 21 shapes and provides
a primary clock CLKl which provides the basic timing
~unctions to all devices that access the bus system lO
in order to synchronize all control, signalling and
supervision functions to the primary clock CLKl. A
delayed:-~ version CLK2 ~s also generated by the
divyder 21. The cloc~ CLKl drives a bus address
generator 22 ~hich is a t~elve~state counter. ~t
provides ~ive address lines, which sequentially
determine the ti~e slot addres~ that ~s active on the
bus system lO. In addition~ a nomi`nal lO0 ~z clock
derived ~rom t~e most sign~ficant bus CMSB~ of the
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generator 22 periodically ena~les a data load generator
23. A bus dr~ver inter~ace 24 bu~fers the time-slot
addresses generated in generator 22, the data load
signal generated in generator 22, as well as the
system clock CLKl onto the bus system 10. As both the
common controls 11 and 11' are running simultaneously,
only the bus driver interface 24 is enabled -to access
the bus system 10, ~h~le the other bus drîver interface
` 24t~ is disabled from access to the bus system 10 by
a clock failure and activity control 25~ In addition,
the common control 24 ComprISes an audio demodulator
26 under control of an enable signal from the radio
transc~e~er as any one of the radio channels becomes
actuals The demodulator 26 then demodulates the PAM
signal appearing on the bus system 10 and enunciates
it over a room loudspeaker monitor.
Turning:now to f~gure 3, the terminal inter-
face 14 cOmprIses analog and digital circuitry in
order to interace a remote terminal 15 via its cable
l~nk to -the system. The terminal interface lLI comprises
~ bus ~nterface 3Q inter~ac~n.g the terminal 15 with -the
bu$ system lQ~ The bus ~nter~ace 30 buffers t~e digital
~gnals present at the bus sys-tem 10 to the remaining
components of the terminal inter~ace 14 by transplanting
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the h~gh level ~gnal~ on the bus 1~ to lo~ level
log~c signals latched accord~ng to the primary system
clock CLKl, and v~ce versa for the outgoing signals.
digital filter 31 accepts rece~ved command flags as the
received data address is matched against the bus system
10 address~ However, the dIg~tal f~lter 31 requires two
successive matching states to ~e rece~ved ~efore it
modifies a connection memory 32 to a new connection
state. This ~s accomplished by writing error free
incomi~g connec*ion states into a last look memory 33
while the immediately previously received error-free
connection state stored in the last look memory 33 is
compared to the currently received connection state~
~hen both these states are identical the serial output
from the last look memory 33 is written into the
connection memory 32, otherwise the latterls output
IS re~circulated to its input. Ser~al select flags
from the connection memory 32 are continuously-: read
in synchronism with the time slot address present at
the bus interface 30. Each select flag determines
whether or not a corresponding TDM slot (channel~
is accessed, The bus interface 30, in addition to
buffering data and supervision signals, also buffers
audio signals to and from aud~o receive 34 and audio
transmit 35, respectively. Both receive and transmit
audio signals are sampled from and transmitted
onto the bus 10 ~n accordance with the connection
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memory 32 flag~ which des~ignate ~he receive and
transm~t TDM time slots o~ the ~us la~
~ n Pigure 4 the audio ~nter~ace 13 is shown.
A radio transceiver 4Q ~s interpaced to the bus system
1~ by being assigned a receIve and transmit audio
t~e slot corresponding to a specifIc channel. The
status of the assoc~ated radio channel is time~division
- multiplexed into the supervision d~gital bit stream
~ ~hile control flags are accepted ~rom the signalling
~it 5tream. Again a bus interface 41 bu~ers con-trol
and signalling informatIon present on the bus system 10
synchronizing the incomlng information via ~ts la-tching
actIon as already described in connection with the
terminal interface 14. A circuit for signalling
supervision 42 enter$ digital signalling ~its serially
nto a signall~ng memory 43 where they are available
~or radio channel control. Again receive and transmit
audio 44 and 45 access the àssigned time-slot in
half-duplex operation, where the push-to-talk signal
controls the associated transceiver 40.
The terMInal equipment lS is shown in
figure 5. It comprises three basic circuit packs:
a control circuit, a key!d~splay circu~t and, o~
course, an audio c~rcuit. The control circu~-t
compr~ses a mtcroprocessor 50 operated at a 3.53 MHz
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ma~ter cloc~ pro~d~ng a t~i`m~ng cycle of ~56 microseconds.
The m~croprocessor 50 ~S ~n~tructed ~y~ a ~rm~are memory
51, ~hich ~s a six k~lolyte ~O~. Var~able data is stored
in RAM 52~ The CPU 50 ~s an ~NTEL 8085A, t~e sanity
of which is maintained by a t~me~out~cIrcu~t (no-t shown2
that requIres periodic trigerr7`ng and is direc-tly connected
-to the non~maskable interrupt of the CPU 50~ Data interface
IS provided by a UART 53, which drives the 4-wire data line
connecting the terminal to the system by means of differential
~ lîne drivers (not shown~. The UART 53 continuously
rece~ves and transmits data by periodically interrupting
the CPU 50 to read and write the UART 53 buffers.
A display memory 54 comprises four RAMs which provide
a four bit display "nibble" that determines the display
symbol for the currently addressed display. By scanning
the R~M 54 continuously multiplexed symbol images are
displayed which are free of flicker~ ~Ihen any given
memory symbol is to be modified the CYU 50 momentarily
blanks the display and enters a new symbol "nibble" into
the memory 54. A key scanner 55 scans the matrix of keys
enabling a group of eight keys at a time; key groups
are enabled in sequence. Any contact closure within a
g~oup appears at the respective bit position in the
keyboard da-ta byte. A key/display circuit 56 provides
enable signal$ to display rows such that the bit pattern
address~ng ~t~e vertical bus can selectively display the
symbol at the intersected display. The audio is received
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and transm,itted via $,e~ara-te ~ala~ced l~e~ and ~
multiplexed ~de~ultî~p~exed`~ n ~e ter~nal inter~ace
14 shown ~n f~gure 3.
SYSTEM OPERATION
The real-time operating system shown in the
flow chart in Fig.6 is a microprocessor based system
(located within each of the remote terminals 15 and 15')
which in-teracts with its environment in a time scale
dictated by the needs of that environment. The system
is interfaced to the outside world by hardware communication
and interface devices and responds to stimuli in a time
range of milliseconds to seconds. The real time operating
system is particularly suitable for the control of
communication equipment, where a limited number of
resources perform a multitude of tas]cs. Concurrent
processing (running several processes simultaneously)
makes optimum use of the available resources. The
system implements concurrent processing by means of a
time-sharing scheme. Each process has dedicated to it
a certain fraction of system time. In this manner,
each process is perceived as if it had a separate
dedica-ted processor. Since peripheral devices are typically
much slower than the processing system,for example a
data channel,' the system is used most effectively by
running another program while waiting for the da-ta channel
t'o complete its task. As the data channel terminates
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its task an interrupt is sent to the processor and the
current process is suspended while the processor handles
the data channel originating the interrupt. The suspended
process will thereafter resume execution. Deciding which
program should run at a particular time is a function of
an executive (or driver) program 60. Operation of the
executive program 60 takes up a percentage of system and
introduces an overhead which is unavoidable.
Interrupts synchronize the system to its
lG environment; -they may be processed in the order -they
occur or be processed on a priority basis where the
highest priority interrupt in a hierarchy is processed
first. Each group of cooperating processes 61', 61" to
61n is used to implement a certain software task. The
processes 61', 61" to 61n are independant of each other,
and new processes may be added to the real-time operating
system at will. The multi~task executive 60 is used
to synchronize the operation of the processes 61' to 61n.
The system is event driven as well as schedule driven.
Interrup~s from external hardware are events driving
the system and overlap the system schedule shown in
Figure 7.
The executive program 60 uses a status byte
EXSTA to indicate the order in which processes are to be run.
The byte EXSTA may con-tain up to eight flags, one for each
process. When a flag is active, it points to an address
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in one of the programs 61~ to 61n add~ess tables, This
address is the location of the stack pointer in the
corresponding process program. The process programs 61'
to 61n are run in sequence. As an interrupt from the external
hardware occurs, it is stored in a request buffer until
the process program 61i necessary tc handle that interrupt is
reached. The processes 61t` to 61n are run on a ten
millisecond schedule. The byte EXSTA is updated af-ter
each process program has been run.
Features modules 62', 62" to 62n are provided
to handle the different interrupts seen by each process program
61~ to 61n. A typical application of a features module 61i is
to implement the various control functions originating from
the keyboard 56 of the remote terminal 15.
Each of the process program modules 61' to 61n
containes data necessary for operation of the process. In
a typical case the follcwing data is stored:
- identification for process scheduling;
- indication whether process is currently
running;
- an entry address to identify program
location where execution starts;
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- a stack pointer used to retrieve return
addresses and register contents from
stack;
- a stack (a block of memory where return
addresses and register contents are stored
for use by the process~; and
- the actual process program.
The process program is re-entrant so that it
continues running undisturbed when it has been reactivated
af-ter suspension. This requirement is met by storing the
register contents and return address in the stack. The
-- return addre~s tells where the program should be re-entered
after re-activation~ Of course, several return addresses
are necessary if the process program con-tains a number of
subroutines~ and nesting of subroutines demands a return
address for each calling program. The stack is an ideal
device for this as it is a last-in/ first-out memory.
Thus, the last return address will be the first read from
the stack and the program will work its way back to the first
subroutine call in an organized manner.
Features modules 62~ to 62n are program
modules which are called ~y the process programs to perform
a features-related function. As a result, the function
of the real-time operating system can be altered by merely
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changing the features modules 62' to 62n. The executive
program 60 and process program modules 61' to 61n are
designed to form the basis of a large number of desirable
possible sys-tems. The only difference between these systems
is evoked and determined by the features-modules 62' to 62n.
Hence, a programmer can modify the system without requiring
detailed knowledge of the executive program 60 and -the
process program modules 61' to 61n. This makes the sys-tem
available to a number of users with minimal alteration.
A feature module, say 62i , fulfills its function
as follows. The process program module 61" will indicate that
a particular function is to be performed. Through an interface
table 63 the appropriate feature module tin this case 62i
will be called to perform this function. When completed,
the feature module 62i will return to the calling process
through -the interface table 63. An example of this is the
key scan process, which identifies that a particular
key has been activated. The address (i.e. identity) of the
activated key will be used to identify which feature module
is to be called and the latter is called through the
interface table 63. The interface table 63 allows several
processes to share common feature modules. The feature module
then performs the function (such as monitor on the room
loudspeaker) which the key was used to initiate by the
operator. Execution will then return to the calling
process through the interface table. Accordingly, the
function of a key may be redefined by changing its
feature module.
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By way of ~urther explanation of feature modules'
function, the basic radio control features w~ll be described.
Entry to the basic radio control features module !~ say 62j,
is made by executing a call from the key scan process
program module, say 61n, or from the incoming data through
the radio interface 13. Calls from the feature module are
made through the interface table which identifies a series
of subroutines located within the process program modules
61l to 61n. Upon completing a sub-routine in a process program
module, a return is made to the feature module. Addi-tional
subroutine calls to other processes take place within the
feature ? S implementation algorithm of the feature module.
Upon completing a feature module algorithm a return to the
original calling process is executed.
Typical operation is illustrated by following the
sequence of events that take place upon the operation of a radio
channel select key. The keyboard is periodically scanned by
the key scan process which thus detects the activation by an
operator of a channel select key. The process uses an address
RFKEY located within the key vector table in:order to
execute a subroutine call to the subroutine RFKEY located in
the basic radio control feature module 62j. The status
of the radio channel state corresponding to the activated
key number is used to determine the func-tional algori-thm
to be executed. For example, operating the select key for -
an idle radio channel the functional algorithm is "select
request program commencing at address RF~02". The radio
channel status table is updated to the select state and the
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feature module executes a call to a data out subroutine in the
data out handiing process in one of the modules 61 to 61n.
The address of that subroutine is available at a corresponding
location of a subroutine address table. When the data out
subroutine has been completed, a return is made to -the
feature module 62i. The feature module determines the display
code associated w;th -the channel and executes a call to the
mul-tiplexed display process subroutine. The associated
subroutine address was found from the subroutine address table.
~When the display subroutine of the multiplexed display process
has modified the channel display in the remote terminals 15,
15l, etc.., a return is made to the feature module 62i. As the
feature module 62i has transferred a data transmit reques*
and has updated the channel display, its operation is now
terminated by executing a return to the key scan process
- which had originated the sequence of subroutines. The key
scan process continues to scan for other key activations until
it is suspended.
Other processes within any of the process program
modules 61 to 61n and features within the feature modules
62 to 62 operate in like manner.
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