VIDEO SIGNAL IMPOSE CIRCUIT

CIRCUIT DE COMBINAISON DE SIGNAUX VIDEO

English Abstract

ABSTRACT OF THE DISCLOSURE
Disclosed is an arrangement for combining video signals from two
sources, for example a TV signal and a signal from a computer. Known arrange-
ments of this type mute the first signal and then insert the second signal
but, because of the response time of the muting circuitry, the composite
picture displayed on a cathode ray tube is defective in that it includes a
white or black band. In this invention, the output of a demodulator for
the first signal is connected to a series circuit of a resistance and an
open collector type inverter so that the resistance lowers the cutoff level
of a transistor constituting a buffer amplifier to which the demodulated
first video signal is fed. The operating point of the transistor is kept
always in an active region so that startup of the transistor is rapid to
enable high speed response of the buffer amplifier, thereby improving the
quality of the composite picture displayed on the cathode ray tube.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. An arrangement for combining video signals from two sources compris-
ing an RGB demodulator for demodulating a first video signal, a video signal
combining circuit having a buffer amplifier adapted to receive the demodulated
first video signal and means to receive a second video signal, said combining
circuit having output means connected to a cathode ray tube display unit, an
output line of said demodulator being connected to a series circuit of a
resistance and an open collector type inverter so that said resistance lowers
the cutoff level of a transistor constituting said buffer amplifier.
2. An arrangement as claimed in claim 1 wherein said inverter is a
transistor-transistor logic integrated circuit.
3. An arrangement as claimed in claim 1 or 2 wherein an insertion
period signal applied to said inverter blocks said first signal and permits
said second signal to be applied to the cathode ray tube.

Description

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This invention relates to a video signal combining circuit used for
combining a first video signal, such as a color TV signal, and a second video
signal made by a computer or the like.
Generally, the first video signal, for example a color TV signal,
and the second video signal, for example a signal made by a computer, are
combined by the following means.
The first video signal is demodulated to RGB (red, green and blue)
by an RGB demodulator and then combined with the second video signal from the
computer by an insertion circuit to be output to a cathode ray tube display
unit. In order to have the first video signal, for example the color TV
signal, as the background picture, it is necessary to take out the first
video signal only during an insertion period for the second video signal and
keep the taken-out part in the black leve:L.
Conventionally, for the above purpose, the output line of the demod-
ulator is subjected to muting by an insertion period signal derived from the
second video signal and the second video signal is inserted into the black
level period obtained by such muting ~partially taking out the color signal
from the first video signal). Since the high speed response fo~ the muting
conventionally is insufficient, the black level period taken out and the inser-
tion period are slightly different from each other so that the composite pic-
ture is defective in that a white or black band attached thereto lowers the
quality thereof.
In the light of the above point, this invention has been designed.
An object of the invention is to improve the quality of composite pictures
displayed on a cathode ray tube.
Therefore, this invention provides an arrangement for combining
video signals from two sources comprising an RGB demodulator for demodulating
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the first video signal, a video signal combining circuit having a buffer ampli-
fier adapted to ~eceive the demodulated first video signal and means to receive
the second video signal, said combining circuit having output means connected
to a cathode ray tube display unit. Connected to an output line of the de-
modulator is a series circuit of a resistance and an open collector type
inverter so that the resistance lowers the cutoff level of a transistor constit-
uting the buffer amplifier. The operating point of the transistor is kept
always in an active region so that startup of ~he transistor is rapid to enable
high speed response of the buffer amplifier, thereby improving the quality of
the composite picture displayed on the cathode ray tube.
Next, an embodiment of the video signal combining arrangement of
the invention will be detailed in accordance with the drawings, in which:
Figure 1 is a block diagram of an arrangement according to the
invention, and
Figure 2 is a circuit diagram detailing the combining circuit of
Figure 1.
In Figure 1, 1 is an input term:inal for the first video signal tfor
example, a color TV signal) and 2 is a synchronous separation circuit which
derives the synchronizing signal from the first video signal.
An RGB demodulator 3 is connected to the output of the synchronous
separation circuit 2. The demodulator 3 derives the signal wave form from
the demodulated wave (video signal), and feeds red, green and blue signals
to combining circuit 5 via its output lines 4R, 4G and 4B, respectively.
The circuit 5 serves to combine the demodulated first video signal
and the second video signal from the computer or the like and output the
composite signal to a cathode ray tube display unit 7 at the subsequent stage,

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the combining circuit 5 and the cathode ray tube display unit 7 being con-
nected to each other by the composite output lines 6R, 6G and 6B.
The combining circuit 5 connects to input lines 8R, 8G and 8B for
the second video signal and also to an insertion period signal line 9.
In Figure 2, the R (red) system only is shown (lines 4R, 6R, 8R,
9R), the other systems G~green) and B(blue) being the same as the red system.
Considering Figure 2 in detail, the output line ~R of demodulator 3
connects through a resistance 10 with the base of NPN transistor 12 constituting
a buffer amplifier 11. The node a of the base of transistor 12 and resistance
10 connects to the insertion period signal line 9R through a series circuit
of resistance 13 and inverter 14 of open collector type. Inverter 1~ may be
of TTLIC (Transistor - Transistor Logic Integrated Circuit) type.
An NPN transistor 16 constituting a buffer amplifier 15 at the sub-
sequent stage in the combining circuit 5 has its base connected to the emitter
of a PNP transistor 18 through the node b and a diode 17, the base of trans-
istor 18 connecting to the input line 8R of the second video signal source
through a resistance 19.
Here, the resistance 13 serves to lower the cutoff level of trans-
istor 12 constituting the buffer amplifier 11, and has a resistance value
selected to keep the base potential (at the node a) of transistor 12 above
the cutoff level for transistor 12, so that the operating point thereof is
selected to have a value which is always in the active region. As an example
the value of resistance 13 may be 160 ~ in this embodiment.
Next, an explanation ~ill be given of the operation of the illustrated
embodiment constructed as described above.
Now, in order to combine the demodulated first video signal and the

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second video signal, the second video signal is fed in via the input line 8R,
and the i.nsertion period signal obtained from the second video signal is fed
in via the insertion period signal line 9R.
The high level inserkion period signal fed into the signal line 9R
is inverted to a low level signal by the inverter 14 so that the first video
signal at the node a in Figure 2 is subjected to muting, whereby the second
video signal is inserted at the node b in Figure 2 into the black level period
obtained by the muting, thus making it possible to obtain the composite pic-
ture with the first video signal as the background picture.
In this case, in the line 9R is provided the series circuit of
resistance 13 and open collector type TTLIC 14, the resistance 13 keeping
the cutoff level of transistor 12 low and the operating point therecf being
kept always in the active region to thereby quicken the startup of transistor
12 and switch it at high speed to enable high speed response of buffer
amplifier 11. As a result, the black level period taken-out is equal to the
insertion period, so that no white or black band is attached -to the composite
picture, thereby improving the quality thereof.