Note: Descriptions are shown in the official language in which they were submitted.
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BACKGROUND OF THE INVENTION
_ield of the Invention
The present invention relates to static memory cells
realized utilizing dual-channel technology for VLSI applications,
and in particular to such a static memory cell having a
substantially reduced surface area.
Description of the Prior Art
Static memory cells constructed utilizing dual-channel
technology are generally realized in CMOS technology. In such
known memory cells, n-channel switching transistors and p-channel
load elements are generally disposed at the boundary surface of a
p-type semiconductor substrate, the source and drain regions of
the load elements being disposed in an n-type trough-like
semiconductor region which is implanted in the p-semiconductor
substrate. Such conventional construction for static dual-
channel memory cells, however, necessarily requires a relatively
large semiconductor surface because of the presence of the
trough-like semiconductor region.
SUMMARY OF THE INVENTION
An object of the present invention is ts provide a
static memory cell in dual-channel technology which occupies a
substantially reduced semiconductor surface than conventional
static memory cells of this type.
The above object is inventively achieved in a static
memory cell in dual-channel technology wherein each of the load
elements has respective source and drain regions consisting of
highly doped sections of a layer of polycrystalline silicon
covering the boundary surface of the semiconductor substrate and
separated therefrom by an insulating layer, the polycrystalline
silicon layer also having weakly or non-doped sections disposed
between the highly doped sections which function as channel
regions, an implanted semiconductor region extending to the
boundary surface of the semiconductor substrate, the implanted
region being of a conductivity type opposite to that of the
semiconductor substrate and being highly additionally doped for
functioning as a gate region.
The above construction, wherein the load elements, each
in the form of an insulated gate field effect transistor (IGFET)
of a second channel type, are at the level of the polycrystalline
silicon layer applied to the semiconductor body with an insula-
ting layer therebetween, so that the trough-like semiconductor
region required in conventional dual-channel static memory cells
is eliminated. Control of the load elements proceeding from the
voltages applied to the various circuit nodes is achieved in
those regions of the semiconductor substrate disposed immediately
below the channel regions of the load elements, so that no
additional semiconductor surface need be utilized for this
purpose. The small surface area requirement for each memory cell
permits a large number of such memory cells to be disposed on a
single semiconductor substrate with a high component density.
Thus, in accordance with a broad aspect of the invention
there is provided a static dual-channel memory cell comprising:
two switching transistors of a first channel type disposed on a
semiconductor substrate having a boundary surface; two load
elements of a second channel type respectively interconnected
in series with the drain regions of said. switching transistors
and a supply voltage, said load elements ha.ving respective source
xegions connected to a reference voltage; at least one selection
transistor interconnected between the drain region of one of
said switching transistors and a bit line, said selection tran~
sistor having a gate region connected to a word iine; each
switching transistor having a drain region connected to the gate
region of the other switching transistor and to the gate region
of the load element connected in series with said other switch-
ing transistor; and each of said load elements having a source
region and a drain region consisting of respective highly doped
sections of a polycrystalline silicon layer covering said bound-
ary surface of said substrate and being separated therefrom by
an intermediate insulating layer, a channel region consisting of
a weakly or non-doped section of said polycrystalline silicon
layer disposed between said highly-doped sections, and a gate
region consisting of an implanted region in said semiconductor
substrate having a highly doped conductivity type opposite to
that of said semiconductor substrate, and extending to said
boundary surface.
DESCRIPTION OF THE DRAWINGS
.
Fig. 1 is a circuit diagram of a static memory cell
constructed in dual-channel technologyO
Fig. 2 is a cross-section of a load element for a
-2a-
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memory cell constructed in accordance with the principles of the
present invention.
Fig. 3 is a plan view of a portion of a semiconductor
substrate surface on which a memory cell constructed in
accordance with the principles of the present invention is
integrated.
Fig. 4 is a cross-section of a portion of the structure
shown in Fig. 3 taken along line IV-IV.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The basic circuit diagram for a static memory cell
constructed in dual-channel technology is shown in Fig. 1. The
memory cell includes two switching transistors Tl and T2 which
f ~3 may be, for example, n-`field effect transistors Load elements
T3 and T4 which may be, for example, p-channel field effect
transistors, are respectively connected in series with the
switching transistors Tl and T2. The respective source terminals
of the load elements T3 and T4 are conducted to a circuit node 1
which is connected to a supply voltage VDD. The respective
source terminals of the switching transistors Tl and T2 are
conducted to a circuit node 2 which is connected to the reference
po~ential~ The drain terminal of the switching transistor Tl is
at a circuit node 3 which is connected to the gate of the load
element T4 and to the gate of the other switching transistor
T2. The drain terminal of the switching transistor T2 forms a
circuit node 4 which is connected to the gate of the load element
T3 and to the gaze of the other switching transistor Tl. The
circuit node 3 is connected Jo a bit line BL through a selection
transistor T5, and the circuit node 4 is connected to a second
bit line BL through a second selection transistor T6. the
respective gate electrodes of the selection transistors T5 and T6
are connected to a word line WL.
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cross-section of a load element constructed in
accordance with the principles of the present invention for use
in the circuit shown in Fig 1 as the transistors ~3 or T4 is
shown in Fig 2. As shown in Fig. 2, a semiconductor substrate 5
which may be comprised for example, of p-type silicon, is
covered with an electrically insulating layer consisting of a
thin film region 6a and thick film regions 6b. Assuming that the
electrically insulating layer cons;sts of SiO2, the region 6a may
be referred to as a gate oxide region, and the regions 6b may be
referred to as field oxide regions. A field implantation region
7, that is, a semiconductor region which is provided with
additional doping intensifying the basic doping of the substrate
5, is disposed below each field oxide region 6b at the boundary
surface 5a of the semiconductor substrate 5.
A layer 8 of polycrystalline silicon is applied to the
insulating layer consisting of 6a and 6b, the layer 8 exhibiting
two sections 9 and 10 which are P+-doped and are disposed above
the field oxide regions 6b. The sections 9 and 10 may have a
doping density of, for example, at least 101~ cm 3. A region 11
of the polycrystalline layer 8, which is non-dopea or weakly p-
doped, is disposed between the sections 9 and 10. the region 11
has a doping density of, for example, lol5 cm 3. An n+-doPed
region 12 is implanted in the p-type substrate 5 below the region
11. The region 12 may have a doping density of, for example,
1019 cm 3. The sections 9 and 10 respectively form the source
region and the drain region for the load element between which
the p-channel region 11 lies. Upon supply of a positive voltage
VDD at a terminal 9a, and upon connection of the reference
potential to a terminal lOa, a current flows in the channel
region 11. upon the application of a positive voltage to the
gate region 12, however, constriction of the cross-section of the
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channel region 11 occurs, the bulk resistance encountered by the
current substantially increasing with rising voltage at the gate
region.
As shown in Fig. 1, the source region 9 of the load
element shown in Fig. 2, which is employed as the load element
T3, is connected at a terminal 1 to the supply voltage VDD,
whereas the drain region 10 is connected to the circuit node 3.
Also as shown in Fig. 1, the gate region 12 is connected to the
other circuit node 4 which, as a function of the memory stalls of
the cell, is supplied with a voltage between zero volts and VDD.
A portion of a semiconductor substrate showing a plan
view of an entire memory cell corresponding to the circuit
diagram of Fig. 1 is shown in Fig. 3, limited by the line 13.
The boundary surface 5a (shown in Fig. 2 but not visible in Fig.
3) is covered with field oxide regions 6b and gate oxide regions
6a, the boundaries between the regions 6a and 6b proceeding along
the lines 14. The gate oxide region 6a undertakes a meandering
path defined by the lines 14. At the top portion of Fig. 3 f the
region 6a is surrounded at the left and right by a frame-like
field oxide region 6b. Strips of highly doped polycrystalline
silicon are disposed on the regions 6a and 6b, these being
illustrated with cross-hatching for purposes of identification.
A first strip 15 at the upper portion of Fig. 3 proceeds from
left to right and covers portions of the field oxide region 6b
proceeding in the vertical direction, and has horizontal branches
15a and 15b. A second strip 15 of polycrystalline silicon
proceeds in the lower portion of Fig. 3 in a horizontal direction
and represents the word line WL.
An n~-type semiconductor region 17 is disposed below
the entire meandering gate oxide region 6a at the boundary
surface 5a, with the exception of four island regions 18, 19, 20
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and 21, which are illustrated with dot-dash lines. The regions
18-21 are projections of the semiconductor substrate 5 which
extend into corresponding recesses in the n~-type regions 17 up
to the boundary surface 5a. Tracks 21a, ~2 and 23 are disposed
above the strips 15 and 16 and separated therefrom by an
intermediate insulating layer. Those tracks 21a through 23
consist of, for example, aluminum and are illustrated with single
hatching. Portions of the semiconductor region 17 are in
electrical connection with the tracks 21a through 23 in the area
of respective contact holes 24, 25 and 26 which are provided in
the gate oxide layer 6a. Portions of the semiconductor region 17
are also in electrical connection with the ends of the branches
lSa and 15b of the strip 15 in the areas of two additional
contact holes 27 and 28.
The transistors Tl through T6 are indicated in Fig. 3
by brackets. The load element T4 is at the level of the
polycrystalline silicon strip in the area of the branch 15b; its
channel region lla being illustrated with single hatching. The
load element T3 lies at the same level in the area of the branch
15a; its channel region llb being also indicated with single
hatching. The transistor Tl has a source region and a drain
region respectively to the left and right of the region 19, which
are portions of the region 17. The switching transistor T2 has a
source region and a drain region respectively Jo the left and
right of the region 20, which are also portions of the region
17. The selection transistor TS has a source region and a drain
region respectively above and below the region 18, which are also
portions of the region 17. Lastly, the selection transistor T6
has a source region and a drain region respectively disposed
above and below the region 21, and also portions of the region
17. The track 21a corresponds to the bit line BL, the track 22
dl~83~4
corresponds to the bit line BL, and the track 23 corresponds to
the circuit node 2 of Fig. 1. An extension of the strip 15 is
provided with the terminal 1.
A crcss-section of a portion of the structure shown in
Fig. 3 is illustrated in Fig. 4, wherein the semiconductor region
17 disposed below the gate oxide layer 6a is visible. The
channel region of the transistor Tl is referenced at 19. The
remaining circuit components in Fig. 4 correspond to those
components already identified in connection with Fig. 2 and Fig.
3 end are identified with the same reference designations.
As shown in Fig. 2, the strips l of polycrystalline
silicon outside of the region 11 are p~-doped~ According to Fig.
3, however, it is preferrable that the portion of the branch 15a
disposed to the left of the region llb and the portion of the
branch 15b disposed to the right of the region lla are n+-doped,
because those branches respectively contact the n+-doped
semicoductor region 17 at contact holes 27 and 2~. In this case,
a portion of the branch 15b adjacent to the channel region lla,
referenced at 15c in Fig. 4, may be provided with p+-doping.
Thi- also applies to a portion of the branch lSa adjacent to the
channel region llb. The p-channel character of the load elements
~3 and T4 is even more greatly emphasized by so doing.
The particularly simple structure of the dual-channel
memory cell constructed in accordance with the principles of the
present invention as can be seen from Fig. 4 is achieved because
the channel region of Tl, the gate region of T4, and one
Gonnection region of T5 each consist of a portion or sub-region
of the n~-doped semiconductor reyion 17 (Fig. 4) so that the
connecting lines between these regions in Fig. 1 are
eliminated. The same also applies to the drain region of T2, the
gate region T3, and one connection region of T6. There exists no
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couplings between the aforemention connecting lines.
Moreover, the channel region 19 of the transistor Tl is covered
by a portion of the branch 15b of the polycrystalline silicon
strip, so that the line illustrated in Fig 1 between the circuit
node 4 and the gate of the transistor Tl is eliminated.
Similarly, the ehannel region 20 of the transistor ~2 is covered
by a portion of the branch 15a of the polycrystalline silicon
strip so that the line illustrated in Fig. 1 between the circuit
node 3 and the gate of the transistor T2 is eliminated. Cross-
couplings between the later lines, which would be present in a
conventional realization of the memory cell show in Fig. 1, are
thus not present in the memory cell disclosed herein.
Voltage control of the gate regions 12 of the load
elements T3 and T4 through the circuit nodes 3 and 4 or through
the collection regions of the selection transistors T5 and T6
occurs such that a node, for example, 3 connected to VDD switches
the load element of the other circuit branch, for example,
transistor T4, with such a high resistance so that substantially
no leakage current flows. Also due to the high resistance
switching, the circuit branch for the node under consideration,
such as node 3, is switched so that the other node, for example
node 4/ is at the reference potential and therefore the switching
transistor, such as transistor Tl, having its source-drain
segment connected to the node 3, has its gate connected at
reference potential ana is thus inhibited. Thus voltage control
of the load elements as in a CMOS realization of the memory cell
occurs so that no static dissipated power arises. Power is
consumed only when switching the memory cell from one memory
state to the other. Voltage control of the load elements occurs
such that the function of the memory cell is substantially not
disturbed even given penetration of particles. Because the
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controlled load elements are at the level of the polycrystalline
layer, undesired thyristor effects similarly do not exist in the
memory cell structureD No additional integration surface need be
utilized for this purpose because of the control of the load
elements through the gate regions which are disposed below the
polycrystalline branches 15a and lSb. A high component density
of a large number of memory cells exhibiting this structure on a
monolithic semicoductor body is achieved.
Driving of the memory cell disclosed herein by means of
the word line WL and the bit lines BL and BL occurs in a manner
known to those skilled in the art. When a logic l is supplied
by BL through the conductively switched transistor T5, the node 3
assumes the potential VDD, and the nod 4 assumes the reference
potential. The logic Rl" is thus stored. readout of the stored
signal occurs given conductively switched selection transistors
T5 and T6 through conventional read amplifiers. Further details
of such conventional operation are described, for example, in the
text "Semiconductor Memory Design and Application by Luecke,
Mize and Carr, 1973 at pages 116-119~
Although and modifications and changes may be suggested
by those skilled in the art it is the intention of the inventor
to embody within the patent warranted hereon all changes and
modifications as reasonably and properly come within the scope of
his contributiol- to the art.
