Note: Descriptions are shown in the official language in which they were submitted.
DIGITAL TIME BASE CORRECTION
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BACKGROUND OF THE INVENTION
Field of the Invention
_,
This invention relates in general to time
5 base correction apparatus end, in particular, to such
apparatus as may be employed in the processing of
multi-channel digital signal&.
To razings
The invention as well as Pie prior art will
10 be described with reference to the figures of which
Fig. 1-3 are diagrams useful in describing
the invention,
Ego. 4 is a block diagram of a presently
preferred buffer useful in the practice of the
15 invention,
Fig. 5 it a schematic circuit diagram
illustrating apparatus according to the invention, and
Fig. 6 is a presently preferred response
curve for the circuit of Fig, 5.
20 Description Relative to the Prior Art
Time base distortion occurs whenever a
signal, or portion thereof, occurs too early or too
late relative to reference time frame. In a
multi-channel longitudinal recorder, a multi-channel
25 recording head it used to record information signals
along a plurality of tracks on a recording medium
such a magnetic tape. The recorded signals are
played back by means of a multi-channel playback
head. If the recording and playback heads are
30 perfectly aligned, and if the transport system that
advances the recording medium does 80 at a perfectly
uniform jolliest, the played back signals will
represent a faithful reproduction of the originally
I
I
recorded information signals. Practical systems,
however, are not so perfect.
A conventional multi-channel magnetic
(recording or playback) head ha a stack of aligned
transducer gaps. The alignment of such gaps con-
statutes a "gap fine". The recording and playback
heads ore perfectly aligned when their respective gap
lines have the same azimuthal angle (e.g. 90 degrees
with respect to the direction of tape advancement (in
the same plane). For various reasons however, the
recording and playback heads in practical system are
often not perfectly aligned. Such misalignment has
the effect of producing time base distortion in the
form of rel~tlve phase errors among the played back
information signals.
Time base distortion can also be caused in a
magnetic recorder by the tape transport system.
Specifically, as the tape advances (during recording
or playback) it may yaw about an axis perpendicular
to the plane of its recording surface 9 thereby intro-
during lime base distortion in the form of relative
phase errors similar to those produced by head mist
alignment. In this case, however, the "misalignment"
varies with the tape yaw as a function of time.
Problem
In connection with the multi-channel
processing of digital information -whether within a
recorder or notate is essential that the bits (which
are processed in respective channels) owe each given
30 byte be of the same time frame. The present invent
Sheehan as will be evident below, concerns time base
correction of digital signals; and, to facilitate
understanding of the problem solved by means of the
invention, the invention is perhaps best perceived as
so
involving magnetic tape recorder apparatus. As
digital bit rates reach astronomical levels, e.g.
gigabit per secondhand us the packing density of
digital information which may be recorded, e.g. about
4.5 million bits per square centimeter or more, on
magnetic media reaches a level which boggles the
mind the need for some means to keep the associated
bits of each given byte In the same time frame
heightens. All sorts of time bate instabilities are
possible: the bits of a byte may statically or
dynamically skew one worry a different warily-
toe to each other; and/or such bits may haphazardly
gain or lose time position relative to each other.
Consider for example, the representative showings of
Fig. 1: Between times to and if, the bits of a
certain byte are skewed one way, as might have been
caused by a clockwise yawing of magnetic tape supply-
in the byte. Between times if and to, the skew
appears to be gone, but the bits are clearly not in
the same time frame this perhaps occurring as a
result ox transient electrical inter channel disturb
banes. Between times to and to, the bits again
shift time position only this time, perhaps, the
shift is associated with mechanical micro-vibration
among the cores of the playback head. Between times
to and to, the bits again appear skewed only
this time perhaps, as a result of a counterclockwise
yaw of the magnetic tape. Looking at Fig. 1, it
would appear that the bits of the byte in question
I behave like horses in a raceO~.constantly shifting
position, back and forth relative TV one another.
With this analogy in mind then, it will be for the
invention to provide in a swoons continuously
sel-adjusting "starting gavel' so that the horses
(bits) start their travel (playback processing)
together. Again see Fig. 1.
(For prior art against which the invention
may be compared, reference should be had to US.
Patent No. 4,330,846, and to the references which
were cited therein. See, also, US. Patent No.
4,3423057.~
Problem S lotion
In a multi~ch~nnel device for the processing
of digital data bytes comprised of parallel arrange-
mints of data bits, the invention calls for recogni-
lion of the fact that irrespective of skew and other
inter channel variations in the processing of such
data bits the median-occurring bit of each success
solve data byte constitutes a good representation of the time of occurrence of the byte in question. By
suitably buffering the bits of successive data bytes,
a "median clock" that is slaved to the affronted
"median-occurring" bits may be used to clock data
bytes devoid of inter-channel timing errors out of
the apparatus used for the indicated buffering
operation. In the event the flow of data bytes is
ubiquity to flutter which affect the processing of
data bytes in all of the indicated processing
channels, the median clock correspondingly varies to
provide the "advantageous effect" of precluding
inter-channel timing errors among the bits exiting
the buffering apparatus.
DETAILED DESCRIPTION Ox THE INVENTION
W to the above summary of the invention in
mind, reference should now be had to Fig. 2 which
shows a succession of bytes involving various
bit-to-~lt timing situations. In byte 1, the bits
ore skewed one way; in byte 2, they are skewed the
other way. Bytes 3 and 4 fund the bits randomly
shifted about, and byte 5 finds all of the bits in
the same time frame. In response to flutter within
the bit stream, the bits of bytes 6 7 spread out,
albeit that they again have a random distribution of
time-positions. Pursuant to the invention as out-
lined above, it will be for the invention to deter-
mine the median occurring bit within each byte, and
to era e a clock based on such determination such
clock being thereafter used in further byte-process-
in. Note in Fig. 2 the "median clock" and the fact
that such clock follows the indicated flutter.
Before addressing actual hardware for
practicing the invention, it is believed appropriate
first to describe somewhat of an overview of how
apparatus according to the invention works to bring
about time coherence among the bits of successive
bytes: Consider, wherefore, the showing of Fig. 3
which indicates the bits of a succession of bytes
flowing into respective buffer memories. The buffer
memories ore depicted as comprised of two equisized
parts apiece. As a result of time base instable-
ties, the memory parts I, to a varying extent,
dynamically fill with bits, some overflowing into
I memory parts II 3 and others not filling at all. One
buffer memory, however, has a full part I, and an
empty part II. This happenstance occurs in response
to a "median-bit condition and as will be
appreciated below, the clock produced in response
err is employed Jo close data bytes comprised of
coherent sets of data bits) out of the buffer memory
parts I. So long as the time coherence among the
bits of a given byte is such that a buffer memory
part II does not overflow the memory parts I will
continually and dynamically wake up the slack among
the bit channels. It may turn out that as time goes
by, the indicated buffer memory that has a full part
I and an empty part II gradually starts to fill its
part II (or empty its part I). As this occurs, a
different buffer memory will gradually approach the
so-called "median-bit condition", and thereby verve
to initiate clocking signals for clocking bits out of
the buffer memory parts I. The point is that 7 at any
one time, one buffer memory (comprised of parts I and
II) can have a full part I and an empty part II,
albeit that the particular buffer memory h~vlng this
condition may change depending on the inter channel
timing among the bits of the bytes which are
processed.
Given the above overview of how apparatus
according to the invention works to provide time
coherence among bits, reference should now be had to
Fig. 4 which depicts a presently preferred form of
buffer memory for implementing the invention. It
should be understood that there will be as many Fog.
4 structures as there are bits per bytes, lye. there
is one structure as in Fig. 4 for each bit channel:
Each buffer memory is comprised of a pair of
asynchronous typewrote memories 10, 12 commonly called
Fifes (firestone fortuity serial memories). Typical
of such devices are components 74LS222, available
from Texas Instruments, Inc. The two FIFOs~-which in
this case are blowout FIFOs--are connected together as
indicated, and cooperate as follows: Incoming bits
are clocked into the upstream FIFO 10 by a (bit)
clock applied to a SO (Chutney) fine. Initially,
the two FIFE are empty, and any input bit flows
through the FIFE 10 to its output Do. When a bit
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appears at the FIFO 10 output Do, the OR (Output
Ready) line the FIFO 10 goes high, clocking the
bit in question into (Do) the downstream FIFO 12.
As the downstream FIFO 12 accepts the bit, its IT
(Input Ready) line goes low to indicate that it
cannot immediately accept another bit. As soon all
the input bit enters the downstream FIFO 12, the IT
line of the FIFO 12 again goes high (this being a
flagging sign~l3 indicating willingness to accept
another data bit. This positive-going IT line of the
FIFO 12 clocks the received bit clear of the upstream
FIFO 10.
When 64 more data bits ore clocked in than
are clocked out of the downstream FIFO 12, it becomes
full. As it coops the 64~h such bit, its IT line
goes Lund stay that way so long as the down-
stream FIFO 12 is full. This cooperation between
upstream and downstream Fifes 109 12 causes data to
"stack up", waiting to be clocked out of the upstream
FIFO 10, and into the downstream FIFO 12, as soon as
space becomes available in the downstream FIFO 12.
Monitoring (14) the Swallower line between the
upstream and downstream Fifes 10, 12 serves to India
gate whether the downstream FIFO 12 it full, i.e. the
I IT line of the FIFO 12 will be low provided the down-
stream FIFO 12 is full and high if such FIFO is not
full.
With the overview of Fig. 3, and the work-
ins of the apparatus of Fig. 4 in mind, reference
should now be had to Fig. 3, as indicated, the
system depicted is (by way of example) a five-channPl
system, i.e. 5 bits per byte.
For each of the five channels in question, a
pair of FXFOs have been hooked together as
,
buffers. like character numbers being used in Figs.
4 & 5, with subscripts identifying the appropriate
bit channels. The Shift Out/Input Ready (SYRIA)
lines are connected into a digltal-to-analog
resistive summing network 16, and the analog
voltage which appears at the common connection of
five resistors 161 through corresponds to
the number of full downstream Fifes 121 through
125. In the setup of Fig. 5, a summation voltage
of about zero volts corresponds to five full down-
stream Fifes; end approximately four volts core-
spends to five empty downstream Fifes. If we were to
start with all downstream FIFE 121 through 125
empty and if we were then to fill them one by
one..Othe common resistor terminal it of the
summation network 16 would develop an analog voltage
that gradually decreased to zero in five discrete
steps 3 each such step representing the "positions" of
the five data bit streams. Four volts would repro-
sent "data off scale to the downstream side"; and zero volts would represent "data of scale to the upstream
side". In the presently preferred form of the invent
lion, operation it at the midpoint of the indicated
voltage range, viz. at a "data position" voltage of
two volts. Such a voltage represents "average data
centered in Fifes". If the peak skew of the five
data bits is less than 64 bits, the most recent
data bit of all five data streams must reside within
the Fifes. By clocking data out of the Fifes at the
average of the input clock rates i.e. by means of a
clock Comedian corresponding to the median Kit Jo
each successive byte, the data position voltage
appearing at the common resistor terminal 18 remains
constant. If the output clock average rate were to
5~3
be too high, the "data position" in the Fifes would
drift toward the downstream Fifes, and the data
position voltage at 18 would increase. Conversely,
were the output clock rate to be too low, the "data
position" would drift toward the upstream Fifes, and
the data position voltage at 18 would decrease.
The analog voltage Nat 18) representing data
position is buffered by an operational amplifier 20,
after which a second amplifier 22 serves to scale and
condition such voltage. The matter of killing will
be discussed below. After smoothing by a companies-
lion circuit 24, the output of the amplifier 22 is
applied to a voltage-controlled oscillator (YOKE) 26,
the output frequency of which increases as the data
position voltage decreases, and vice versa. The VC0
output which corresponds to the median-occurring
bits of successive baptizes then used to clock data
out of the Fifes 121 through 125. Such an
arrangement constitutes a closed loop 3 where the
fullness of the downstream Fifes 121 through 125
controls the effective output clock rate provided by
the VC0 26.
The resistive network 16 and operational
amplifier components are chosen so that the VC0 26 is
stable with two downstream Fifes 12 full, two empty,
and one full half the time. In other words, by means
of the invention, the input data gets so positioned
within the downstream Fifes that the VC0 output shift
clock corresponds with the median of the instant-
nexus input bit clock rates: for data which occurs
too feat (i.e. squadded data), the Fifes allow again up to 64 bits; for data which occurs too slow
(i.e. skewed-behind data), the Fifes allow the data
to fall buck by as much as 64 bits without any data
being lost.
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As indicated above, the data position
voltage Nat 18) is scaled (see, for example,
Electronics For Engineers, Armed and Spread bury,
Cambridge University Press 1973, page 124~ Library
of Congress Catalog Card No. 72 93138) by the
operational amplifier 22 before being applied to
control the YOKE. This scaling is preferably
nonlinear (see Fig. 6): For small changes in the
data positron voltage (at lo) about two jolt , such
voltage it applied with low grin to the VCO 26,
resulting in a relatively small median clock
frequency shift. Were however, the data position
voltage to get further from two volts representing
an increased error in data position, the gain of the
scaling amplifier 22 would increase. Attendantly,
this would cause a more drastic median clock
frequency shift a the VC0 26 attempts to keep the
Fifes from under- or over-flowing. From Fig. 6, it
is clear that, for example, for a shift of from 2 1/2
full downstream Fifes 12 to only one full downstream
FIFO, a O . 25% change in the VCO frequency occurs.
However, for still another shift to zero full down-
stream Fifes 12, this causes thy VCO frequency to
shift by 1.57~. Such non-linear response to the data
position error helps to minimize jitter of the median
clock, thereby allowing much of the input bit jitter
to be masked
The invention has been described in detail
with particular refererlce to preferred embodiDlents
thereof, but it will be understood that variations
and modifications can be effected within the spirit
and scope of the invent on For example, while t is
presently preferred that the median clock works to
keep one buffer half full/h~lf empty, within an even
~23..~3
split between the over- and under-flowing buffer
part I (Fig. 3), other ratios than a fifty-flfty
split are possible. Also, while the disclosed
multi-channel apparatus it configured to handle 5-bit
byte, apparatus with other number of channels may
be accommodated to the practice of the invention.
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