Note: Descriptions are shown in the official language in which they were submitted.
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TITLE: REAL-TIME Doria Processing SWISS FOR
PROCESSING TIME PERIOD CORDS
The present invention relates to real-time data
processing systems and is more particularly concerned with
arrangements for processing "wait-for time period" commands.
In real-time data processing systems used to control
for example teleco~nunication switching systems or the like
it is often necessary to suspend a process for a specified
time period. For example during call set-up the dialed
digit registration process could be suspended after the
reception of each digit for a predetermined period (such
as the inter-digital pause). Such an operation is achieved
by executing a wait-for time period command or microinstruction
in which the command itself specifies the time delay. Many
other instances of "wait-for time period" macro instructions
can be envisaged and in a large exchange system using a
multiprocessor stored program control the number of
suspended processes experienced at any one time can be quite
substantial.
It is an aim of the present invention to arrange all
the "wait-for time period" commands into an
ordered list and to arrange for the data processing system
to administer this list so that the process suspended can be
restarted when the wait-for time period matures.
According to the invention there is provided a real-time
digital data processing system of the type handling processes
which include "wait-for time period" commands, each said
command specifying one of a plurality of predetermined time
periods and all processes whip are suspended by commands
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.
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having the same particular time period are chained to each
other in the chronological order in which they are suspended
and to a timing chain header which holds information on the
real-time t which the wait-for time period of the first
process in the chain will mature and all the timing chain
headers are linked in list and the system includes a process
for searching the list when a predetermined time interval
has elapsed to ascertain the process or processes whose
wait-for time period has matured.
Also according to the invention there is provided a
real-time digital data processing system of the type
handling a plurality of processes which include 'Iwait-for
tome period" commands, each said command specifying one of
a plurality of predetermined time periods, the system including
1.5 a memory, for storing information relevant to the processes,
and at least one processor unit arranged to perform the
processes and each process is provided with an information
--segment in the memory for holding worming parameters for the
process when the process is suspended and the information
segment includes an indication of the time when the wait-for
time period is due to mature for that process and
information segment linking information which forms the
information segments, of all the processes which are suspended
by commands having the same particular time period, into a
first linked list arranged in the chronological order in
which the processes are suspended and the first linked list
is also linked to a timing chain header segment stored in
28 the memory and exclusively allocated to the said particular
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time period, the timing chain header segment storing a wake-up
value indicative of the time when the wait-for time period for
the first information segment on the first linked list will
mature and each timing chain header includes header linking
information forming the timing chain header segments into a
second list anc7 the system includes a timing chain search process
which causes the second list to be searched to ascertain the
process or processes whose wait-for time periods have matured and
isle system also includes means for activating interval timing
arrangement conditioned to monitor a time interval and on
completion of the interval to activate the timing chain search
process.
In accordance with the present invention, there is provided
a system for controlling the execution of a plurality of
suspended processes in a real-time data processing system, said
processes being suspended for predetermined time periods upon the
data processing system executing a sub-routine, and encountering
a wait-for time period command, each said command specifying one
of a plurality of predetermined time periods, the system
including a memory for storing information relevant to the
processes, and at least one processor unit arranged to perform
the processes, an information segment in said memory for holding
working parameters for each process when the process is
suspended, each information segment including (i) an indication
of the time when the wait-for time period is due to mature for
that process, and (ii) information segment linking information to
form the information segments of all the processes which are
suspended by commands havislg the same particular time period into
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a first linked list arranged in chronological order, a timing
chain header segment in said memory exclusively allocated to the
said particular time period, the first linked list being also
linked to said timing chain header segment stored in said timing
chain header segment, said timing chain header segment storing a
wake-up value indicative of the time when the wait-for time
period for the first information segment on the first linked list
will mature, and each tilnillg chain header segment including
header linking information forming all said timing chain header
segments into a second linked list, said memory also including a
ready to run file having one entry for each process which is
ready to be run by the processor unit, said system having means
to implement a timing chain search procedure which is arranged to
be run when the real-time reaches a predetermined value, said
timing chain search means includes
(a) means for reading the wake-up values in each of the
timing chain header segments,
(b) means for comparing the wake-up values read with the
time at which the timing chain search procedure is run,
(c) means for placing those processes having wake-up values
which equate to the time at which the timing chain search
procedure is run on the ready to run file,
(d) means for removing those processes having wake-up values
which equate to the time at which the timing chain search
procedure is run from the first linked lists, and adjusting the
wakeup values in the relevant timing chain header segments, and
(e) means for reading the wake-up values of each timing
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chain header segment and selecting the smallest wake-up value to
provide the next predetermined value.
The invention will now be described with reference to
the accompanying drawings in which
Figs. lo and lb which should be placed side by side with
Fig. lo on the left show a block diagram of a central processing
unit suitable for use in one embodiment of the invention.
Fig. 2 shows the reglste~s incorporated in -the CPU of
jigs. lo and lb.
Fig. 3 shows the store protection (capability) registers
incorporated in the CPU of Figs. lo and lb.
Fig. 4 shows a process dump stack.
Fig. S shows a process base.
Fig. 6 shows the scheduler's running list.
Fig 7 shows a timing chain according to the invention.
Fig. 8 shows how timing chain headers are linked.
Fig. 9 shows a flow diagram of a processes suspension
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algorithm, whereas,
Fig. 10 shows flow diagram of a so-called "usherette"
process.
before embarking on a detailed description of the
arrangements of the invention, opportunity will be token to
review briefly a central processor unit which would be
suitable for use in the data processing system of the
invention. Such a central processing unit is shown in
Figs. lo and lb which should be placed side by side with
Fig. lo on the left the central processing unit is
connected to a storage module over leads SIOUX, SDH, SIOUX
and SIX. reads SDH and SIX being the output and input data
paths respectively of the storage module whereas leads
SIOUX and SIOUX are the output and input control signal5 highways respectively for the storage module.
the central processing unit is microprogram controlled
PRIG which exercises control over data transfer gates
allowing the passage of a data on and off the highways of
the unit The unit comprises an arithmetic unit MILL, a
comparator COUP, an instruction register IRK an operand
register OPREG, a store communication register SDIREG and
three register stacks. the unit is organized on the so- Al
called capability register structure which is disclosed in
detail in Specification No. 1,329,721. the stacks provide
general purpose register storage ARC STY (shown in detail
in jig. 2) and capability register storage divided into
base ASSAY SINK and limit I IMP SKYE stacks and these are
28 shown in detail on Fig. 3. the central processor is
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particularly suitable for use in modular processing systems
of -the type discussed in "System 250 - a fau]t-tolerant,
modular processing system for control applications" pages
26 to 34 of issue 27 of Systems technology. In such
systems the capability structure is arranged such that a
master list of all resources is held in a so-called system
capability table and each process is provided with a list
of pointers to that table indicative of the resources to
which the process is to be permitted access. In addition
each process is provided with a so-called dump stack (shown
in Fig. 4) held in the common memory which is pointed to by
the dump stuck capability register DCR of the capability
register stack in the processor unit executing that process.
the dump stack DA is used to store the contents of the
general purposes register stack ARC So when a change
process occurs (i.e. when the process is suspended) together
with the value of sequence control register SIR and all the
working capability registers RIP WICKER to RIP WICKER. In
addition each process dump stack DA includes a RIGHT WINK
a IFFY and an INCREMENT value and these values will be
used later in operations required to perform the embodiment
ox the invention.
Each process is provided with a so-called process base
(Fig. 5) PUB Lucia is a list of primary pointers, including
one to the process dump stack WEDS, a job link block JIB,
a trap flag WIFELY, a scheduler work space link WINK and a
work space holding a list ox` Post and wait-for flags.
28 the operations performed by the multi-processor system
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of System ~50 are organized by a scheduler process which
operates on a running list. this list is shown in Fig. 6
and it consists of three blocks of information having one
entry for each processor unit in the system. Fig. 6 shows
a running list arrangement for a three processor unit
system and the list includes for each processor (i) a
pointer to -the process base for the process running on a
processor, (ii) a pointer to the dump stack for each
running process and (iii) a pointer to the dump stack for
the process previously running on the processor unit.
Each processor has its own current time block and this
block is addressed by a time capability register CRY (Fig. 3).
The block pointed to by CRY consists of three words labeled
WIT, WISP and WINNIE. WIT is the interval timer, WAGE
Jo 15 is the estimated time at which the next timer interrupt
will occur and WISP is used to record the interval timer
value when one processor interrupts another.
Timing information for WAFER timing periods, is
I, based on a notional supervisor "current time". In fact,
there is no single value; instead, each processor maintains
its own version, and external system control arrangements
(not shown) are made to keep the processors in reasonable
synchronism.
Each version of current time is maintained as follows.
I've word labeled WINNIE is used to hold the estimated real-
time at which the next timer interrupt will occur, i.e. the
real-time at which WIT will become zero. Current time is
28 given by I = WINNIE - WIT. Whenever WIT is updated at the
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end of a time interval to start a new internal time-out,
EIGHTEEN is naturally altered by the same amount. The value
WIT is set-up by an interval timer process to a value
indicative of the number of loo u second periods which
are to elapse before the interval timer process is to be
reactivated. Mach processor in the system is arranged to
be interrupted at 100 second intervals and -the interval
timer word WIT is decrement Ed by one and tested for a zero
condition. When a zero condition is encountered the
interval time-out is complete and reentry into the process
waiting for the interval to mature is made.
The actual interval timer process used in this
embodiment of the invention is a so-called "usherette" process
which will be considered in detail later.
Each I is normally an increasing value, but there are
two possible exceptions to this:-
` (a) When any time value is about to overflow the capacity
of one word, all the time values are reduced by a
fixed amount (typically 3 minutes).
(b) The Us may be subject to minor corrections when
synchronization is performed.
The use of the word labeled WIT SUP is two-fold. When
one processor wishes to interrupt another, it sets the
latter's WIT to zero, (unless it is already zero or negative).
The previous value is WIT SUP so that the original interval
to be timed can later be reestablished. WIT SUP is also
used to Ashley single-threading of operations on the bleakly:
28 the value -1 indicates that the block is "locked".
i
Sty
In the system according to the invention, a process can sup-
pond for an interval of time which it specifies itself using the
"wait-for time period" commands may also be made conditional upon
the occurrence of an external event. For example, in a telephone
environment a "wait-for time period" command could be used to
control the exchange control algorithm in the handling of dialed
digits. In this case, the process handling the reception of dialed
digits will be suspended by a "wait-for time period" command which
is also dependent upon the reception of the next Doyle digit.
If the dialed digit arrives before the time period expires, then
the suspended process is awakened, and this is accommodated in
the embodiment of the invention by entering the flow diagram of
Fig. 10 at point I . The interval can take any integer value
from one up to a fixed maximum value, and no limit is placed on the
number of processes which can be simultaneously suspended.
the data structure used to implement the facility j
has been designed to be efficient for application in which
(i) the number of processes simultaneously suspended can
be very large and (ii) the number of different time
intervals in force at any instant is relatively small. In
a practical example thirty is considered to be a reasonable
number, however, it is arranged for a given interval to be
in force for a large number of processes which request it
at different times, and which therefore, need to be "woken-up"
at different times.
Sue
~11 the processes which are suspended waiting for the
expire of the same time interval are chained to each other
in the order in which they made their request and to a
-"timing chain header". The chaining is achieved by means
of the ROUGE LINK (AL) and LEFT LINK (LO) pointers in the
process dump stacks as shown in Fig. 7. As Fig. 7 shows
a chain is formed which is doubly circularly linked. In
the- example given three processes, having dump stacks 1, 2
and 3 respectively have "asked" to be suspended for an
interval of 15 milliseconds. The fifteen value is
multiplied by ten to convert it to units of 100 u seconds
as the system is arranged to have 100 u seconds processing
slots. The achieved value of 150 is written into the interval
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,
IT location in the TIMING CHAIN EIDER. considering now
the example chain shown in jig. 6 the first process in the
chain is due to be woven up at time 1270 and this is
written into the WAKE UP location in the header. The dump
stack of the first process in the chain has a zero value
written into its increment location INC. the second
process in the chain requires to be reenacted at time 1270
, plus 20 (i.e. at time 1290) while process 3 should be
¦ reenacted after a further increment of 10 (i.e. at time
1300). the increment value IN for the first process in the
chain is always zero and the value NEGSUM in the header
is maintained as a signed twenty-two bit number which is the
negative sum of the increments of the chain. The I~EGS~M
is computed by negating the sum of the increments and
subtracting one. Hence in the example chosen the EXHUME
becomes -31 from the increments of 20 and 10. this value
is of significance when adding a process to the end of a
¦ chain since it enables the ICKY value for the new process to
, be determined without traversing the entire chain.
jig. 7 shows the way in which the process dump stacks
for processes are chained for processes which are suspended
for a particular timing period (i.e. 15 milliseconds).
In any multi-processor system handling real-time processes,
such as are found in the telecommunications art, there will
be process suspended for differing intervals. Such a
` situation is handled by having several timing chains each
with a timing chain header.
28 the headers are then linked as shown in jig. 8 using the
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.
down link WIDELY of the header shown in jig. 7. the head
of the header chain is a timing chain master pointer block
- having a pointer IRIS HEADER to the head of the timing chain
header list. The timing chain headers are not arranged in
any particlilar order. When an individual timing chain
becomes empty (i.e. there are no longer any processes on it)
the header is said to be "free" and can be reused for a
different interval if required. the pointer ROY in the
timing chain master pointer block is used to contain a
pointer to a free header and this pointer is set to NULL. if
no free headers are available.
the timing chain scheme described above involves three
j major operations in its administration.
¦ Al. A process suspends execution until a specified time
¦--- 15 interval has elapsed (i.e. performs a WAIT FOR time
interval instruction) or possibly until some external
event (i.e. Flag) occurs, whichever is the sooner.
the process has therefore to link itself to an
appropriate timing chain.
2. A process in a timing chain is to be removed from
the chain because of the occurrence of an external
event.
3. A prowess in a timing chain is removed from the
chain because its time interval has matured.
the first operation is shown in flow diagram form in
jig. 9 whereas a special process, called the "usherette"
process is responsible searching the timing chain headers
28 for handling the third operation and this is shown in jig. 10.
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.
the second operation is handled using some of the steps
of jig. 10.
Consideration will firstly be given to the operations
necessary to suspend a process, in other words place a
process on a timing chain.
PROCESS SUSPENSION
-
As mentioned previously jig. 9 shows -the flow diagram
of the operations performed when a WORRY time period
microinstruction is encountered. the processor unit
encountering that instruction will set up, in one of its
capability registers, the descriptor (i.e. base and limit
value together with the access type code) for the master
pointer block (jig. 8). the processor unit will then perform
step Pal which addresses the ROY location in the master
1 15 pointer block, using the MILL to form the actual required
! store address in the register SDIREG and addressing the
storage module in which the block resides over leads SIX
in jigs. lo and lb. the contents of the addressed location
are returned on leads SDH into say one of the general purpose
registers in ARC SKYE. the processor then performs step PS2
of Fig. 9 where the contents of that register will be tested
by the MIX using the arithmetic unit condition signals AXIS.
It will ye appreciated by those skilled in the art
that all the process operational steps in jigs. 9 and 10 can
be arrange to be executed using the equipment of jigs. lo and
lb using normal data processing operations and accordingly
no detailed' break-down of the rest of the operation step
28 will be attempted in the rest of this specification.
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sup PS3
In this step, which is entered because no free timing
header was identified by the ROY location of the master
pointer block, the list of -timing chain headers is scanned
using the down link WINK (Fig. 8) of each timing chain
header testing each header to see if it is free. If one is
found the pointer FREE in the master pointer block is
conditioned to point to that header. If no such free header
is found a new store block is obtained from a pool administered
by a store manager process and this new block is initialized
as a timing chain header and it is added to the end of the
timing chain header list.
P PS4
I
This step involves the setting of a value X into a
1, general purpose register in the processor unit. the value
X is calculated by adding the WAIT-FOR time interval (I)
to the current system time. the value X will be used later
to condition the WAKE UP value or the increment value for
the process.
SUP PS5
In this step the timing chain header list (Fig. 8) is
scanned looking for a header having an interval time (IN .,
jig. 7) equal to the requisite wait-for time (I). If a
timing chain involving the wait-for time exists Step PS6
-~~~ 25 will be completed on the y path whereas if no timing chain
already exists path n -will be followed.
STEP PS7
28 In this step the increment (IN? for the process dump
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stack is formed by subtracting a value formed from WAKE UP
minus NEGSUM minus one (for the timing chain header identified
in Step PS6) from the value X formed in step PS4. this
step also causes the NEGSUM in the selected timing chain
header to be updated by subtracting tune new formed increment
for the new process.
SUP PS8
Upon the completion of step PS7 it is necessary to
insert the process into the selected timing chain and this
is performed by identifying the last process in tile chain
by reading the IOTA WINK NO WINK slot in the header It
should be noted that if the chain is empty, the "last process"
will be the header itself. Having identified the last
process in the list the links between this last process and
the header are broken and reformed incorporating the new
process as the last process in the chain. The value X
is also used in this step to ensure that the usherette
process is woven up at or before time X. Upon completion
of this operation the suspend process process is completed
and the processor unit executing the suspend process process
would now enter the process scheduler.
STEP PS9 I',
_
If no timing chain exists having an interval equal to
the wait for time of the newly suspended process step PS6
Jo 25 will be ended on -the n path. Steps PS9, 10 and 11 are
I- performed in this case to take a new timing chain header
into use and to set up the WOE U?, IN and NEGSUM values
28 (jig. 9) as well as removing that header from the TREE
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pointer of the master pointer block (Fig. I).
prom the above it can be seen that to suspend a process
for a defined period the process dump stack is added to the
end of a chain of such process dump stacks all waiting on
the same interval equal to the defined period. The
administration of that timing chain is achieved by the
WAKE UP, RIGHT LIT EAT LINK and NEGSUM values of the
timing chain header
Once a process is suspended by the WAIT FOR time period
macro it will remain on the timing chain until (a) the
required interval matures, or (b) it is removed by the
occurrence of some external event. Both of these operations
are achieved in the flow diagram of jig. 10 which is a
swilled USHERETTE Process and they will be described in
the order defined above.
USHERETTE PROCESS
this process is scheduled under the control of an
interval timer arrangement in a processor unit which is
conditioned to mature and cause entry into the Usherette
I, I
1 20 Process at or before the time at which the shortest timing¦ chain wake-up value is to mature. The way in which the
shortest value is identified is defined in the following
process. Basically the usherette process is used as a
timing chain search process to ascertain the process or
processes whose wait-for time periods have matured.
SUP Up
In -this step a general purpose register in the
28 processor executing the Usherette Process is used to store
.
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the value TIME for the process and this register is set to
current system time.
STOP UP
A second general purpose register in the processor is
used to store the value NEXT Tao and the contents of that
register in this step are set to a very large value, I
say all ones ;
STEP UP
The processor now inspects the first header in the
chain. This is achieved by using the FIRST HEADER Pointer
(jig. 8). The operations performed in this step involves
the reading of FIRST VADER into a timing chain list pointer
(CLUE POINTER) which again is one of the general purpose
registers of the processor.
I STEP UP
In this step the TCL POINTER is used to read the WAKE
UP value (see jig. 7) of the first timing chain header ox
the chain.
STEP UP
,,
the processor unit now compares the WAKE UP value just
read with the value TIME. Typically one of the two values
held in separate registers in the processor may be subtracted
from the other by the MILL and the result monitored. If
WAKE UP TIME steps UP etc. are performed to step onto
Jo 25 the next header in the chain as the wake-up time for the
first header is greater than the current system time.
If the result of the comparison I the step indicates that
28 TIME is equal to (or greater than) WAKE-UP then steps Pull
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etc. are performed to extract the first process on the first
timing chain and to place it on the "ready to run list".
It will be assumed at this stage -that the first header's
WAKE UP is greater than TIME.
SUP UP
In this step WAKE UP is compared with EN IAMB and if
WAKE UP is less than EN TIME step UP is performed. In
the situation assumed NEXT TIME has been set in step UP to
a very large value and hence step UP will be performed.
lo SUP UP
In this step EN TIME will be overwritten by the WAKE UP
value read from the header addressed in step UP. this
operation controls the search "down" the timing chain
headers setting EN TIME to the lowest value encountered
until of course the NEXT TIME encountered equals the current
system time given by TIME.
SO P UP
The down link WEDLOCK (Figs. 7 and 8) in the header
addressed in step UP is read in this step into one of the
general purpose registers of the processor.
REP UP
In this step the down link is tested to see if it is
NULL indicating the end of the chain. It will be assumed
that the down link is not NULL. It should be pointed out,
however, that such a situation could occur because a process
could be placed on a timing chain awaiting a time out or
an external everlt arid if the external event occurs before
28 the time out the process will be removed from the chain and
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the Usherette process could therefore have been woken-up to
respond to that time-out. The operations necessary to remove
a process from a timing chain are related to steps Pull to
UP18 inclusive and will be discussed later.
STEP Up_
In this step the down link WOODY read in step UP
will be written into the general purpose register used as
the timing chain list pointer TCL POINTER to allow steps
,
UP and UP to be performed again using the WAKE UP value
from the next header in the chain. Steps UP to UP LO will
be performed in a repeated manner until the header having
a WAKE UP value which equates to TIME is found or the
complete header chain has been traversed. When the condition
WAKE UP equals TIME in step UP is found step Pull is
performed which starts the chain of steps which remove -the
suspended process from the timing chain as its wake-up
period has matured
So
In this step the right link R WINK (jig. 7) of the
timing chain header of the timing list having a WAKE UP
value equal to the current system time is read into one of
the processor s general purpose registers. This operation I!
identifies the first process dump stack on the timing chain '
served by the header.
Jo STEP UP12
_
In this step the right link read in step Pull is 'i
tested to see if the chain is empty. Again such a situation
28 could occur if the timing chain contained a dump stack .
.~, ., . I= .
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- 19 -
waiting for a time out or the occurrence of an external event and the latter had occurred causing the removal of
the process from the timing chain before the WOE UP for
the particular timing chain matured. It will be assumed that
the timing chain "entered" in steps TJp5 and UP11 has a
process dump stack waiting to be processed at this point in
; time
REP UP13
! - In this step a general purpose register defined in the
10 flow diagram of Fig. 10 as X is used to read the increment
value of the right hand neighbor of the timing chain.
STEP UP14
In this step the increment value INN) of the right hand
neighbor ox the timing chain is set to zero as this process
is about to become the first process in the chain since the
current first process is to be placed on the read to run
list.
'I Skip UP15
In this step the X value is used to adjust the WAKE UP
and NEGSUM values in the timing chain header to accommodate
the removal of the reactivated process.
! STEP UP16
_ .
In this step the right (lo WINK) and left (No WINK)
links in the timing chain header are reformed to point now
to what was process 2 in the chain as previously constituted.
Skip UP17
qlhe processor unit now causes the process, which was
28 identified in steps UP to UP12 as being ready to be wo~en-up,
" . ._ .
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to be placed onto the schedulers "ready to run" list.
the usherette process will then execute steps UP, UP,
- UP LO, IJP4 and IJP5 searching for any other process which
should be woken-up at the current system time given by TIME.
Ultimately step UP will encounter the then end of the
header chain and step UPl9 will be performed.
SUP UPl9
In this step the final value of NEXT TIME, which will
-- be the lowest WAKE UP value encountered while interrogating
lo the headers which did not equate to the current system time,
will be written into the HARDWARE TIMER system to cause the
Usherette Process to be reactivated at that time. the
Usherette Process then suspends itself waiting for the
current system time to reach the HARDWARE TIMER value
using the interval timer arrangement of one of the processors.
Jo remove a process from a timing chain it is simply
necessary to perform steps Pull, UPl2, UPl3, Pull UPl5,
UPl6 and UPl7. Point ox in jig. lo indicates the point of
entry into the Usherette Process which is "forced" by -the
occurrence of the particular external event
the timing chain scheme described above has several
advantages over other prior art schemes. typical of these
advantages are:
l. The addition of a new process to a chain is always
I-- 25 at the end, and is an easy operation due to the
chaining and the NEGSUM value. traversal of the
entire chain is no-t necessary, and so the operation
28 is efficient no matter how long the chain is.
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2. Removal of a process from any part of the chain
is an easy and efficient operation not requiring
traversal of the chain.
. If, as in real time system, absolute time values
must occasionally be adjusted so that overflow does
not occur, it is only necessary to visit each header
and adjust one value (WAKE UP) in it. The time values
in the individual process dump stacks are relative and
do not need to be adjusted.
4. the set of INTERVAL values can easily be adapted to
suit the needs of the moment because when an individual
chain becomes empty (i.e. there are no more processes
on it) the header is said to be "free" and can be
I reused for a different IM~RVA~.
.
r 'IT'.' p'-
