Note: Descriptions are shown in the official language in which they were submitted.
CMOS LSI AN~ VLSI CHIPS HAVING INTE~NAL
DELAY TESTING CAPABILITY
BACKGROUND OF THE INVENTION
This invention relates to large scale integration (LSI) circuit
chips and very large scale integration (VLSI) circuit chips, and more
particularly to LSI and VLSI circuit chips using complementary metal
oxide semiconductor (CMOS) logic circuitry. Still more particularly,
the present invention relates to CMOS LSI and VLSI circuit chips
including a special set of integral test circuitry which, in addition
to being used to functionally test the chip, is used to test the
electrical delay of the circuits on the chip prior to packaging in an
integrated circuit package.
Integrated circuit chips are formed on a wafer. A wafer is a
thin slice of pure silicon, typically four inches in diameter for LSI
and VLSI circuits, on which an array of chips are fabricated. The
wafer is scribed, along the unused channels between the chips, and
the chips are broken off from the wafer. They are then packaged in
an integrated circuit package for testing and, if they pass testing,
for use.
The percentage of properly operating chips on a wafer, i.e., the
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yield, is often very low. In LSI and VLSI technology, the yield can
be as low as 10 percent because of the complexities involved in the
fabrication process. Since the packaging of a chip adds considerably
to its manufacturing cost, it is desirable to fully test chips when
they are still part of the wafer to avoid the expense of packaging
defective chips.
There are typically three types of tests that are required to
fully test an integrated circuit: ~1) functional tests show whether
all the circuits function as required; (2) parametric tests show that
the input and output circuits of the chip have the correct electrical
characteristics; and ~3) delay tests show that the circuits perform
with the necessary speed. This invention provides a means of easily
performing the third test while the CMOS LSI or VLSI chip is still
part of the wafer.
Delay testing of CMOS LSI or VLSI chips has not heretofore been
possible for the reasons set forth below. However, it will be
helpful to understand the advantages of the present invention to
review the evolution of delay testing as it relates to non-LSI or
-VLSI integrated circuit technology.
Testing chips when they are part of the wafer requires a method
of getting signals into, and reading signals from, the chip's
input/output (I/O) pads. Probe mechanisms have been developed to
satisfy this need. A probe is a mechanical arm, electrically
conductive, with a fine point on one end to make electrical contact
with an I/O pad; the other end of the probe being wired to the tester
electronics. Probe systems have been fabricated that have as many
probes as the number of I/O pads on the chip
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being tested. The contact ends of the probes are arranged in the
same pattern as the I/O pads such that when the chip is aligned under
the probes, an electrical signal from the tester causes the probe
points to lower and make contact with the I/O pads.
When contact is made with all the I/O pads, test patterns can be
applied to the input pads and a clock signal, if necessary, is
generated by the tester and sent to the appropriate input pad. The
response of the circuitry on the chip to the input signals can then
be read by the tester through the probes connected to the output
pads. The tester can compare the output pattern read from the chip
to the pattern that is expected, based upon the input pattern, and
determine if the chip is functioning correctly. Thus, the probe
system satisfies the functional test requirement of testing chips
while still part of the wafer.
The probe system is also used for delay measurements by the use
of special test chips. These test chips are placed at strategic
locations within the array of desired functional chips, thereby using
up space on the wafer that could otherhwise be used for additional
functional chips. The test chips have a small number of I/O pads and
the delay test is performed using a probe mechanism that is different
from that used for functional test of the other chips. Because of
the small number of I/O pads on the test chip, the probe arms on the
delay tester can be made very small. Therefore, the inductance of
the probe arms does no~ affect the delay test results. Since each
test chip displaces a potentially usable functional chip, only a
small number of test chips are used on each wafer.
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The results of delay testing test chips (which results may vary
by as much as 25 percent) can be used to reject an entire wafer.
However, even if the delay test results do not cause wafer rejection,
all the functional chips that passed functional test must still be
delay tested after being individually packaged. As explained below,
as the density of integrated circuit technology increased, the use of
these test chips became impractical.
In khe early 1970's, wafers were typically 2-inches in diameter
and the line widths (the minimum dimension~ on a chip were typically
7-microns. The mask (a different mask is required for each step in
the wafer fabrication process) was typically 1:1 size and was used to
expose the resist on the wafer using a contact printing process. The
mask was generated using a reticle, which was the pattern for one
layer of one chip. The original layout was made using manual or
automated techniques and was usually much larger than actual size;
typically 100:1 to 500:1. This was reduced, using photographic
reduction methods, to the reticle which was typically a 10:1 size.
The reticle was then inserted into a step-and-repeat camera which
reduced it to a 1:1 size, as it exposed the pattern on the mask. The
mask locations that were to have the test chip pattern were skipped.
When all of the chip patterns were exposed on the mask, the test chip
reticle was inserted in the step-and-repeat camera and the camera
exposed the test chip pattern in the blank locations.
By the mid-1970's, wafers were typically 3-inches in diameter and
line widths on a chip were typically 4-microns. The mask was
generated at a 1:1 size, including the test chips, by electron-beam
systems, and exposed on the wafer by a 1:1 projection alignment
system.
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By 1980, wafers were typically 4-inches in diameter and line
widths on a chip were typically 2-microns. The projection alignment
system was no longer adequate for the accuracy required. Because of
the small dimensions involved, reticles were generated at 10:1 size
using an electron beam system. Masks were not used; rather the
reticle was exposed on the wafer resist using a direct step on wafer
(DSW) system. The DSW system did not allow the replacement of the
chip reticle with a test chip reticle because of the very fine
tolerances involved in making the exposure. Thus, by the time VLSI
technology had e~erged, test chips were no longer practical.
Performing delay tests on a normal chip in LSI and VLSI
technology has not heretofore been practical for two major reasons:
(1) circuit delays decreased; and (2) the number of I/0 pads
increased as LSI and VLSI technology developed.
The decrease in circuit delays means that the time between the
application of the input pulses and the detection of the output pulse
becomes smallPr, dictating a more precise measurement of the time
involved if the answers are to be meaningful. As the circuit density
of the chip and the number of I/0 pads increased, the size of the
chip did not ~ncrease in the same proportion. In fact, as the number
of I/0 pads on a chip increased, they had to be made smaller and
closer together.
The end of the probe arm which is wired to the tester is much
wider than the ~ontact end. Therefore, the row of probe arms along
each side of a chip form a "fan", narrow at the probe end and wide at
the end wired to the tester. Since a chip is typically square, with
I/0 pads and probe
l~i93t~
arms along each side, as the number of I/O pads increased, the length
of the probe arm has to increase because the four "fans" get wider at
the tester end of the probe arm. This increased probe length adds
significant inductance to the test circuits used for delay testing.
As mentioned above, the decreased circuit delays inherent to LSI
and VLSI technology require more precise measurement when performing
delay tests. This means that the rise and fall times of the signals
generated and measured must be small compared to the delay being
measured. Further, the switching point of the output signal, with
respect to the switching point of the input signa~, must be measured
more accurately. However, the inductance of the longer probe
distorts the signals used for the delay test, lenthening the
otherwise fast rise or fall times. Thus, even though a delay can be
measured, the time between the switchings of the first input circuit
and last output circuit can not be determined with enough accuracy to
make a go/no-go decision. Therefore, LSI and VLSI chips, while still
part of the wafer, are functionally tested, but accurate delay
testing must still be done after the chip is packaged in an
integrated circuit package.
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S~MARY OF THE INVE_TION
The present invention addresses the problem of how to delay test
CMOS LSI and VLSI chips while they are still part of the wafer. By
so doing, the expense of packaging chips which may not meet the delay
requirements is avoided. The invention accomplishes this solution by
taking advantage of two characteristics of CMOS technology explained
in the following two paragraphs.
The CMOS LSI and VLSI circuit technology is inherently intolerant
of process defec~s, while quite tolerant of process variations.
Because of the fine geometries involved, a defect, such as a mask
with too poor line resolution or a pin-hole in the resist, usually
results in a catastrophic failure. That is, the circuit fabricated
with the defect typically will not function and is detected at
functional test when the chip i9 still part of the wafer. Process
variations such as doping level, temperature, diffusion time, etc.,
usually yield circuits that will function but may be too slow for the
intended use. Functional test, being a steady state test, typically
will not detect delay fault~ caused by process variations.
Another characteristic of CMOS LSI and VLSI circuit technology is
that if process variations affect circuit delays, then over a single
chip on a wafer, all circuits will be affected in approximately the
same way. Therefore, if a single meaningful delay measurement can be
made on a CMOS LSI or VLSI chip, while it is still part of the wafer,
a high confidence level decision may be made about the delays of all
the circuits on that chip. The present invention allows such a delay
test to be made.
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The present objective of the invention is accomplished
by using a CMOS LSI or VLSI integrated circuit having integral
test circuitry consisting of a shift register around the periph-
ery of the chip. The shift register has a stage, or storage lo-
cation, physically corresponding to each of the I/O pads of the
chip. The shift register is normally used by the tester to func-
tionally test the chip.
Additional circuitry is used to gate a signal from the
tester, with one inversion, into the shift register. All stages
of the shift register are held open so that the signal passes
through the shift register and appears at the output. When the
shift register is used in this manner, it is called a ring oscil-
lator. Each stage of the ring oscillator causes a double inver-
sion of the signal so the signal that appears at the output, be-
cause of the single inversion of the additional circuitry, is the
inversion of what the tester originally sent. The additional
circuitry gates this output signal back to the tester for detec-
tion, as well as to the inverter to circulate through the ring
oscillator again. The transit time of the signal through all the
stages of the ring oscillator is a measure of the delay of the
circuits on the chip.
Thus, in accordance with a broad aspect of the invention,
there is provided an integrated circuit having integral delay
testing capability comprising:
an integrated circuit circuit chip having internal functional
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- 8a -
circuitry thereon;
a shift register circuit formed on said chip, said shift
register circuit comprising a plurality of shift register stages
connected in series, each stage being adapted to selectively
allow data signals to pass directly therethrough;
a control circuit formed on said chip for controlling the
operation of said shift register circuit;
means for selectively configuring said shift register cir-
cuit as a ring oscillator in response to control signals generated
by said control circuit; said ring oscillator having a period of
oscillation that is approximately two times the time it takes a
data signal to propogate through said shift register circuit;
a plurality of input/output pads located near the periphery
of said chip for providing input and output connections to said
internal functional circuitry and said control circuit, one of
said pads being an input pad through which a data signal may be
directed towards said shift register circuit~ a.nd another of said
pads being an output pad through which a data signal may be re-
ceived from said shift register circuit;
whereby a time measurement may be made of the time it takes
a data signal to propagate through said shift register circuit;
which time measurement can be related to the delay times associat-
ed with the operation of said internal functional circuit.
In accordance with another broad aspect of the invention,
there is provided a method of performing delay testing of CMOS
8b -
LSI or VLSI integrated circuits comprising the steps of:
(a) realizing a shift register circuit having a large number
of serially connected stages as part of the LSI/VLSI CMOS cir-
cuitry;
(b) realizing a shift register control circuit as part of
the LSI/VLSI CMOS circuitry that controls -the operation of said
shift register circuit and allows the shift register circuit to
operate in at least one of two modes, a first mode of which per-
mits data signals to be controllably clocked through the shift
register stages, and a second mode of which allows the shift reg-
ister to operate as a ring oscillator and permits data signals to
propagate through the shift register stages at a speed limited
only by the inherent propagation delay times associated with each
shift register stage;
(c) including logic combinational circuitry as part of said
LSI/VLSI circuitry that selectively allows said shift register
circuit to be configured as a ring oscillator in response to con-
trol signals generated by said shift register control circuit;
(d) placing input/output pads around the periphery of said
LSI/VLSI CMOS circuitry through which data signals and control
signals may be sent to or received from the shift register cir-
cuit, control circuit, and other circuitry forming part of said
LSI/VLSI circuitry;
(e) sending appropriate control signals to said shift regis-
ter control circuit to cause said shift register circuit to assume
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- 8c -
its second mode of operation;
(f) injecting a data signal into a first stage to shift reg-
ister circuit through one of said input/output pads; and
(g) measuring the period of oscillation associated with said
ring oscillator, said period of oscillation being related to the
delay time it takes said data signal to propagate through the
stages of said shift register circuit.
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BRIEF DESCRIPTION OF THE DRAWINGS
The above and other features, advantages, and objects of the
present invention will be better understood by the following more
detailed description of the invention presented in conjunction with
the accompanying drawings, in which:
Figure 1 is a diagrammatic top plan view of the chip of the
present invention.
Figure 2 is a schematic diagram of an input pad and associated
latch.
Figure 3 i9 a schematic diagram of an output pad and associated
latch.
Figure 4 is a block diagram showing the provision of
complementary inputs to the clock control circuitry.
Figure 5 is a schematic diagram of the input buffer circuit of
Figure 4.
Figure 6 is a schematic diagram of the clock control circuitry
used to generate timing signals to control the testing of the chip.
Figure 7 is a sohematic diagram of the output and input circuitry
of the test portion of the chip.
Figure 8 is a timing diagram showing the various operations of
the ring oscillator.
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-- 10 --
D ILED DESCRIPTION_
The following description is of the best presently
contemplated mode of carrying out the invention. The description
is made for the purpose of describing the general principles of
the invention and is not to be taken in a limiting sense. The
scope of the invention is best defined by the appended claims.
Referring to Figure 1, the present invention is part
of an integrated circuit 10 which includes internal circuitry 12
connected to a number of I/0 pads 14 by means of I/0 drivers 16.
The integrated circuit of the present embodiment uses CMOS VLSI
and has two hundred and fifty-six I/0 pads 14. Seven of the I/0
pads 14, labeled DI, A, B, C, D, E and DO are connected to the
tester input/output control and clock control circuitry 18. A
shift register 20, with a stage connected to each pad 14 (with the
exception of the test pads mentioned above and the pads dedicated
to ground and power supply connections) is formed around the per-
imeter of the chip 10. The shift register is normally used for
functionally testing the chip; however, in the present invention
the shift register is used as a ring oscillator when performing
delay measurements. These operations are all controlled by the
input/output control and clock control circuitry 18.
Figures 2 and 3 each show a shift register stage
and I/0 circuitry for an individual pad. Figure 2 shows a shift
register stage when it is associated with an input pad while
Figure 3 shows the configuration when the shift register staye is
associated with an output pad. Each shift
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register stage includes four inverters, 44-50, and six transmission
gates Tl-T6. In the present embodiment, the shift register is used
as a ring oscillator. In this application the transmission gates Tl,
T3 and T5 are turned on by control signals. This allows a signal
that is input at the first stage of the ring oscillator to be
propagated to the output of the last stage. Each stage has two
inverters so the output of the ring oscillator is the same polarity
as the input. The signal goes through five circuit delays at each
stage of the ring oscillator; that is, each of the three transmission
gates and the two inverters each have one circuit delay a~sociated
there with.
Referring to FIGURE 4, the input pads of the clock signals A, B,
C, D and E are each connected to an input buffer 22 which provides
protection and buffering for the input signals and complementary
output signals. FIGURE 5 shows the circuitry of one of the input
buffers. Input protection is provided by resistor 56 and diodes 58
and 59. The complementary signals are provided by inverters 52 and
54. The figure shows the input buffer for the signal A. The two
other signals that are true high, A and B, use identical circuitry.
The input buffers for the two signals, D and E, that are true low,
are identical except that the polarity of the output signals is
reversed. FIGURE 6 shows the clock decoding circuitry consists of
NAND gates 60-78 and inverters 80-106. This circuitry decodes tne
complementary clock signals from the input buffers, A-E, and
generates the signals AE, BE, CE, DE, R and their complements.
The following description uses an asterisk, *, to denote a logic
1~19~i8
signal that is true when its voltage level is low. For example, the
signal R is true when high while the signal R~ is true when low. The
use of the asterisk is identical to the bar over a signal name on a
circuit drawing. Since many signal names are a combination of
individual signal names, for example, the signal AE is the result of
the logical AND of the two signals A and E, parenthesis, ( ), are
sometimes used with the asterisk to avoid ambiguity. Thus, (AE)*
means the signal AE that is true when both A and E are low, while
(A)*E would be the signal that is true when A is low and E is high.
Referring to FIGURE 7, the Output Buffer 116 is driven by the
inverter 114 and the AND-OR-INVERT gate 112. The gate 112 selects
either DOI or DOE as inputs. DOI is the data-out signal from the
internal shift register of the chip 10, fabricated as part of the
internal circuitry 12. DOE is the data-out signal from the external
shift register 20. The transmissior. gates T3 and T4 and the two
inverters 108 and 110 are the slave latch of the last stage in the
external shift register. In the present embodiment, this is the ring
oscillator output. When E is true, DOE is selected for the Output
Buffer; when E is false, DOI is selected. The output, SO (Shift
~ut), of the AND-OR-INVERT gate 112 is inverted by the inverter 114
and goes to the output buffer and to the input select circuitry. The
AND-OR-INVERT gate 120 is used to select either (DI)* or SO. (DI)*
is the data-in signal from the tester and SO is the data-out signal
from the output select circuitry. The two transmission gates Tl and
T2 and the inverters 122 and 124 are the master latch of the first
stage of the external shift register .
L93~
When the signal R is true, SO is selected as the input; and when R is
false, (DI)* is selected. The three input NAND gate 78 and the
inverter 90 shown in FIGURE 6 are used to generate the signal R. R
will be true whenever A, B and C are true.
A timing diagram is shown in FIGURE 8. At time tl, the tester
raises the input signals A, 8 and E. The clock decoding circuitry of
FIGURE 6 decodes the signals A through E, and their complements,
from the input buffers shown in FIGURE 5~ and generates three high
level signals AE, BE and DE and a low level signal CE. These four
signals turn on the transmission gates labeled Tl, T3 and T5, shown
in FIGURES 2 and 3, and turn off the transmission gates T2 and T4.
This allows the signal at the output of the AND-OR-INVERT gate 120
(shown on FIGURE 7) to pass through the ring oscillator. Since the
signal C is low, the three input NAND gate 78 (FIGURE 6) will cause
R* to be high, causing (DI)* to be selected as the input to the ring
oscillator.
The signal (DI)*, inverted by the AND-OR-INVERT gate 120, passes
through the ring oscillator until it appears at the last stage as
DOE. Since the signal E is high, the output circuitry, shown in
FIGURE 7, will pass DOE on to the tester as the signal SO. The
tester, after detecting the arrival o~ SO, ra~ses the signal C. This
is shown at time t2 on FIGURE 8. Prior to time tl and after time t2,
the data-input signal DI is shown cross-hatched, indicating a
don't-care condition for the signal. When the signal C goes high,
the three input NAND gate 78 on FIGURE 6 will cause the slgnal h to
go high and R* to go low. The AND-OR-IN~ERT gate will then select
the signal SO instead of (DI)* as the input to the ring oscillator.
The signals AE, BE, CE and DE are not affected when the signal C goes
high so transmission gates Tl, T3 and T5
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14
remain turned on and T2 and T4 remain turned offO Since SO is the
inversion of (DI)* (inverted by the AND-OR-INVERT gate 120) the ring
oscillator will generate a square wave as the output signal SO is
inverted before being applied to the input again. The period of the
square wave is equal to two delay times through the ring oscillator
and the input and output select circuitry. The tester senses each
transition of the signal SO through the output circuitry shown in
Figure 7b and uses the time measured to determine the average circuit
delay for all of the circuits involved in the ring oscillator. The
ring oscillator will oscillate until the tester changes the timing
signals, A, B, C and D.
The ring oscillator produces a square wave for the tester to use
in its delay measurement. If a chip has 256-I/O pads, the ring
oscillator and additional circuitry has more than 1250 individual
circuit delays (two inverters and three transmission gates, each with
one circuit delay, per shift register stage). Since, as discussed
above, process variations in CMOS technology tend to affect all
circuits on a chip equally, the ring oscillator will multiply the
discrepancy in circuit delay by more than 1250, making it easier to
measure. The rlsing and falling edges of square wave output of the
ring oscillator will be degraded by the inductance of the probe,
turning it into a trapezoidal waveform with ringing superimposed on
it. However, the waveform is repetitious and it is only necessary to
trigger a counter at a given level on the rising or falling edge of
the waveform to determine the period of the waveform. Since each
transit through the ring oscillator cause~ an inversion, the total
delay through the circuits of the ring oscillator and additional
circuitry is one-half the period.
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The ring oscillator solves the problem of delay testing CMOS LSI
and VLSI chips when they are part of the wafer. Since CMOS circuitry
has the characteristic of little or no power consumption under DC
conditions, the ring oscillator does not add to the heat dissipation
of the chip when the chip is being used in its normal application.
The ring oscillator can also be used for delay testing at any
package level, i.e., integrated circuit package level, printed
circuit board level, or system level. CMOS circuitry is very
sensitive to voltage and temperature changes, that is, a decrease in
supply voltage or an increase in ambient temperature will cause the
circuit delays of CMOS to increase. The ring oscillator can be used
at the package level to detect a poor die bond, which would cause an
increase in chip temperature, or at the printed circuit board level
to detect a cold solder joint on a power pin, which would cause a low
voltage to the chip. The ring oscillator can also be used at the
system level to find hot-spots, caused by poor design or plugged
filters, or to check for low voltage, caused by poor design, poor
connections, low power supply voltage, etc. A record of the original
delay measured on the chip can be maintained and changes in the newly
measured value can be used to isolate the problem.
